| 1 | // Helper: |
| 2 | // |
| 3 | // Given an extended register number, translate it into an index into the |
| 4 | // register array. This is necessary as the upper 8 extended registers are |
| 5 | // actually synonyms for the d0-d3/a0-a3 registers. |
| 6 | // |
| 7 | // |
| 8 | |
| 9 | :function:::int:translate_rreg:int rreg |
| 10 | { |
| 11 | |
| 12 | /* The higher register numbers actually correspond to the |
| 13 | basic machine's address and data registers. */ |
| 14 | if (rreg > 7 && rreg < 12) |
| 15 | return REG_A0 + rreg - 8; |
| 16 | else if (rreg > 11 && rreg < 16) |
| 17 | return REG_D0 + rreg - 12; |
| 18 | else |
| 19 | return REG_E0 + rreg; |
| 20 | } |
| 21 | |
| 22 | :function:::int:translate_xreg:int xreg |
| 23 | { |
| 24 | switch (xreg) |
| 25 | { |
| 26 | case 0: |
| 27 | return REG_SP; |
| 28 | case 1: |
| 29 | return REG_MDRQ; |
| 30 | case 2: |
| 31 | return REG_MCRH; |
| 32 | case 3: |
| 33 | return REG_MCRL; |
| 34 | case 4: |
| 35 | return REG_MCVF; |
| 36 | default: |
| 37 | sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__); |
| 38 | } |
| 39 | } |
| 40 | |
| 41 | // 1111 0000 0010 00An; mov USP,An |
| 42 | 8.0xf0+4.0x2,00,2.AN0:D0m:::mov |
| 43 | "mov" |
| 44 | *am33 |
| 45 | *am33_2 |
| 46 | { |
| 47 | PC = cia; |
| 48 | State.regs[REG_A0 + AN0] = State.regs[REG_USP]; |
| 49 | } |
| 50 | |
| 51 | |
| 52 | // 1111 0000 0010 01An; mov SSP,An |
| 53 | 8.0xf0+4.0x2,01,2.AN0:D0n:::mov |
| 54 | "mov" |
| 55 | *am33 |
| 56 | *am33_2 |
| 57 | { |
| 58 | PC = cia; |
| 59 | State.regs[REG_A0 + AN0] = State.regs[REG_SSP]; |
| 60 | } |
| 61 | |
| 62 | |
| 63 | // 1111 0000 0010 10An; mov MSP,An |
| 64 | 8.0xf0+4.0x2,10,2.AN0:D0o:::mov |
| 65 | "mov" |
| 66 | *am33 |
| 67 | *am33_2 |
| 68 | { |
| 69 | PC = cia; |
| 70 | State.regs[REG_A0 + AN0] = State.regs[REG_MSP]; |
| 71 | } |
| 72 | |
| 73 | |
| 74 | // 1111 0000 0010 11An; mov PC,An |
| 75 | 8.0xf0+4.0x2,11,2.AN0:D0p:::mov |
| 76 | "mov" |
| 77 | *am33 |
| 78 | *am33_2 |
| 79 | { |
| 80 | PC = cia; |
| 81 | State.regs[REG_A0 + AN0] = PC; |
| 82 | } |
| 83 | |
| 84 | |
| 85 | // 1111 0000 0011 Am00; mov Am,USP |
| 86 | 8.0xf0+4.0x3,2.AM1,00:D0q:::mov |
| 87 | "mov" |
| 88 | *am33 |
| 89 | *am33_2 |
| 90 | { |
| 91 | PC = cia; |
| 92 | State.regs[REG_USP] = State.regs[REG_A0 + AM1]; |
| 93 | } |
| 94 | |
| 95 | // 1111 0000 0011 Am01; mov Am,SSP |
| 96 | 8.0xf0+4.0x3,2.AM1,01:D0r:::mov |
| 97 | "mov" |
| 98 | *am33 |
| 99 | *am33_2 |
| 100 | { |
| 101 | PC = cia; |
| 102 | State.regs[REG_SSP] = State.regs[REG_A0 + AM1]; |
| 103 | } |
| 104 | |
| 105 | // 1111 0000 0011 Am10; mov Am,MSP |
| 106 | 8.0xf0+4.0x3,2.AM1,10:D0s:::mov |
| 107 | "mov" |
| 108 | *am33 |
| 109 | *am33_2 |
| 110 | { |
| 111 | PC = cia; |
| 112 | State.regs[REG_MSP] = State.regs[REG_A0 + AM1]; |
| 113 | } |
| 114 | |
| 115 | |
| 116 | // 1111 0000 1110 imm4; syscall |
| 117 | 8.0xf0+4.0xe,IMM4:D0t:::syscall |
| 118 | "syscall" |
| 119 | *am33 |
| 120 | *am33_2 |
| 121 | { |
| 122 | unsigned32 sp, next_pc; |
| 123 | |
| 124 | PC = cia; |
| 125 | sp = State.regs[REG_SP]; |
| 126 | next_pc = State.regs[REG_PC] + 2; |
| 127 | store_word (sp - 4, next_pc); |
| 128 | store_word (sp - 8, PSW); |
| 129 | State.regs[REG_PC] = 0x40000000 + IMM4 * 8; |
| 130 | nia = PC; |
| 131 | } |
| 132 | |
| 133 | |
| 134 | // 1111 0010 1110 11Dn; mov EPSW,Dn |
| 135 | 8.0xf2+4.0xe,11,2.DN0:D0u:::mov |
| 136 | "mov" |
| 137 | *am33 |
| 138 | *am33_2 |
| 139 | { |
| 140 | PC = cia; |
| 141 | State.regs[REG_D0 + DN0] = PSW; |
| 142 | } |
| 143 | |
| 144 | |
| 145 | // 1111 0010 1111 Dm01; mov Dm,EPSW |
| 146 | 8.0xf2+4.0xf,2.DM1,01:D0v:::mov |
| 147 | "mov" |
| 148 | *am33 |
| 149 | *am33_2 |
| 150 | { |
| 151 | PC = cia; |
| 152 | PSW = State.regs[REG_D0 + DM1]; |
| 153 | } |
| 154 | |
| 155 | // 1111 0101 00Am Rn; mov Am,Rn |
| 156 | 8.0xf5+00,2.AM1,4.RN0:D0w:::mov |
| 157 | "mov" |
| 158 | *am33 |
| 159 | *am33_2 |
| 160 | { |
| 161 | int destreg = translate_rreg (SD_, RN0); |
| 162 | |
| 163 | PC = cia; |
| 164 | State.regs[destreg] = State.regs[REG_A0 + AM1]; |
| 165 | } |
| 166 | |
| 167 | // 1111 0101 01Dm Rn; mov Dm,Rn |
| 168 | 8.0xf5+01,2.DM1,4.RN0:D0x:::mov |
| 169 | "mov" |
| 170 | *am33 |
| 171 | *am33_2 |
| 172 | { |
| 173 | int destreg = translate_rreg (SD_, RN0); |
| 174 | |
| 175 | PC = cia; |
| 176 | State.regs[destreg] = State.regs[REG_D0 + DM1]; |
| 177 | } |
| 178 | |
| 179 | // 1111 0101 10Rm An; mov Rm,An |
| 180 | 8.0xf5+10,4.RM1,2.AN0:D0y:::mov |
| 181 | "mov" |
| 182 | *am33 |
| 183 | *am33_2 |
| 184 | { |
| 185 | int destreg = translate_rreg (SD_, RM1); |
| 186 | |
| 187 | PC = cia; |
| 188 | State.regs[REG_A0 + AN0] = State.regs[destreg]; |
| 189 | } |
| 190 | |
| 191 | // 1111 0101 11Rm Dn; mov Rm,Dn |
| 192 | 8.0xf5+11,4.RM1,2.DN0:D0z:::mov |
| 193 | "mov" |
| 194 | *am33 |
| 195 | *am33_2 |
| 196 | { |
| 197 | int destreg = translate_rreg (SD_, RM1); |
| 198 | |
| 199 | PC = cia; |
| 200 | State.regs[REG_D0 + DN0] = State.regs[destreg]; |
| 201 | } |
| 202 | |
| 203 | |
| 204 | // 1111 1000 1100 1110 regs....; movm (USP),regs |
| 205 | 8.0xf8+8.0xce+8.REGS:D1a:::movm |
| 206 | "movm" |
| 207 | *am33 |
| 208 | *am33_2 |
| 209 | { |
| 210 | unsigned32 usp = State.regs[REG_USP]; |
| 211 | unsigned32 mask; |
| 212 | |
| 213 | PC = cia; |
| 214 | mask = REGS; |
| 215 | |
| 216 | if (mask & 0x8) |
| 217 | { |
| 218 | usp += 4; |
| 219 | State.regs[REG_LAR] = load_word (usp); |
| 220 | usp += 4; |
| 221 | State.regs[REG_LIR] = load_word (usp); |
| 222 | usp += 4; |
| 223 | State.regs[REG_MDR] = load_word (usp); |
| 224 | usp += 4; |
| 225 | State.regs[REG_A0 + 1] = load_word (usp); |
| 226 | usp += 4; |
| 227 | State.regs[REG_A0] = load_word (usp); |
| 228 | usp += 4; |
| 229 | State.regs[REG_D0 + 1] = load_word (usp); |
| 230 | usp += 4; |
| 231 | State.regs[REG_D0] = load_word (usp); |
| 232 | usp += 4; |
| 233 | } |
| 234 | |
| 235 | if (mask & 0x10) |
| 236 | { |
| 237 | State.regs[REG_A0 + 3] = load_word (usp); |
| 238 | usp += 4; |
| 239 | } |
| 240 | |
| 241 | if (mask & 0x20) |
| 242 | { |
| 243 | State.regs[REG_A0 + 2] = load_word (usp); |
| 244 | usp += 4; |
| 245 | } |
| 246 | |
| 247 | if (mask & 0x40) |
| 248 | { |
| 249 | State.regs[REG_D0 + 3] = load_word (usp); |
| 250 | usp += 4; |
| 251 | } |
| 252 | |
| 253 | if (mask & 0x80) |
| 254 | { |
| 255 | State.regs[REG_D0 + 2] = load_word (usp); |
| 256 | usp += 4; |
| 257 | } |
| 258 | |
| 259 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33 |
| 260 | || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2 |
| 261 | ) |
| 262 | { |
| 263 | if (mask & 0x1) |
| 264 | { |
| 265 | /* Need to restore MDQR, MCRH, MCRL, and MCVF */ |
| 266 | usp += 16; |
| 267 | State.regs[REG_E0 + 1] = load_word (usp); |
| 268 | usp += 4; |
| 269 | State.regs[REG_E0 + 0] = load_word (usp); |
| 270 | usp += 4; |
| 271 | } |
| 272 | |
| 273 | if (mask & 0x2) |
| 274 | { |
| 275 | State.regs[REG_E0 + 7] = load_word (usp); |
| 276 | usp += 4; |
| 277 | State.regs[REG_E0 + 6] = load_word (usp); |
| 278 | usp += 4; |
| 279 | State.regs[REG_E0 + 5] = load_word (usp); |
| 280 | usp += 4; |
| 281 | State.regs[REG_E0 + 4] = load_word (usp); |
| 282 | usp += 4; |
| 283 | } |
| 284 | |
| 285 | if (mask & 0x4) |
| 286 | { |
| 287 | State.regs[REG_E0 + 3] = load_word (usp); |
| 288 | usp += 4; |
| 289 | State.regs[REG_E0 + 2] = load_word (usp); |
| 290 | usp += 4; |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | /* And make sure to update the stack pointer. */ |
| 295 | State.regs[REG_USP] = usp; |
| 296 | } |
| 297 | |
| 298 | // 1111 1000 1100 1111 regs....; movm (USP),regs |
| 299 | 8.0xf8+8.0xcf+8.REGS:D1b:::movm |
| 300 | "movm" |
| 301 | *am33 |
| 302 | *am33_2 |
| 303 | { |
| 304 | unsigned32 usp = State.regs[REG_USP]; |
| 305 | unsigned32 mask; |
| 306 | |
| 307 | PC = cia; |
| 308 | mask = REGS; |
| 309 | |
| 310 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33 |
| 311 | || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2 |
| 312 | ) |
| 313 | { |
| 314 | if (mask & 0x4) |
| 315 | { |
| 316 | usp -= 4; |
| 317 | store_word (usp, State.regs[REG_E0 + 2]); |
| 318 | usp -= 4; |
| 319 | store_word (usp, State.regs[REG_E0 + 3]); |
| 320 | } |
| 321 | |
| 322 | if (mask & 0x2) |
| 323 | { |
| 324 | usp -= 4; |
| 325 | store_word (usp, State.regs[REG_E0 + 4]); |
| 326 | usp -= 4; |
| 327 | store_word (usp, State.regs[REG_E0 + 5]); |
| 328 | usp -= 4; |
| 329 | store_word (usp, State.regs[REG_E0 + 6]); |
| 330 | usp -= 4; |
| 331 | store_word (usp, State.regs[REG_E0 + 7]); |
| 332 | } |
| 333 | |
| 334 | if (mask & 0x1) |
| 335 | { |
| 336 | usp -= 4; |
| 337 | store_word (usp, State.regs[REG_E0 + 0]); |
| 338 | usp -= 4; |
| 339 | store_word (usp, State.regs[REG_E0 + 1]); |
| 340 | usp -= 16; |
| 341 | /* Need to save MDQR, MCRH, MCRL, and MCVF */ |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | if (mask & 0x80) |
| 346 | { |
| 347 | usp -= 4; |
| 348 | store_word (usp, State.regs[REG_D0 + 2]); |
| 349 | } |
| 350 | |
| 351 | if (mask & 0x40) |
| 352 | { |
| 353 | usp -= 4; |
| 354 | store_word (usp, State.regs[REG_D0 + 3]); |
| 355 | } |
| 356 | |
| 357 | if (mask & 0x20) |
| 358 | { |
| 359 | usp -= 4; |
| 360 | store_word (usp, State.regs[REG_A0 + 2]); |
| 361 | } |
| 362 | |
| 363 | if (mask & 0x10) |
| 364 | { |
| 365 | usp -= 4; |
| 366 | store_word (usp, State.regs[REG_A0 + 3]); |
| 367 | } |
| 368 | |
| 369 | if (mask & 0x8) |
| 370 | { |
| 371 | usp -= 4; |
| 372 | store_word (usp, State.regs[REG_D0]); |
| 373 | usp -= 4; |
| 374 | store_word (usp, State.regs[REG_D0 + 1]); |
| 375 | usp -= 4; |
| 376 | store_word (usp, State.regs[REG_A0]); |
| 377 | usp -= 4; |
| 378 | store_word (usp, State.regs[REG_A0 + 1]); |
| 379 | usp -= 4; |
| 380 | store_word (usp, State.regs[REG_MDR]); |
| 381 | usp -= 4; |
| 382 | store_word (usp, State.regs[REG_LIR]); |
| 383 | usp -= 4; |
| 384 | store_word (usp, State.regs[REG_LAR]); |
| 385 | usp -= 4; |
| 386 | } |
| 387 | |
| 388 | /* And make sure to update the stack pointer. */ |
| 389 | State.regs[REG_USP] = usp; |
| 390 | } |
| 391 | |
| 392 | // 1111 1100 1111 1100 imm32...; and imm32,EPSW |
| 393 | 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and |
| 394 | "and" |
| 395 | *am33 |
| 396 | *am33_2 |
| 397 | { |
| 398 | PC = cia; |
| 399 | PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); |
| 400 | } |
| 401 | |
| 402 | // 1111 1100 1111 1101 imm32...; or imm32,EPSW |
| 403 | 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or |
| 404 | "or" |
| 405 | *am33 |
| 406 | *am33_2 |
| 407 | { |
| 408 | PC = cia; |
| 409 | PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); |
| 410 | } |
| 411 | |
| 412 | // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn) |
| 413 | 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov |
| 414 | "mov" |
| 415 | *am33 |
| 416 | *am33_2 |
| 417 | { |
| 418 | int srcreg, dstreg; |
| 419 | |
| 420 | PC = cia; |
| 421 | |
| 422 | srcreg = translate_rreg (SD_, RM2); |
| 423 | dstreg = translate_rreg (SD_, RN0); |
| 424 | State.regs[dstreg] = State.regs[srcreg]; |
| 425 | } |
| 426 | |
| 427 | // 1111 1001 0001 1000 Rn Rn; ext Rn |
| 428 | 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext |
| 429 | "mov" |
| 430 | *am33 |
| 431 | *am33_2 |
| 432 | { |
| 433 | int srcreg; |
| 434 | |
| 435 | PC = cia; |
| 436 | srcreg = translate_rreg (SD_, RN0); |
| 437 | if (State.regs[srcreg] & 0x80000000) |
| 438 | State.regs[REG_MDR] = -1; |
| 439 | else |
| 440 | State.regs[REG_MDR] = 0; |
| 441 | } |
| 442 | |
| 443 | // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn |
| 444 | 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb |
| 445 | "extb" |
| 446 | *am33 |
| 447 | *am33_2 |
| 448 | { |
| 449 | int srcreg, dstreg; |
| 450 | |
| 451 | PC = cia; |
| 452 | srcreg = translate_rreg (SD_, RM2); |
| 453 | dstreg = translate_rreg (SD_, RN0); |
| 454 | State.regs[dstreg] = EXTEND8 (State.regs[srcreg]); |
| 455 | } |
| 456 | |
| 457 | // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn |
| 458 | 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu |
| 459 | "extbu" |
| 460 | *am33 |
| 461 | *am33_2 |
| 462 | { |
| 463 | int srcreg, dstreg; |
| 464 | |
| 465 | PC = cia; |
| 466 | srcreg = translate_rreg (SD_, RM2); |
| 467 | dstreg = translate_rreg (SD_, RN0); |
| 468 | State.regs[dstreg] = State.regs[srcreg] & 0xff; |
| 469 | } |
| 470 | |
| 471 | // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn |
| 472 | 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth |
| 473 | "exth" |
| 474 | *am33 |
| 475 | *am33_2 |
| 476 | { |
| 477 | int srcreg, dstreg; |
| 478 | |
| 479 | PC = cia; |
| 480 | srcreg = translate_rreg (SD_, RM2); |
| 481 | dstreg = translate_rreg (SD_, RN0); |
| 482 | State.regs[dstreg] = EXTEND16 (State.regs[srcreg]); |
| 483 | } |
| 484 | |
| 485 | // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn |
| 486 | 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu |
| 487 | "exthu" |
| 488 | *am33 |
| 489 | *am33_2 |
| 490 | { |
| 491 | int srcreg, dstreg; |
| 492 | |
| 493 | PC = cia; |
| 494 | srcreg = translate_rreg (SD_, RM2); |
| 495 | dstreg = translate_rreg (SD_, RN0); |
| 496 | State.regs[dstreg] = State.regs[srcreg] & 0xffff; |
| 497 | } |
| 498 | |
| 499 | // 1111 1001 0110 1000 Rn Rn; clr Rn |
| 500 | 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr |
| 501 | "clr" |
| 502 | *am33 |
| 503 | *am33_2 |
| 504 | { |
| 505 | int dstreg; |
| 506 | |
| 507 | PC = cia; |
| 508 | dstreg = translate_rreg (SD_, RN0); |
| 509 | State.regs[dstreg] = 0; |
| 510 | PSW |= PSW_Z; |
| 511 | PSW &= ~(PSW_V | PSW_C | PSW_N); |
| 512 | } |
| 513 | |
| 514 | // 1111 1001 0111 1000 Rm Rn; add Rm,Rn |
| 515 | 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add |
| 516 | "add" |
| 517 | *am33 |
| 518 | *am33_2 |
| 519 | { |
| 520 | int srcreg, dstreg; |
| 521 | |
| 522 | PC = cia; |
| 523 | srcreg = translate_rreg (SD_, RM2); |
| 524 | dstreg = translate_rreg (SD_, RN0); |
| 525 | genericAdd (State.regs[srcreg], dstreg); |
| 526 | } |
| 527 | |
| 528 | // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn |
| 529 | 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc |
| 530 | "addc" |
| 531 | *am33 |
| 532 | *am33_2 |
| 533 | { |
| 534 | int srcreg, dstreg; |
| 535 | int z, c, n, v; |
| 536 | unsigned32 reg1, reg2, sum; |
| 537 | |
| 538 | PC = cia; |
| 539 | srcreg = translate_rreg (SD_, RM2); |
| 540 | dstreg = translate_rreg (SD_, RN0); |
| 541 | |
| 542 | reg1 = State.regs[srcreg]; |
| 543 | reg2 = State.regs[dstreg]; |
| 544 | sum = reg1 + reg2 + ((PSW & PSW_C) != 0); |
| 545 | State.regs[dstreg] = sum; |
| 546 | |
| 547 | z = ((PSW & PSW_Z) != 0) && (sum == 0); |
| 548 | n = (sum & 0x80000000); |
| 549 | c = (sum < reg1) || (sum < reg2); |
| 550 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
| 551 | && (reg2 & 0x80000000) != (sum & 0x80000000)); |
| 552 | |
| 553 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 554 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 555 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 556 | } |
| 557 | |
| 558 | // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn |
| 559 | 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub |
| 560 | "sub" |
| 561 | *am33 |
| 562 | *am33_2 |
| 563 | { |
| 564 | int srcreg, dstreg; |
| 565 | |
| 566 | PC = cia; |
| 567 | srcreg = translate_rreg (SD_, RM2); |
| 568 | dstreg = translate_rreg (SD_, RN0); |
| 569 | genericSub (State.regs[srcreg], dstreg); |
| 570 | } |
| 571 | |
| 572 | // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn |
| 573 | 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc |
| 574 | "subc" |
| 575 | *am33 |
| 576 | *am33_2 |
| 577 | { |
| 578 | int srcreg, dstreg; |
| 579 | int z, c, n, v; |
| 580 | unsigned32 reg1, reg2, difference; |
| 581 | |
| 582 | PC = cia; |
| 583 | srcreg = translate_rreg (SD_, RM2); |
| 584 | dstreg = translate_rreg (SD_, RN0); |
| 585 | |
| 586 | reg1 = State.regs[srcreg]; |
| 587 | reg2 = State.regs[dstreg]; |
| 588 | difference = reg2 - reg1 - ((PSW & PSW_C) != 0); |
| 589 | State.regs[dstreg] = difference; |
| 590 | |
| 591 | z = ((PSW & PSW_Z) != 0) && (difference == 0); |
| 592 | n = (difference & 0x80000000); |
| 593 | c = (reg1 > reg2); |
| 594 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
| 595 | && (reg2 & 0x80000000) != (difference & 0x80000000)); |
| 596 | |
| 597 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 598 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 599 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 600 | } |
| 601 | |
| 602 | // 1111 1001 1011 1000 Rn Rn; inc Rn |
| 603 | 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc |
| 604 | "inc" |
| 605 | *am33 |
| 606 | *am33_2 |
| 607 | { |
| 608 | int dstreg; |
| 609 | |
| 610 | PC = cia; |
| 611 | dstreg = translate_rreg (SD_, RN0); |
| 612 | genericAdd (1, dstreg); |
| 613 | } |
| 614 | |
| 615 | // 1111 1001 1101 1000 Rn Rn; inc Rn |
| 616 | 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4 |
| 617 | "inc4" |
| 618 | *am33 |
| 619 | *am33_2 |
| 620 | { |
| 621 | int dstreg; |
| 622 | |
| 623 | PC = cia; |
| 624 | dstreg = translate_rreg (SD_, RN0); |
| 625 | genericAdd (4, dstreg); |
| 626 | } |
| 627 | |
| 628 | // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn |
| 629 | 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp |
| 630 | "cmp" |
| 631 | *am33 |
| 632 | *am33_2 |
| 633 | { |
| 634 | int srcreg1, srcreg2; |
| 635 | |
| 636 | PC = cia; |
| 637 | srcreg1 = translate_rreg (SD_, RN0); |
| 638 | srcreg2 = translate_rreg (SD_, RM2); |
| 639 | genericCmp (State.regs[srcreg2], State.regs[srcreg1]); |
| 640 | } |
| 641 | |
| 642 | // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn |
| 643 | 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov |
| 644 | "mov" |
| 645 | *am33 |
| 646 | *am33_2 |
| 647 | { |
| 648 | int dstreg, srcreg; |
| 649 | |
| 650 | PC = cia; |
| 651 | dstreg = translate_rreg (SD_, RN0); |
| 652 | srcreg = translate_xreg (SD_, XRM2); |
| 653 | |
| 654 | State.regs[dstreg] = State.regs[srcreg]; |
| 655 | } |
| 656 | |
| 657 | // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn |
| 658 | 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov |
| 659 | "mov" |
| 660 | *am33 |
| 661 | *am33_2 |
| 662 | { |
| 663 | int srcreg, dstreg; |
| 664 | |
| 665 | PC = cia; |
| 666 | srcreg = translate_rreg (SD_, RM2); |
| 667 | dstreg = translate_xreg (SD_, XRN0); |
| 668 | |
| 669 | State.regs[dstreg] = State.regs[srcreg]; |
| 670 | } |
| 671 | |
| 672 | // 1111 1001 0000 1001 Rm Rn; and Rm,Rn |
| 673 | 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and |
| 674 | "and" |
| 675 | *am33 |
| 676 | *am33_2 |
| 677 | { |
| 678 | int srcreg, dstreg; |
| 679 | int z, n; |
| 680 | |
| 681 | PC = cia; |
| 682 | |
| 683 | srcreg = translate_rreg (SD_, RM2); |
| 684 | dstreg = translate_rreg (SD_, RN0); |
| 685 | |
| 686 | State.regs[dstreg] &= State.regs[srcreg]; |
| 687 | z = (State.regs[dstreg] == 0); |
| 688 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 689 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 690 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 691 | } |
| 692 | |
| 693 | // 1111 1001 0001 1001 Rm Rn; or Rm,Rn |
| 694 | 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or |
| 695 | "or" |
| 696 | *am33 |
| 697 | *am33_2 |
| 698 | { |
| 699 | int srcreg, dstreg; |
| 700 | int z, n; |
| 701 | |
| 702 | PC = cia; |
| 703 | srcreg = translate_rreg (SD_, RM2); |
| 704 | dstreg = translate_rreg (SD_, RN0); |
| 705 | |
| 706 | State.regs[dstreg] |= State.regs[srcreg]; |
| 707 | z = (State.regs[dstreg] == 0); |
| 708 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 709 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 710 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 711 | } |
| 712 | |
| 713 | // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn |
| 714 | 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor |
| 715 | "xor" |
| 716 | *am33 |
| 717 | *am33_2 |
| 718 | { |
| 719 | int srcreg, dstreg; |
| 720 | int z, n; |
| 721 | |
| 722 | PC = cia; |
| 723 | srcreg = translate_rreg (SD_, RM2); |
| 724 | dstreg = translate_rreg (SD_, RN0); |
| 725 | |
| 726 | State.regs[dstreg] ^= State.regs[srcreg]; |
| 727 | z = (State.regs[dstreg] == 0); |
| 728 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 729 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 730 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 731 | } |
| 732 | |
| 733 | // 1111 1001 0011 1001 Rn Rn; not Rn |
| 734 | 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not |
| 735 | "not" |
| 736 | *am33 |
| 737 | *am33_2 |
| 738 | { |
| 739 | int dstreg; |
| 740 | int z, n; |
| 741 | |
| 742 | PC = cia; |
| 743 | dstreg = translate_rreg (SD_, RN0); |
| 744 | |
| 745 | State.regs[dstreg] = ~State.regs[dstreg]; |
| 746 | z = (State.regs[dstreg] == 0); |
| 747 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 748 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 749 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 750 | } |
| 751 | |
| 752 | // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn |
| 753 | 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr |
| 754 | "asr" |
| 755 | *am33 |
| 756 | *am33_2 |
| 757 | { |
| 758 | int srcreg, dstreg; |
| 759 | signed32 temp; |
| 760 | int c, z, n; |
| 761 | |
| 762 | PC = cia; |
| 763 | srcreg = translate_rreg (SD_, RM2); |
| 764 | dstreg = translate_rreg (SD_, RN0); |
| 765 | |
| 766 | temp = State.regs[dstreg]; |
| 767 | c = temp & 1; |
| 768 | temp >>= State.regs[srcreg]; |
| 769 | State.regs[dstreg] = temp; |
| 770 | z = (State.regs[dstreg] == 0); |
| 771 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 772 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 773 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 774 | } |
| 775 | |
| 776 | // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn |
| 777 | 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr |
| 778 | "lsr" |
| 779 | *am33 |
| 780 | *am33_2 |
| 781 | { |
| 782 | int srcreg, dstreg; |
| 783 | int z, n, c; |
| 784 | |
| 785 | PC = cia; |
| 786 | |
| 787 | srcreg = translate_rreg (SD_, RM2); |
| 788 | dstreg = translate_rreg (SD_, RN0); |
| 789 | |
| 790 | c = State.regs[dstreg] & 1; |
| 791 | State.regs[dstreg] >>= State.regs[srcreg]; |
| 792 | z = (State.regs[dstreg] == 0); |
| 793 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 794 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 795 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 796 | } |
| 797 | |
| 798 | // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn |
| 799 | 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl |
| 800 | "asl" |
| 801 | *am33 |
| 802 | *am33_2 |
| 803 | { |
| 804 | int srcreg, dstreg; |
| 805 | int z, n; |
| 806 | |
| 807 | PC = cia; |
| 808 | srcreg = translate_rreg (SD_, RM2); |
| 809 | dstreg = translate_rreg (SD_, RN0); |
| 810 | |
| 811 | State.regs[dstreg] <<= State.regs[srcreg]; |
| 812 | z = (State.regs[dstreg] == 0); |
| 813 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 814 | PSW &= ~(PSW_Z | PSW_N); |
| 815 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 816 | } |
| 817 | |
| 818 | // 1111 1001 0111 1001 Rn Rn; asl2 Rn |
| 819 | 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2 |
| 820 | "asl2" |
| 821 | *am33 |
| 822 | *am33_2 |
| 823 | { |
| 824 | int dstreg; |
| 825 | int n, z; |
| 826 | |
| 827 | PC = cia; |
| 828 | dstreg = translate_rreg (SD_, RN0); |
| 829 | |
| 830 | State.regs[dstreg] <<= 2; |
| 831 | z = (State.regs[dstreg] == 0); |
| 832 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 833 | PSW &= ~(PSW_Z | PSW_N); |
| 834 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 835 | } |
| 836 | |
| 837 | // 1111 1001 1000 1001 Rn Rn; ror Rn |
| 838 | 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror |
| 839 | "ror" |
| 840 | *am33 |
| 841 | *am33_2 |
| 842 | { |
| 843 | int dstreg; |
| 844 | int c, n, z; |
| 845 | unsigned32 value; |
| 846 | |
| 847 | PC = cia; |
| 848 | dstreg = translate_rreg (SD_, RN0); |
| 849 | |
| 850 | value = State.regs[dstreg]; |
| 851 | c = (value & 0x1); |
| 852 | |
| 853 | value >>= 1; |
| 854 | value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; |
| 855 | State.regs[dstreg] = value; |
| 856 | z = (value == 0); |
| 857 | n = (value & 0x80000000) != 0; |
| 858 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 859 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 860 | } |
| 861 | |
| 862 | // 1111 1001 1001 1001 Rn Rn; rol Rn |
| 863 | 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol |
| 864 | "rol" |
| 865 | *am33 |
| 866 | *am33_2 |
| 867 | { |
| 868 | int dstreg; |
| 869 | int c, n, z; |
| 870 | unsigned32 value; |
| 871 | |
| 872 | PC = cia; |
| 873 | dstreg = translate_rreg (SD_, RN0); |
| 874 | |
| 875 | value = State.regs[dstreg]; |
| 876 | c = (value & 0x80000000) ? 1 : 0; |
| 877 | |
| 878 | value <<= 1; |
| 879 | value |= ((PSW & PSW_C) != 0); |
| 880 | State.regs[dstreg] = value; |
| 881 | z = (value == 0); |
| 882 | n = (value & 0x80000000) != 0; |
| 883 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 884 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 885 | } |
| 886 | |
| 887 | // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn |
| 888 | 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul |
| 889 | "mul" |
| 890 | *am33 |
| 891 | *am33_2 |
| 892 | { |
| 893 | int srcreg, dstreg; |
| 894 | unsigned64 temp; |
| 895 | int n, z; |
| 896 | |
| 897 | PC = cia; |
| 898 | srcreg = translate_rreg (SD_, RM2); |
| 899 | dstreg = translate_rreg (SD_, RN0); |
| 900 | |
| 901 | temp = ((signed64)(signed32)State.regs[dstreg] |
| 902 | * (signed64)(signed32)State.regs[srcreg]); |
| 903 | State.regs[dstreg] = temp & 0xffffffff; |
| 904 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 905 | z = (State.regs[dstreg] == 0); |
| 906 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 907 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 908 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 909 | } |
| 910 | |
| 911 | // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn |
| 912 | 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu |
| 913 | "mulu" |
| 914 | *am33 |
| 915 | *am33_2 |
| 916 | { |
| 917 | int srcreg, dstreg; |
| 918 | unsigned64 temp; |
| 919 | int n, z; |
| 920 | |
| 921 | PC = cia; |
| 922 | srcreg = translate_rreg (SD_, RM2); |
| 923 | dstreg = translate_rreg (SD_, RN0); |
| 924 | |
| 925 | temp = ((unsigned64)State.regs[dstreg] |
| 926 | * (unsigned64)State.regs[srcreg]); |
| 927 | State.regs[dstreg] = temp & 0xffffffff; |
| 928 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 929 | z = (State.regs[dstreg] == 0); |
| 930 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 931 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 932 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 933 | } |
| 934 | |
| 935 | // 1111 1001 1100 1001 Rm Rn; div Rm,Rn |
| 936 | 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div |
| 937 | "div" |
| 938 | *am33 |
| 939 | *am33_2 |
| 940 | { |
| 941 | int srcreg, dstreg; |
| 942 | signed64 temp; |
| 943 | int n, z; |
| 944 | |
| 945 | PC = cia; |
| 946 | srcreg = translate_rreg (SD_, RM2); |
| 947 | dstreg = translate_rreg (SD_, RN0); |
| 948 | |
| 949 | temp = State.regs[REG_MDR]; |
| 950 | temp <<= 32; |
| 951 | temp |= State.regs[dstreg]; |
| 952 | State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg]; |
| 953 | temp /= (signed32)State.regs[srcreg]; |
| 954 | State.regs[dstreg] = temp & 0xffffffff; |
| 955 | z = (State.regs[dstreg] == 0); |
| 956 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 957 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 958 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 959 | } |
| 960 | |
| 961 | // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn |
| 962 | 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu |
| 963 | "divu" |
| 964 | *am33 |
| 965 | *am33_2 |
| 966 | { |
| 967 | int srcreg, dstreg; |
| 968 | unsigned64 temp; |
| 969 | int n, z; |
| 970 | |
| 971 | PC = cia; |
| 972 | srcreg = translate_rreg (SD_, RM2); |
| 973 | dstreg = translate_rreg (SD_, RN0); |
| 974 | |
| 975 | temp = State.regs[REG_MDR]; |
| 976 | temp <<= 32; |
| 977 | temp |= State.regs[dstreg]; |
| 978 | State.regs[REG_MDR] = temp % State.regs[srcreg]; |
| 979 | temp /= State.regs[srcreg]; |
| 980 | State.regs[dstreg] = temp & 0xffffffff; |
| 981 | z = (State.regs[dstreg] == 0); |
| 982 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 983 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 984 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 985 | } |
| 986 | |
| 987 | |
| 988 | // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn |
| 989 | 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov |
| 990 | "mov" |
| 991 | *am33 |
| 992 | *am33_2 |
| 993 | { |
| 994 | int srcreg, dstreg; |
| 995 | |
| 996 | PC = cia; |
| 997 | srcreg = translate_rreg (SD_, RM0); |
| 998 | dstreg = translate_rreg (SD_, RN2); |
| 999 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 1000 | } |
| 1001 | |
| 1002 | // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn) |
| 1003 | 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov |
| 1004 | "mov" |
| 1005 | *am33 |
| 1006 | *am33_2 |
| 1007 | { |
| 1008 | int srcreg, dstreg; |
| 1009 | |
| 1010 | PC = cia; |
| 1011 | srcreg = translate_rreg (SD_, RM2); |
| 1012 | dstreg = translate_rreg (SD_, RN0); |
| 1013 | store_word (State.regs[dstreg], State.regs[srcreg]); |
| 1014 | } |
| 1015 | |
| 1016 | // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn |
| 1017 | 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu |
| 1018 | "movbu" |
| 1019 | *am33 |
| 1020 | *am33_2 |
| 1021 | { |
| 1022 | int srcreg, dstreg; |
| 1023 | |
| 1024 | PC = cia; |
| 1025 | srcreg = translate_rreg (SD_, RM0); |
| 1026 | dstreg = translate_rreg (SD_, RN2); |
| 1027 | State.regs[dstreg] = load_byte (State.regs[srcreg]); |
| 1028 | } |
| 1029 | |
| 1030 | // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn) |
| 1031 | 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu |
| 1032 | "movbu" |
| 1033 | *am33 |
| 1034 | *am33_2 |
| 1035 | { |
| 1036 | int srcreg, dstreg; |
| 1037 | |
| 1038 | PC = cia; |
| 1039 | srcreg = translate_rreg (SD_, RM2); |
| 1040 | dstreg = translate_rreg (SD_, RN0); |
| 1041 | store_byte (State.regs[dstreg], State.regs[srcreg]); |
| 1042 | } |
| 1043 | |
| 1044 | // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn |
| 1045 | 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu |
| 1046 | "movhu" |
| 1047 | *am33 |
| 1048 | *am33_2 |
| 1049 | { |
| 1050 | int srcreg, dstreg; |
| 1051 | |
| 1052 | PC = cia; |
| 1053 | srcreg = translate_rreg (SD_, RM0); |
| 1054 | dstreg = translate_rreg (SD_, RN2); |
| 1055 | State.regs[dstreg] = load_half (State.regs[srcreg]); |
| 1056 | } |
| 1057 | |
| 1058 | // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn) |
| 1059 | 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu |
| 1060 | "movhu" |
| 1061 | *am33 |
| 1062 | *am33_2 |
| 1063 | { |
| 1064 | int srcreg, dstreg; |
| 1065 | |
| 1066 | PC = cia; |
| 1067 | srcreg = translate_rreg (SD_, RM2); |
| 1068 | dstreg = translate_rreg (SD_, RN0); |
| 1069 | store_half (State.regs[dstreg], State.regs[srcreg]); |
| 1070 | } |
| 1071 | |
| 1072 | // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn |
| 1073 | 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov |
| 1074 | "mov" |
| 1075 | *am33 |
| 1076 | *am33_2 |
| 1077 | { |
| 1078 | int srcreg, dstreg; |
| 1079 | |
| 1080 | PC = cia; |
| 1081 | srcreg = translate_rreg (SD_, RM0); |
| 1082 | dstreg = translate_rreg (SD_, RN2); |
| 1083 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 1084 | State.regs[srcreg] += 4; |
| 1085 | } |
| 1086 | |
| 1087 | // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+) |
| 1088 | 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov |
| 1089 | "mov" |
| 1090 | *am33 |
| 1091 | *am33_2 |
| 1092 | { |
| 1093 | int srcreg, dstreg; |
| 1094 | |
| 1095 | PC = cia; |
| 1096 | srcreg = translate_rreg (SD_, RM2); |
| 1097 | dstreg = translate_rreg (SD_, RN0); |
| 1098 | store_word (State.regs[dstreg], State.regs[srcreg]); |
| 1099 | State.regs[dstreg] += 4; |
| 1100 | } |
| 1101 | |
| 1102 | // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn |
| 1103 | 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov |
| 1104 | "mov" |
| 1105 | *am33 |
| 1106 | *am33_2 |
| 1107 | { |
| 1108 | int dstreg; |
| 1109 | |
| 1110 | PC = cia; |
| 1111 | dstreg = translate_rreg (SD_, RN2); |
| 1112 | State.regs[dstreg] = load_word (State.regs[REG_SP]); |
| 1113 | } |
| 1114 | |
| 1115 | // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp) |
| 1116 | 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov |
| 1117 | "mov" |
| 1118 | *am33 |
| 1119 | *am33_2 |
| 1120 | { |
| 1121 | int srcreg; |
| 1122 | |
| 1123 | PC = cia; |
| 1124 | srcreg = translate_rreg (SD_, RM2); |
| 1125 | store_word (State.regs[REG_SP], State.regs[srcreg]); |
| 1126 | } |
| 1127 | |
| 1128 | // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn |
| 1129 | 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu |
| 1130 | "movbu" |
| 1131 | *am33 |
| 1132 | *am33_2 |
| 1133 | { |
| 1134 | int dstreg; |
| 1135 | |
| 1136 | PC = cia; |
| 1137 | dstreg = translate_rreg (SD_, RN2); |
| 1138 | State.regs[dstreg] = load_byte (State.regs[REG_SP]); |
| 1139 | } |
| 1140 | |
| 1141 | // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp) |
| 1142 | 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu |
| 1143 | "movbu" |
| 1144 | *am33 |
| 1145 | *am33_2 |
| 1146 | { |
| 1147 | int srcreg; |
| 1148 | |
| 1149 | PC = cia; |
| 1150 | srcreg = translate_rreg (SD_, RM2); |
| 1151 | store_byte (State.regs[REG_SP], State.regs[srcreg]); |
| 1152 | } |
| 1153 | |
| 1154 | // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn |
| 1155 | 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu |
| 1156 | "movhu" |
| 1157 | *am33 |
| 1158 | *am33_2 |
| 1159 | { |
| 1160 | int dstreg; |
| 1161 | |
| 1162 | PC = cia; |
| 1163 | dstreg = translate_rreg (SD_, RN2); |
| 1164 | State.regs[dstreg] = load_half (State.regs[REG_SP]); |
| 1165 | } |
| 1166 | |
| 1167 | // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp) |
| 1168 | 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu |
| 1169 | "movhu" |
| 1170 | *am33 |
| 1171 | *am33_2 |
| 1172 | { |
| 1173 | int srcreg; |
| 1174 | |
| 1175 | PC = cia; |
| 1176 | srcreg = translate_rreg (SD_, RM2); |
| 1177 | store_half (State.regs[REG_SP], State.regs[srcreg]); |
| 1178 | } |
| 1179 | |
| 1180 | // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn |
| 1181 | 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu |
| 1182 | "movhu" |
| 1183 | *am33 |
| 1184 | *am33_2 |
| 1185 | { |
| 1186 | int srcreg, dstreg; |
| 1187 | |
| 1188 | PC = cia; |
| 1189 | srcreg = translate_rreg (SD_, RM0); |
| 1190 | dstreg = translate_rreg (SD_, RN2); |
| 1191 | State.regs[dstreg] = load_half (State.regs[srcreg]); |
| 1192 | State.regs[srcreg] += 2; |
| 1193 | } |
| 1194 | |
| 1195 | // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+) |
| 1196 | 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu |
| 1197 | "movhu" |
| 1198 | *am33 |
| 1199 | *am33_2 |
| 1200 | { |
| 1201 | int srcreg, dstreg; |
| 1202 | |
| 1203 | PC = cia; |
| 1204 | srcreg = translate_rreg (SD_, RM2); |
| 1205 | dstreg = translate_rreg (SD_, RN0); |
| 1206 | store_half (State.regs[dstreg], State.regs[srcreg]); |
| 1207 | State.regs[dstreg] += 2; |
| 1208 | } |
| 1209 | |
| 1210 | |
| 1211 | // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn |
| 1212 | 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac |
| 1213 | "mac" |
| 1214 | *am33 |
| 1215 | *am33_2 |
| 1216 | { |
| 1217 | int srcreg1, srcreg2; |
| 1218 | signed64 temp, sum; |
| 1219 | int c, v; |
| 1220 | |
| 1221 | PC = cia; |
| 1222 | srcreg1 = translate_rreg (SD_, RM2); |
| 1223 | srcreg2 = translate_rreg (SD_, RN0); |
| 1224 | |
| 1225 | temp = ((signed64)(signed32)State.regs[srcreg2] |
| 1226 | * (signed64)(signed32)State.regs[srcreg1]); |
| 1227 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 1228 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 1229 | State.regs[REG_MCRL] = sum; |
| 1230 | temp >>= 32; |
| 1231 | temp &= 0xffffffff; |
| 1232 | sum = State.regs[REG_MCRH] + temp + c; |
| 1233 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 1234 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1235 | State.regs[REG_MCRH] = sum; |
| 1236 | if (v) |
| 1237 | State.regs[REG_MCVF] = 1; |
| 1238 | } |
| 1239 | |
| 1240 | // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn |
| 1241 | 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu |
| 1242 | "macu" |
| 1243 | *am33 |
| 1244 | *am33_2 |
| 1245 | { |
| 1246 | int srcreg1, srcreg2; |
| 1247 | unsigned64 temp, sum; |
| 1248 | int c, v; |
| 1249 | |
| 1250 | PC = cia; |
| 1251 | srcreg1 = translate_rreg (SD_, RM2); |
| 1252 | srcreg2 = translate_rreg (SD_, RN0); |
| 1253 | |
| 1254 | temp = ((unsigned64)State.regs[srcreg2] |
| 1255 | * (unsigned64)State.regs[srcreg1]); |
| 1256 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 1257 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 1258 | State.regs[REG_MCRL] = sum; |
| 1259 | temp >>= 32; |
| 1260 | temp &= 0xffffffff; |
| 1261 | sum = State.regs[REG_MCRH] + temp + c; |
| 1262 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 1263 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1264 | State.regs[REG_MCRH] = sum; |
| 1265 | if (v) |
| 1266 | State.regs[REG_MCVF] = 1; |
| 1267 | } |
| 1268 | |
| 1269 | // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn |
| 1270 | 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb |
| 1271 | "macb" |
| 1272 | *am33 |
| 1273 | *am33_2 |
| 1274 | { |
| 1275 | int srcreg1, srcreg2; |
| 1276 | signed32 temp, sum; |
| 1277 | int v; |
| 1278 | |
| 1279 | PC = cia; |
| 1280 | srcreg1 = translate_rreg (SD_, RM2); |
| 1281 | srcreg2 = translate_rreg (SD_, RN0); |
| 1282 | |
| 1283 | temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff) |
| 1284 | * (signed32)(signed8)(State.regs[srcreg1] & 0xff)); |
| 1285 | sum = State.regs[REG_MCRL] + temp; |
| 1286 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 1287 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1288 | State.regs[REG_MCRL] = sum; |
| 1289 | if (v) |
| 1290 | State.regs[REG_MCVF] = 1; |
| 1291 | } |
| 1292 | |
| 1293 | // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn |
| 1294 | 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu |
| 1295 | "macbu" |
| 1296 | *am33 |
| 1297 | *am33_2 |
| 1298 | { |
| 1299 | int srcreg1, srcreg2; |
| 1300 | signed64 temp, sum; |
| 1301 | int v; |
| 1302 | |
| 1303 | PC = cia; |
| 1304 | srcreg1 = translate_rreg (SD_, RM2); |
| 1305 | srcreg2 = translate_rreg (SD_, RN0); |
| 1306 | |
| 1307 | temp = ((unsigned32)(State.regs[srcreg2] & 0xff) |
| 1308 | * (unsigned32)(State.regs[srcreg1] & 0xff)); |
| 1309 | sum = State.regs[REG_MCRL] + temp; |
| 1310 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 1311 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1312 | State.regs[REG_MCRL] = sum; |
| 1313 | if (v) |
| 1314 | State.regs[REG_MCVF] = 1; |
| 1315 | } |
| 1316 | |
| 1317 | // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn |
| 1318 | 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach |
| 1319 | "mach" |
| 1320 | *am33 |
| 1321 | *am33_2 |
| 1322 | { |
| 1323 | int srcreg1, srcreg2; |
| 1324 | signed64 temp, sum; |
| 1325 | int c, v; |
| 1326 | |
| 1327 | PC = cia; |
| 1328 | srcreg1 = translate_rreg (SD_, RM2); |
| 1329 | srcreg2 = translate_rreg (SD_, RN0); |
| 1330 | |
| 1331 | temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff) |
| 1332 | * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 1333 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 1334 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 1335 | State.regs[REG_MCRL] = sum; |
| 1336 | temp >>= 32; |
| 1337 | temp &= 0xffffffff; |
| 1338 | sum = State.regs[REG_MCRH] + temp + c; |
| 1339 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 1340 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1341 | State.regs[REG_MCRH] = sum; |
| 1342 | if (v) |
| 1343 | State.regs[REG_MCVF] = 1; |
| 1344 | } |
| 1345 | |
| 1346 | // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn |
| 1347 | 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu |
| 1348 | "machu" |
| 1349 | *am33 |
| 1350 | *am33_2 |
| 1351 | { |
| 1352 | int srcreg1, srcreg2; |
| 1353 | signed64 temp, sum; |
| 1354 | int c, v; |
| 1355 | |
| 1356 | PC = cia; |
| 1357 | srcreg1 = translate_rreg (SD_, RM2); |
| 1358 | srcreg2 = translate_rreg (SD_, RN0); |
| 1359 | |
| 1360 | temp = ((unsigned64)(State.regs[srcreg2] & 0xffff) |
| 1361 | * (unsigned64)(State.regs[srcreg1] & 0xffff)); |
| 1362 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 1363 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 1364 | State.regs[REG_MCRL] = sum; |
| 1365 | temp >>= 32; |
| 1366 | temp &= 0xffffffff; |
| 1367 | sum = State.regs[REG_MCRH] + temp + c; |
| 1368 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 1369 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1370 | State.regs[REG_MCRH] = sum; |
| 1371 | if (v) |
| 1372 | State.regs[REG_MCVF] = 1; |
| 1373 | } |
| 1374 | |
| 1375 | // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn |
| 1376 | 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach |
| 1377 | "dmach" |
| 1378 | *am33 |
| 1379 | *am33_2 |
| 1380 | { |
| 1381 | int srcreg1, srcreg2; |
| 1382 | signed32 temp, temp2, sum; |
| 1383 | int v; |
| 1384 | |
| 1385 | PC = cia; |
| 1386 | srcreg1 = translate_rreg (SD_, RM2); |
| 1387 | srcreg2 = translate_rreg (SD_, RN0); |
| 1388 | |
| 1389 | temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff) |
| 1390 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 1391 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 1392 | * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff)); |
| 1393 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 1394 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 1395 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1396 | State.regs[REG_MCRL] = sum; |
| 1397 | if (v) |
| 1398 | State.regs[REG_MCVF] = 1; |
| 1399 | } |
| 1400 | |
| 1401 | // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn |
| 1402 | 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu |
| 1403 | "dmachu" |
| 1404 | *am33 |
| 1405 | *am33_2 |
| 1406 | { |
| 1407 | int srcreg1, srcreg2; |
| 1408 | unsigned32 temp, temp2, sum; |
| 1409 | int v; |
| 1410 | |
| 1411 | PC = cia; |
| 1412 | srcreg1 = translate_rreg (SD_, RM2); |
| 1413 | srcreg2 = translate_rreg (SD_, RN0); |
| 1414 | |
| 1415 | temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) |
| 1416 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); |
| 1417 | temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) |
| 1418 | * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); |
| 1419 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 1420 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 1421 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 1422 | State.regs[REG_MCRL] = sum; |
| 1423 | if (v) |
| 1424 | State.regs[REG_MCVF] = 1; |
| 1425 | } |
| 1426 | |
| 1427 | // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn |
| 1428 | 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh |
| 1429 | "dmulh" |
| 1430 | *am33 |
| 1431 | *am33_2 |
| 1432 | { |
| 1433 | int srcreg, dstreg; |
| 1434 | signed32 temp; |
| 1435 | |
| 1436 | PC = cia; |
| 1437 | srcreg = translate_rreg (SD_, RM2); |
| 1438 | dstreg = translate_rreg (SD_, RN0); |
| 1439 | |
| 1440 | temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) |
| 1441 | * (signed32)(signed16)(State.regs[srcreg] & 0xffff)); |
| 1442 | State.regs[REG_MDRQ] = temp; |
| 1443 | temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) |
| 1444 | * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff)); |
| 1445 | State.regs[dstreg] = temp; |
| 1446 | } |
| 1447 | |
| 1448 | // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn |
| 1449 | 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu |
| 1450 | "dmachu" |
| 1451 | *am33 |
| 1452 | *am33_2 |
| 1453 | { |
| 1454 | int srcreg, dstreg; |
| 1455 | unsigned32 temp; |
| 1456 | |
| 1457 | PC = cia; |
| 1458 | srcreg = translate_rreg (SD_, RM2); |
| 1459 | dstreg = translate_rreg (SD_, RN0); |
| 1460 | |
| 1461 | temp = ((unsigned32)(State.regs[dstreg] & 0xffff) |
| 1462 | * (unsigned32)(State.regs[srcreg] & 0xffff)); |
| 1463 | State.regs[REG_MDRQ] = temp; |
| 1464 | temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) |
| 1465 | * (unsigned32)((State.regs[srcreg] >>16) & 0xffff)); |
| 1466 | State.regs[dstreg] = temp; |
| 1467 | } |
| 1468 | |
| 1469 | // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn |
| 1470 | 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16 |
| 1471 | "sat16" |
| 1472 | *am33 |
| 1473 | *am33_2 |
| 1474 | { |
| 1475 | int srcreg, dstreg; |
| 1476 | int value, z, n; |
| 1477 | |
| 1478 | PC = cia; |
| 1479 | srcreg = translate_rreg (SD_, RM2); |
| 1480 | dstreg = translate_rreg (SD_, RN0); |
| 1481 | |
| 1482 | value = State.regs[srcreg]; |
| 1483 | |
| 1484 | if (value >= 0x7fff) |
| 1485 | State.regs[dstreg] = 0x7fff; |
| 1486 | else if (value <= 0xffff8000) |
| 1487 | State.regs[dstreg] = 0xffff8000; |
| 1488 | else |
| 1489 | State.regs[dstreg] = value; |
| 1490 | |
| 1491 | n = (State.regs[dstreg] & 0x8000) != 0; |
| 1492 | z = (State.regs[dstreg] == 0); |
| 1493 | PSW &= ~(PSW_Z | PSW_N); |
| 1494 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 1495 | } |
| 1496 | |
| 1497 | // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn |
| 1498 | 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste |
| 1499 | "mcste" |
| 1500 | *am33 |
| 1501 | *am33_2 |
| 1502 | { |
| 1503 | int srcreg, dstreg; |
| 1504 | |
| 1505 | PC = cia; |
| 1506 | srcreg = translate_rreg (SD_, RM2); |
| 1507 | dstreg = translate_rreg (SD_, RN0); |
| 1508 | |
| 1509 | PSW &= ~(PSW_V | PSW_C); |
| 1510 | PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); |
| 1511 | |
| 1512 | /* 32bit saturation. */ |
| 1513 | if (State.regs[srcreg] == 0x20) |
| 1514 | { |
| 1515 | signed64 tmp; |
| 1516 | |
| 1517 | tmp = State.regs[REG_MCRH]; |
| 1518 | tmp <<= 32; |
| 1519 | tmp += State.regs[REG_MCRL]; |
| 1520 | |
| 1521 | if (tmp > 0x7fffffff) |
| 1522 | State.regs[dstreg] = 0x7fffffff; |
| 1523 | else if (tmp < 0xffffffff80000000LL) |
| 1524 | State.regs[dstreg] = 0x80000000; |
| 1525 | else |
| 1526 | State.regs[dstreg] = tmp; |
| 1527 | } |
| 1528 | /* 16bit saturation */ |
| 1529 | else if (State.regs[srcreg] == 0x10) |
| 1530 | { |
| 1531 | signed64 tmp; |
| 1532 | |
| 1533 | tmp = State.regs[REG_MCRH]; |
| 1534 | tmp <<= 32; |
| 1535 | tmp += State.regs[REG_MCRL]; |
| 1536 | |
| 1537 | if (tmp > 0x7fff) |
| 1538 | State.regs[dstreg] = 0x7fff; |
| 1539 | else if (tmp < 0xffffffffffff8000LL) |
| 1540 | State.regs[dstreg] = 0x8000; |
| 1541 | else |
| 1542 | State.regs[dstreg] = tmp; |
| 1543 | } |
| 1544 | /* 8 bit saturation */ |
| 1545 | else if (State.regs[srcreg] == 0x8) |
| 1546 | { |
| 1547 | signed64 tmp; |
| 1548 | |
| 1549 | tmp = State.regs[REG_MCRH]; |
| 1550 | tmp <<= 32; |
| 1551 | tmp += State.regs[REG_MCRL]; |
| 1552 | |
| 1553 | if (tmp > 0x7f) |
| 1554 | State.regs[dstreg] = 0x7f; |
| 1555 | else if (tmp < 0xffffffffffffff80LL) |
| 1556 | State.regs[dstreg] = 0x80; |
| 1557 | else |
| 1558 | State.regs[dstreg] = tmp; |
| 1559 | } |
| 1560 | /* 9 bit saturation */ |
| 1561 | else if (State.regs[srcreg] == 0x9) |
| 1562 | { |
| 1563 | signed64 tmp; |
| 1564 | |
| 1565 | tmp = State.regs[REG_MCRH]; |
| 1566 | tmp <<= 32; |
| 1567 | tmp += State.regs[REG_MCRL]; |
| 1568 | |
| 1569 | if (tmp > 0x80) |
| 1570 | State.regs[dstreg] = 0x80; |
| 1571 | else if (tmp < 0xffffffffffffff81LL) |
| 1572 | State.regs[dstreg] = 0x81; |
| 1573 | else |
| 1574 | State.regs[dstreg] = tmp; |
| 1575 | } |
| 1576 | /* 9 bit saturation */ |
| 1577 | else if (State.regs[srcreg] == 0x30) |
| 1578 | { |
| 1579 | signed64 tmp; |
| 1580 | |
| 1581 | tmp = State.regs[REG_MCRH]; |
| 1582 | tmp <<= 32; |
| 1583 | tmp += State.regs[REG_MCRL]; |
| 1584 | |
| 1585 | if (tmp > 0x7fffffffffffLL) |
| 1586 | tmp = 0x7fffffffffffLL; |
| 1587 | else if (tmp < 0xffff800000000000LL) |
| 1588 | tmp = 0xffff800000000000LL; |
| 1589 | |
| 1590 | tmp >>= 16; |
| 1591 | State.regs[dstreg] = tmp; |
| 1592 | } |
| 1593 | } |
| 1594 | |
| 1595 | // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn |
| 1596 | 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap |
| 1597 | "swap" |
| 1598 | *am33 |
| 1599 | *am33_2 |
| 1600 | { |
| 1601 | int srcreg, dstreg; |
| 1602 | |
| 1603 | PC = cia; |
| 1604 | srcreg = translate_rreg (SD_, RM2); |
| 1605 | dstreg = translate_rreg (SD_, RN0); |
| 1606 | |
| 1607 | State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24) |
| 1608 | | (((State.regs[srcreg] >> 8) & 0xff) << 16) |
| 1609 | | (((State.regs[srcreg] >> 16) & 0xff) << 8) |
| 1610 | | ((State.regs[srcreg] >> 24) & 0xff)); |
| 1611 | } |
| 1612 | |
| 1613 | // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn |
| 1614 | 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph |
| 1615 | "swaph" |
| 1616 | *am33 |
| 1617 | *am33_2 |
| 1618 | { |
| 1619 | int srcreg, dstreg; |
| 1620 | |
| 1621 | PC = cia; |
| 1622 | srcreg = translate_rreg (SD_, RM2); |
| 1623 | dstreg = translate_rreg (SD_, RN0); |
| 1624 | |
| 1625 | State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8) |
| 1626 | | ((State.regs[srcreg] >> 8) & 0xff) |
| 1627 | | (((State.regs[srcreg] >> 16) & 0xff) << 24) |
| 1628 | | (((State.regs[srcreg] >> 24) & 0xff) << 16)); |
| 1629 | } |
| 1630 | |
| 1631 | // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn |
| 1632 | 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw |
| 1633 | "swhw" |
| 1634 | *am33 |
| 1635 | *am33_2 |
| 1636 | { |
| 1637 | int srcreg, dstreg; |
| 1638 | |
| 1639 | PC = cia; |
| 1640 | srcreg = translate_rreg (SD_, RM2); |
| 1641 | dstreg = translate_rreg (SD_, RN0); |
| 1642 | |
| 1643 | State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16) |
| 1644 | | ((State.regs[srcreg] >> 16) & 0xffff)); |
| 1645 | } |
| 1646 | |
| 1647 | // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn |
| 1648 | 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch |
| 1649 | "bsch" |
| 1650 | *am33 |
| 1651 | *am33_2 |
| 1652 | { |
| 1653 | int temp, c, i; |
| 1654 | int srcreg, dstreg; |
| 1655 | int start; |
| 1656 | |
| 1657 | PC = cia; |
| 1658 | srcreg = translate_rreg (SD_, RM2); |
| 1659 | dstreg = translate_rreg (SD_, RN0); |
| 1660 | |
| 1661 | temp = State.regs[srcreg]; |
| 1662 | start = (State.regs[dstreg] & 0x1f) - 1; |
| 1663 | if (start == -1) |
| 1664 | start = 31; |
| 1665 | |
| 1666 | c = 0; |
| 1667 | for (i = start; i >= 0; i--) |
| 1668 | { |
| 1669 | if (temp & (1 << i)) |
| 1670 | { |
| 1671 | c = 1; |
| 1672 | State.regs[dstreg] = i; |
| 1673 | break; |
| 1674 | } |
| 1675 | } |
| 1676 | |
| 1677 | if (i < 0) |
| 1678 | { |
| 1679 | c = 0; |
| 1680 | State.regs[dstreg] = 0; |
| 1681 | } |
| 1682 | PSW &= ~(PSW_C); |
| 1683 | PSW |= (c ? PSW_C : 0); |
| 1684 | } |
| 1685 | |
| 1686 | |
| 1687 | // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn |
| 1688 | 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov |
| 1689 | "mov" |
| 1690 | *am33 |
| 1691 | *am33_2 |
| 1692 | { |
| 1693 | int dstreg; |
| 1694 | |
| 1695 | PC = cia; |
| 1696 | dstreg = translate_rreg (SD_, RN0); |
| 1697 | State.regs[dstreg] = EXTEND8 (IMM8); |
| 1698 | } |
| 1699 | |
| 1700 | // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn |
| 1701 | 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu |
| 1702 | "movu" |
| 1703 | *am33 |
| 1704 | *am33_2 |
| 1705 | { |
| 1706 | int dstreg; |
| 1707 | |
| 1708 | PC = cia; |
| 1709 | dstreg = translate_rreg (SD_, RN0); |
| 1710 | State.regs[dstreg] = IMM8 & 0xff; |
| 1711 | } |
| 1712 | |
| 1713 | // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn |
| 1714 | 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add |
| 1715 | "add" |
| 1716 | *am33 |
| 1717 | *am33_2 |
| 1718 | { |
| 1719 | int dstreg; |
| 1720 | |
| 1721 | PC = cia; |
| 1722 | dstreg = translate_rreg (SD_, RN0); |
| 1723 | genericAdd (EXTEND8 (IMM8), dstreg); |
| 1724 | } |
| 1725 | |
| 1726 | // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn |
| 1727 | 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc |
| 1728 | "addc" |
| 1729 | *am33 |
| 1730 | *am33_2 |
| 1731 | { |
| 1732 | int dstreg, imm; |
| 1733 | int z, c, n, v; |
| 1734 | unsigned32 reg2, sum; |
| 1735 | |
| 1736 | PC = cia; |
| 1737 | dstreg = translate_rreg (SD_, RN0); |
| 1738 | |
| 1739 | imm = EXTEND8 (IMM8); |
| 1740 | reg2 = State.regs[dstreg]; |
| 1741 | sum = imm + reg2 + ((PSW & PSW_C) != 0); |
| 1742 | State.regs[dstreg] = sum; |
| 1743 | |
| 1744 | z = ((PSW & PSW_Z) != 0) && (sum == 0); |
| 1745 | n = (sum & 0x80000000); |
| 1746 | c = (sum < imm) || (sum < reg2); |
| 1747 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) |
| 1748 | && (reg2 & 0x80000000) != (sum & 0x80000000)); |
| 1749 | |
| 1750 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 1751 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 1752 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 1753 | } |
| 1754 | |
| 1755 | // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn |
| 1756 | 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub |
| 1757 | "sub" |
| 1758 | *am33 |
| 1759 | *am33_2 |
| 1760 | { |
| 1761 | int dstreg; |
| 1762 | |
| 1763 | PC = cia; |
| 1764 | dstreg = translate_rreg (SD_, RN0); |
| 1765 | |
| 1766 | genericSub (EXTEND8 (IMM8), dstreg); |
| 1767 | } |
| 1768 | |
| 1769 | // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn |
| 1770 | 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc |
| 1771 | "subc" |
| 1772 | *am33 |
| 1773 | *am33_2 |
| 1774 | { |
| 1775 | int imm, dstreg; |
| 1776 | int z, c, n, v; |
| 1777 | unsigned32 reg2, difference; |
| 1778 | |
| 1779 | PC = cia; |
| 1780 | dstreg = translate_rreg (SD_, RN0); |
| 1781 | |
| 1782 | imm = EXTEND8 (IMM8); |
| 1783 | reg2 = State.regs[dstreg]; |
| 1784 | difference = reg2 - imm - ((PSW & PSW_C) != 0); |
| 1785 | State.regs[dstreg] = difference; |
| 1786 | |
| 1787 | z = ((PSW & PSW_Z) != 0) && (difference == 0); |
| 1788 | n = (difference & 0x80000000); |
| 1789 | c = (imm > reg2); |
| 1790 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) |
| 1791 | && (reg2 & 0x80000000) != (difference & 0x80000000)); |
| 1792 | |
| 1793 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 1794 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 1795 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 1796 | } |
| 1797 | |
| 1798 | // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn |
| 1799 | 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp |
| 1800 | "cmp" |
| 1801 | *am33 |
| 1802 | *am33_2 |
| 1803 | { |
| 1804 | int srcreg; |
| 1805 | |
| 1806 | PC = cia; |
| 1807 | srcreg = translate_rreg (SD_, RN0); |
| 1808 | genericCmp (EXTEND8 (IMM8), State.regs[srcreg]); |
| 1809 | } |
| 1810 | |
| 1811 | // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn |
| 1812 | 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov |
| 1813 | "mov" |
| 1814 | *am33 |
| 1815 | *am33_2 |
| 1816 | { |
| 1817 | int dstreg; |
| 1818 | |
| 1819 | PC = cia; |
| 1820 | dstreg = translate_xreg (SD_, XRN0); |
| 1821 | |
| 1822 | State.regs[dstreg] = IMM8; |
| 1823 | } |
| 1824 | |
| 1825 | // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn |
| 1826 | 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and |
| 1827 | "and" |
| 1828 | *am33 |
| 1829 | *am33_2 |
| 1830 | { |
| 1831 | int dstreg; |
| 1832 | int z, n; |
| 1833 | |
| 1834 | PC = cia; |
| 1835 | dstreg = translate_rreg (SD_, RN0); |
| 1836 | |
| 1837 | State.regs[dstreg] &= (IMM8 & 0xff); |
| 1838 | z = (State.regs[dstreg] == 0); |
| 1839 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1840 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 1841 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 1842 | } |
| 1843 | |
| 1844 | // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn |
| 1845 | 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or |
| 1846 | "or" |
| 1847 | *am33 |
| 1848 | *am33_2 |
| 1849 | { |
| 1850 | int dstreg; |
| 1851 | int z, n; |
| 1852 | |
| 1853 | PC = cia; |
| 1854 | dstreg = translate_rreg (SD_, RN0); |
| 1855 | |
| 1856 | State.regs[dstreg] |= (IMM8 & 0xff); |
| 1857 | z = (State.regs[dstreg] == 0); |
| 1858 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1859 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 1860 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 1861 | } |
| 1862 | |
| 1863 | // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn |
| 1864 | 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor |
| 1865 | "xor" |
| 1866 | *am33 |
| 1867 | *am33_2 |
| 1868 | { |
| 1869 | int dstreg; |
| 1870 | int z, n; |
| 1871 | |
| 1872 | PC = cia; |
| 1873 | dstreg = translate_rreg (SD_, RN0); |
| 1874 | |
| 1875 | State.regs[dstreg] ^= (IMM8 & 0xff); |
| 1876 | z = (State.regs[dstreg] == 0); |
| 1877 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1878 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 1879 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 1880 | } |
| 1881 | |
| 1882 | // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn |
| 1883 | 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr |
| 1884 | "asr" |
| 1885 | *am33 |
| 1886 | *am33_2 |
| 1887 | { |
| 1888 | int dstreg; |
| 1889 | signed32 temp; |
| 1890 | int c, z, n; |
| 1891 | |
| 1892 | PC = cia; |
| 1893 | dstreg = translate_rreg (SD_, RN0); |
| 1894 | |
| 1895 | temp = State.regs[dstreg]; |
| 1896 | c = temp & 1; |
| 1897 | temp >>= (IMM8 & 0xff); |
| 1898 | State.regs[dstreg] = temp; |
| 1899 | z = (State.regs[dstreg] == 0); |
| 1900 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1901 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 1902 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 1903 | } |
| 1904 | |
| 1905 | // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn |
| 1906 | 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr |
| 1907 | "lsr" |
| 1908 | *am33 |
| 1909 | *am33_2 |
| 1910 | { |
| 1911 | int dstreg; |
| 1912 | int z, n, c; |
| 1913 | |
| 1914 | PC = cia; |
| 1915 | dstreg = translate_rreg (SD_, RN0); |
| 1916 | |
| 1917 | c = State.regs[dstreg] & 1; |
| 1918 | State.regs[dstreg] >>= (IMM8 & 0xff); |
| 1919 | z = (State.regs[dstreg] == 0); |
| 1920 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1921 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 1922 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 1923 | } |
| 1924 | |
| 1925 | // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn |
| 1926 | 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl |
| 1927 | "asl" |
| 1928 | *am33 |
| 1929 | *am33_2 |
| 1930 | { |
| 1931 | int dstreg; |
| 1932 | int z, n; |
| 1933 | |
| 1934 | PC = cia; |
| 1935 | dstreg = translate_rreg (SD_, RN0); |
| 1936 | |
| 1937 | State.regs[dstreg] <<= (IMM8 & 0xff); |
| 1938 | z = (State.regs[dstreg] == 0); |
| 1939 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1940 | PSW &= ~(PSW_Z | PSW_N); |
| 1941 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 1942 | } |
| 1943 | |
| 1944 | // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn |
| 1945 | 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul |
| 1946 | "mul" |
| 1947 | *am33 |
| 1948 | *am33_2 |
| 1949 | { |
| 1950 | int dstreg; |
| 1951 | unsigned64 temp; |
| 1952 | int z, n; |
| 1953 | |
| 1954 | PC = cia; |
| 1955 | dstreg = translate_rreg (SD_, RN0); |
| 1956 | |
| 1957 | temp = ((signed64)(signed32)State.regs[dstreg] |
| 1958 | * (signed64)(signed32)EXTEND8 (IMM8)); |
| 1959 | State.regs[dstreg] = temp & 0xffffffff; |
| 1960 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 1961 | z = (State.regs[dstreg] == 0); |
| 1962 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1963 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 1964 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 1965 | } |
| 1966 | |
| 1967 | // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn |
| 1968 | 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu |
| 1969 | "mulu" |
| 1970 | *am33 |
| 1971 | *am33_2 |
| 1972 | { |
| 1973 | int dstreg; |
| 1974 | unsigned64 temp; |
| 1975 | int z, n; |
| 1976 | |
| 1977 | PC = cia; |
| 1978 | dstreg = translate_rreg (SD_, RN0); |
| 1979 | |
| 1980 | temp = ((unsigned64)State.regs[dstreg] |
| 1981 | * (unsigned64)(IMM8 & 0xff)); |
| 1982 | State.regs[dstreg] = temp & 0xffffffff; |
| 1983 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 1984 | z = (State.regs[dstreg] == 0); |
| 1985 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 1986 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 1987 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 1988 | } |
| 1989 | |
| 1990 | // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn |
| 1991 | 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst |
| 1992 | "btst" |
| 1993 | *am33 |
| 1994 | *am33_2 |
| 1995 | { |
| 1996 | int srcreg; |
| 1997 | |
| 1998 | PC = cia; |
| 1999 | srcreg = translate_rreg (SD_, RM0); |
| 2000 | genericBtst(IMM8, State.regs[srcreg]); |
| 2001 | } |
| 2002 | |
| 2003 | // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn |
| 2004 | 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov |
| 2005 | "mov" |
| 2006 | *am33 |
| 2007 | *am33_2 |
| 2008 | { |
| 2009 | int srcreg, dstreg; |
| 2010 | |
| 2011 | PC = cia; |
| 2012 | srcreg = translate_rreg (SD_, RM0); |
| 2013 | dstreg = translate_rreg (SD_, RN2); |
| 2014 | State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8)); |
| 2015 | } |
| 2016 | |
| 2017 | // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn) |
| 2018 | 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov |
| 2019 | "mov" |
| 2020 | *am33 |
| 2021 | *am33_2 |
| 2022 | { |
| 2023 | int srcreg, dstreg; |
| 2024 | |
| 2025 | PC = cia; |
| 2026 | srcreg = translate_rreg (SD_, RM2); |
| 2027 | dstreg = translate_rreg (SD_, RN0); |
| 2028 | store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); |
| 2029 | } |
| 2030 | |
| 2031 | // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn |
| 2032 | 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu |
| 2033 | "movbu" |
| 2034 | *am33 |
| 2035 | *am33_2 |
| 2036 | { |
| 2037 | int srcreg, dstreg; |
| 2038 | |
| 2039 | PC = cia; |
| 2040 | srcreg = translate_rreg (SD_, RM0); |
| 2041 | dstreg = translate_rreg (SD_, RN2); |
| 2042 | State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8)); |
| 2043 | } |
| 2044 | |
| 2045 | // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn) |
| 2046 | 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu |
| 2047 | "movbu" |
| 2048 | *am33 |
| 2049 | *am33_2 |
| 2050 | { |
| 2051 | int srcreg, dstreg; |
| 2052 | |
| 2053 | PC = cia; |
| 2054 | srcreg = translate_rreg (SD_, RM2); |
| 2055 | dstreg = translate_rreg (SD_, RN0); |
| 2056 | store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); |
| 2057 | } |
| 2058 | |
| 2059 | // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn |
| 2060 | 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu |
| 2061 | "movhu" |
| 2062 | *am33 |
| 2063 | *am33_2 |
| 2064 | { |
| 2065 | int srcreg, dstreg; |
| 2066 | |
| 2067 | PC = cia; |
| 2068 | srcreg = translate_rreg (SD_, RM0); |
| 2069 | dstreg = translate_rreg (SD_, RN2); |
| 2070 | State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8)); |
| 2071 | } |
| 2072 | |
| 2073 | // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn) |
| 2074 | 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu |
| 2075 | "movhu" |
| 2076 | *am33 |
| 2077 | *am33_2 |
| 2078 | { |
| 2079 | int srcreg, dstreg; |
| 2080 | |
| 2081 | PC = cia; |
| 2082 | srcreg = translate_rreg (SD_, RM2); |
| 2083 | dstreg = translate_rreg (SD_, RN0); |
| 2084 | store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); |
| 2085 | } |
| 2086 | |
| 2087 | // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn |
| 2088 | 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov |
| 2089 | "mov" |
| 2090 | *am33 |
| 2091 | *am33_2 |
| 2092 | { |
| 2093 | int srcreg, dstreg; |
| 2094 | |
| 2095 | PC = cia; |
| 2096 | srcreg = translate_rreg (SD_, RM0); |
| 2097 | dstreg = translate_rreg (SD_, RN2); |
| 2098 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 2099 | State.regs[srcreg] += EXTEND8 (IMM8); |
| 2100 | } |
| 2101 | |
| 2102 | // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+) |
| 2103 | 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov |
| 2104 | "mov" |
| 2105 | *am33 |
| 2106 | *am33_2 |
| 2107 | { |
| 2108 | int srcreg, dstreg; |
| 2109 | |
| 2110 | PC = cia; |
| 2111 | srcreg = translate_rreg (SD_, RM2); |
| 2112 | dstreg = translate_rreg (SD_, RN0); |
| 2113 | store_word (State.regs[dstreg], State.regs[srcreg]); |
| 2114 | State.regs[dstreg] += EXTEND8 (IMM8); |
| 2115 | } |
| 2116 | |
| 2117 | |
| 2118 | // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn |
| 2119 | 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov |
| 2120 | "mov" |
| 2121 | *am33 |
| 2122 | *am33_2 |
| 2123 | { |
| 2124 | int dstreg; |
| 2125 | |
| 2126 | PC = cia; |
| 2127 | dstreg = translate_rreg (SD_, RN2); |
| 2128 | State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8); |
| 2129 | } |
| 2130 | |
| 2131 | // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp) |
| 2132 | 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov |
| 2133 | "mov" |
| 2134 | *am33 |
| 2135 | *am33_2 |
| 2136 | { |
| 2137 | int srcreg; |
| 2138 | |
| 2139 | PC = cia; |
| 2140 | srcreg = translate_rreg (SD_, RM2); |
| 2141 | store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]); |
| 2142 | } |
| 2143 | |
| 2144 | // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn |
| 2145 | 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu |
| 2146 | "movbu" |
| 2147 | *am33 |
| 2148 | *am33_2 |
| 2149 | { |
| 2150 | int dstreg; |
| 2151 | |
| 2152 | PC = cia; |
| 2153 | dstreg = translate_rreg (SD_, RN2); |
| 2154 | State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8); |
| 2155 | } |
| 2156 | |
| 2157 | // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp) |
| 2158 | 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu |
| 2159 | "movbu" |
| 2160 | *am33 |
| 2161 | *am33_2 |
| 2162 | { |
| 2163 | int srcreg; |
| 2164 | |
| 2165 | PC = cia; |
| 2166 | srcreg = translate_rreg (SD_, RM2); |
| 2167 | store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]); |
| 2168 | } |
| 2169 | |
| 2170 | // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn |
| 2171 | 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu |
| 2172 | "movhu" |
| 2173 | *am33 |
| 2174 | *am33_2 |
| 2175 | { |
| 2176 | int dstreg; |
| 2177 | |
| 2178 | PC = cia; |
| 2179 | dstreg = translate_rreg (SD_, RN2); |
| 2180 | State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8); |
| 2181 | } |
| 2182 | |
| 2183 | // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp) |
| 2184 | 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu |
| 2185 | "movhu" |
| 2186 | *am33 |
| 2187 | *am33_2 |
| 2188 | { |
| 2189 | int srcreg; |
| 2190 | |
| 2191 | PC = cia; |
| 2192 | srcreg = translate_rreg (SD_, RM2); |
| 2193 | store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]); |
| 2194 | } |
| 2195 | |
| 2196 | // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn |
| 2197 | 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu |
| 2198 | "movhu" |
| 2199 | *am33 |
| 2200 | *am33_2 |
| 2201 | { |
| 2202 | int srcreg, dstreg; |
| 2203 | |
| 2204 | PC = cia; |
| 2205 | srcreg = translate_rreg (SD_, RM0); |
| 2206 | dstreg = translate_rreg (SD_, RN2); |
| 2207 | State.regs[dstreg] = load_half (State.regs[srcreg]); |
| 2208 | State.regs[srcreg] += EXTEND8 (IMM8); |
| 2209 | } |
| 2210 | |
| 2211 | // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+) |
| 2212 | 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu |
| 2213 | "movhu" |
| 2214 | *am33 |
| 2215 | *am33_2 |
| 2216 | { |
| 2217 | int srcreg, dstreg; |
| 2218 | |
| 2219 | PC = cia; |
| 2220 | srcreg = translate_rreg (SD_, RM2); |
| 2221 | dstreg = translate_rreg (SD_, RN0); |
| 2222 | store_half (State.regs[dstreg], State.regs[srcreg]); |
| 2223 | State.regs[dstreg] += EXTEND8 (IMM8); |
| 2224 | } |
| 2225 | |
| 2226 | |
| 2227 | // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn |
| 2228 | 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac |
| 2229 | "mac" |
| 2230 | *am33 |
| 2231 | *am33_2 |
| 2232 | { |
| 2233 | int srcreg; |
| 2234 | signed64 temp, sum; |
| 2235 | int c, v; |
| 2236 | |
| 2237 | PC = cia; |
| 2238 | srcreg = translate_rreg (SD_, RN2); |
| 2239 | |
| 2240 | temp = ((signed64)(signed32)EXTEND8 (IMM8) |
| 2241 | * (signed64)(signed32)State.regs[srcreg]); |
| 2242 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 2243 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 2244 | State.regs[REG_MCRL] = sum; |
| 2245 | temp >>= 32; |
| 2246 | temp &= 0xffffffff; |
| 2247 | sum = State.regs[REG_MCRH] + temp + c; |
| 2248 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 2249 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 2250 | State.regs[REG_MCRH] = sum; |
| 2251 | if (v) |
| 2252 | State.regs[REG_MCVF] = 1; |
| 2253 | } |
| 2254 | |
| 2255 | // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn |
| 2256 | 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu |
| 2257 | "macu" |
| 2258 | *am33 |
| 2259 | *am33_2 |
| 2260 | { |
| 2261 | int srcreg; |
| 2262 | signed64 temp, sum; |
| 2263 | int c, v; |
| 2264 | |
| 2265 | PC = cia; |
| 2266 | srcreg = translate_rreg (SD_, RN2); |
| 2267 | |
| 2268 | temp = ((unsigned64) (IMM8) |
| 2269 | * (unsigned64)State.regs[srcreg]); |
| 2270 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 2271 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 2272 | State.regs[REG_MCRL] = sum; |
| 2273 | temp >>= 32; |
| 2274 | temp &= 0xffffffff; |
| 2275 | sum = State.regs[REG_MCRH] + temp + c; |
| 2276 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 2277 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 2278 | State.regs[REG_MCRH] = sum; |
| 2279 | if (v) |
| 2280 | State.regs[REG_MCVF] = 1; |
| 2281 | } |
| 2282 | |
| 2283 | // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn |
| 2284 | 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb |
| 2285 | "macb" |
| 2286 | *am33 |
| 2287 | *am33_2 |
| 2288 | { |
| 2289 | int srcreg; |
| 2290 | signed64 temp, sum; |
| 2291 | int c, v; |
| 2292 | |
| 2293 | PC = cia; |
| 2294 | srcreg = translate_rreg (SD_, RN2); |
| 2295 | |
| 2296 | temp = ((signed64)(signed8)EXTEND8 (IMM8) |
| 2297 | * (signed64)(signed8)State.regs[srcreg] & 0xff); |
| 2298 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 2299 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 2300 | State.regs[REG_MCRL] = sum; |
| 2301 | temp >>= 32; |
| 2302 | temp &= 0xffffffff; |
| 2303 | sum = State.regs[REG_MCRH] + temp + c; |
| 2304 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 2305 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 2306 | State.regs[REG_MCRH] = sum; |
| 2307 | if (v) |
| 2308 | State.regs[REG_MCVF] = 1; |
| 2309 | } |
| 2310 | |
| 2311 | // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn |
| 2312 | 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu |
| 2313 | "macbu" |
| 2314 | *am33 |
| 2315 | *am33_2 |
| 2316 | { |
| 2317 | int srcreg; |
| 2318 | signed64 temp, sum; |
| 2319 | int c, v; |
| 2320 | |
| 2321 | PC = cia; |
| 2322 | srcreg = translate_rreg (SD_, RN2); |
| 2323 | |
| 2324 | temp = ((unsigned64) (IMM8) |
| 2325 | * (unsigned64)State.regs[srcreg] & 0xff); |
| 2326 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 2327 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 2328 | State.regs[REG_MCRL] = sum; |
| 2329 | temp >>= 32; |
| 2330 | temp &= 0xffffffff; |
| 2331 | sum = State.regs[REG_MCRH] + temp + c; |
| 2332 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 2333 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 2334 | State.regs[REG_MCRH] = sum; |
| 2335 | if (v) |
| 2336 | State.regs[REG_MCVF] = 1; |
| 2337 | } |
| 2338 | |
| 2339 | // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn |
| 2340 | 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach |
| 2341 | "mach" |
| 2342 | *am33 |
| 2343 | *am33_2 |
| 2344 | { |
| 2345 | int srcreg; |
| 2346 | signed64 temp, sum; |
| 2347 | int c, v; |
| 2348 | |
| 2349 | PC = cia; |
| 2350 | srcreg = translate_rreg (SD_, RN2); |
| 2351 | |
| 2352 | temp = ((signed64)(signed16)EXTEND8 (IMM8) |
| 2353 | * (signed64)(signed16)State.regs[srcreg] & 0xffff); |
| 2354 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 2355 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 2356 | State.regs[REG_MCRL] = sum; |
| 2357 | temp >>= 32; |
| 2358 | temp &= 0xffffffff; |
| 2359 | sum = State.regs[REG_MCRH] + temp + c; |
| 2360 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 2361 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 2362 | State.regs[REG_MCRH] = sum; |
| 2363 | if (v) |
| 2364 | State.regs[REG_MCVF] = 1; |
| 2365 | } |
| 2366 | |
| 2367 | // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn |
| 2368 | 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu |
| 2369 | "machu" |
| 2370 | *am33 |
| 2371 | *am33_2 |
| 2372 | { |
| 2373 | int srcreg; |
| 2374 | signed64 temp, sum; |
| 2375 | int c, v; |
| 2376 | |
| 2377 | PC = cia; |
| 2378 | srcreg = translate_rreg (SD_, RN2); |
| 2379 | |
| 2380 | temp = ((unsigned64) (IMM8) |
| 2381 | * (unsigned64)State.regs[srcreg] & 0xffff); |
| 2382 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 2383 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 2384 | State.regs[REG_MCRL] = sum; |
| 2385 | temp >>= 32; |
| 2386 | temp &= 0xffffffff; |
| 2387 | sum = State.regs[REG_MCRH] + temp + c; |
| 2388 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 2389 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 2390 | State.regs[REG_MCRH] = sum; |
| 2391 | if (v) |
| 2392 | State.regs[REG_MCVF] = 1; |
| 2393 | } |
| 2394 | |
| 2395 | // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn |
| 2396 | 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste |
| 2397 | "mcste" |
| 2398 | *am33 |
| 2399 | *am33_2 |
| 2400 | { |
| 2401 | int dstreg; |
| 2402 | |
| 2403 | PC = cia; |
| 2404 | dstreg = translate_rreg (SD_, RN0); |
| 2405 | |
| 2406 | PSW &= ~(PSW_V | PSW_C); |
| 2407 | PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); |
| 2408 | |
| 2409 | /* 32bit saturation. */ |
| 2410 | if (IMM8 == 0x20) |
| 2411 | { |
| 2412 | signed64 tmp; |
| 2413 | |
| 2414 | tmp = State.regs[REG_MCRH]; |
| 2415 | tmp <<= 32; |
| 2416 | tmp += State.regs[REG_MCRL]; |
| 2417 | |
| 2418 | if (tmp > 0x7fffffff) |
| 2419 | State.regs[dstreg] = 0x7fffffff; |
| 2420 | else if (tmp < 0xffffffff80000000LL) |
| 2421 | State.regs[dstreg] = 0x80000000; |
| 2422 | else |
| 2423 | State.regs[dstreg] = tmp; |
| 2424 | } |
| 2425 | /* 16bit saturation */ |
| 2426 | else if (IMM8 == 0x10) |
| 2427 | { |
| 2428 | signed64 tmp; |
| 2429 | |
| 2430 | tmp = State.regs[REG_MCRH]; |
| 2431 | tmp <<= 32; |
| 2432 | tmp += State.regs[REG_MCRL]; |
| 2433 | |
| 2434 | if (tmp > 0x7fff) |
| 2435 | State.regs[dstreg] = 0x7fff; |
| 2436 | else if (tmp < 0xffffffffffff8000LL) |
| 2437 | State.regs[dstreg] = 0x8000; |
| 2438 | else |
| 2439 | State.regs[dstreg] = tmp; |
| 2440 | } |
| 2441 | /* 8 bit saturation */ |
| 2442 | else if (IMM8 == 0x8) |
| 2443 | { |
| 2444 | signed64 tmp; |
| 2445 | |
| 2446 | tmp = State.regs[REG_MCRH]; |
| 2447 | tmp <<= 32; |
| 2448 | tmp += State.regs[REG_MCRL]; |
| 2449 | |
| 2450 | if (tmp > 0x7f) |
| 2451 | State.regs[dstreg] = 0x7f; |
| 2452 | else if (tmp < 0xffffffffffffff80LL) |
| 2453 | State.regs[dstreg] = 0x80; |
| 2454 | else |
| 2455 | State.regs[dstreg] = tmp; |
| 2456 | } |
| 2457 | /* 9 bit saturation */ |
| 2458 | else if (IMM8 == 0x9) |
| 2459 | { |
| 2460 | signed64 tmp; |
| 2461 | |
| 2462 | tmp = State.regs[REG_MCRH]; |
| 2463 | tmp <<= 32; |
| 2464 | tmp += State.regs[REG_MCRL]; |
| 2465 | |
| 2466 | if (tmp > 0x80) |
| 2467 | State.regs[dstreg] = 0x80; |
| 2468 | else if (tmp < 0xffffffffffffff81LL) |
| 2469 | State.regs[dstreg] = 0x81; |
| 2470 | else |
| 2471 | State.regs[dstreg] = tmp; |
| 2472 | } |
| 2473 | /* 9 bit saturation */ |
| 2474 | else if (IMM8 == 0x30) |
| 2475 | { |
| 2476 | signed64 tmp; |
| 2477 | |
| 2478 | tmp = State.regs[REG_MCRH]; |
| 2479 | tmp <<= 32; |
| 2480 | tmp += State.regs[REG_MCRL]; |
| 2481 | |
| 2482 | if (tmp > 0x7fffffffffffLL) |
| 2483 | tmp = 0x7fffffffffffLL; |
| 2484 | else if (tmp < 0xffff800000000000LL) |
| 2485 | tmp = 0xffff800000000000LL; |
| 2486 | |
| 2487 | tmp >>= 16; |
| 2488 | State.regs[dstreg] = tmp; |
| 2489 | } |
| 2490 | } |
| 2491 | |
| 2492 | // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd |
| 2493 | 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add |
| 2494 | "add" |
| 2495 | *am33 |
| 2496 | *am33_2 |
| 2497 | { |
| 2498 | int z, c, n, v; |
| 2499 | unsigned32 sum, source1, source2; |
| 2500 | int srcreg1, srcreg2, dstreg; |
| 2501 | |
| 2502 | PC = cia; |
| 2503 | srcreg1 = translate_rreg (SD_, RM2); |
| 2504 | srcreg2 = translate_rreg (SD_, RN0); |
| 2505 | dstreg = translate_rreg (SD_, RD0); |
| 2506 | |
| 2507 | source1 = State.regs[srcreg1]; |
| 2508 | source2 = State.regs[srcreg2]; |
| 2509 | sum = source1 + source2; |
| 2510 | State.regs[dstreg] = sum; |
| 2511 | |
| 2512 | z = (sum == 0); |
| 2513 | n = (sum & 0x80000000); |
| 2514 | c = (sum < source1) || (sum < source2); |
| 2515 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) |
| 2516 | && (source1 & 0x80000000) != (sum & 0x80000000)); |
| 2517 | |
| 2518 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 2519 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 2520 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 2521 | } |
| 2522 | |
| 2523 | // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd |
| 2524 | 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc |
| 2525 | "addc" |
| 2526 | *am33 |
| 2527 | *am33_2 |
| 2528 | { |
| 2529 | int z, c, n, v; |
| 2530 | unsigned32 sum, source1, source2; |
| 2531 | int srcreg1, srcreg2, dstreg; |
| 2532 | |
| 2533 | PC = cia; |
| 2534 | srcreg1 = translate_rreg (SD_, RM2); |
| 2535 | srcreg2 = translate_rreg (SD_, RN0); |
| 2536 | dstreg = translate_rreg (SD_, RD0); |
| 2537 | |
| 2538 | source1 = State.regs[srcreg1]; |
| 2539 | source2 = State.regs[srcreg2]; |
| 2540 | sum = source1 + source2 + ((PSW & PSW_C) != 0); |
| 2541 | State.regs[dstreg] = sum; |
| 2542 | |
| 2543 | z = ((PSW & PSW_Z) != 0) && (sum == 0); |
| 2544 | n = (sum & 0x80000000); |
| 2545 | c = (sum < source1) || (sum < source2); |
| 2546 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) |
| 2547 | && (source1 & 0x80000000) != (sum & 0x80000000)); |
| 2548 | |
| 2549 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 2550 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 2551 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 2552 | } |
| 2553 | |
| 2554 | // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd |
| 2555 | 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub |
| 2556 | "sub" |
| 2557 | *am33 |
| 2558 | *am33_2 |
| 2559 | { |
| 2560 | int z, c, n, v; |
| 2561 | unsigned32 difference, source1, source2; |
| 2562 | int srcreg1, srcreg2, dstreg; |
| 2563 | |
| 2564 | PC = cia; |
| 2565 | srcreg1 = translate_rreg (SD_, RM2); |
| 2566 | srcreg2 = translate_rreg (SD_, RN0); |
| 2567 | dstreg = translate_rreg (SD_, RD0); |
| 2568 | |
| 2569 | source1 = State.regs[srcreg1]; |
| 2570 | source2 = State.regs[srcreg2]; |
| 2571 | difference = source2 - source1; |
| 2572 | State.regs[dstreg] = difference; |
| 2573 | |
| 2574 | z = (difference == 0); |
| 2575 | n = (difference & 0x80000000); |
| 2576 | c = (source1 > source2); |
| 2577 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) |
| 2578 | && (source1 & 0x80000000) != (difference & 0x80000000)); |
| 2579 | |
| 2580 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 2581 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 2582 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 2583 | } |
| 2584 | |
| 2585 | // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd |
| 2586 | 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc |
| 2587 | "subc" |
| 2588 | *am33 |
| 2589 | *am33_2 |
| 2590 | { |
| 2591 | int z, c, n, v; |
| 2592 | unsigned32 difference, source1, source2; |
| 2593 | int srcreg1, srcreg2, dstreg; |
| 2594 | |
| 2595 | PC = cia; |
| 2596 | srcreg1 = translate_rreg (SD_, RM2); |
| 2597 | srcreg2 = translate_rreg (SD_, RN0); |
| 2598 | dstreg = translate_rreg (SD_, RD0); |
| 2599 | |
| 2600 | source1 = State.regs[srcreg1]; |
| 2601 | source2 = State.regs[srcreg2]; |
| 2602 | difference = source2 - source1 - ((PSW & PSW_C) != 0); |
| 2603 | State.regs[dstreg] = difference; |
| 2604 | |
| 2605 | z = ((PSW & PSW_Z) != 0) && (difference == 0); |
| 2606 | n = (difference & 0x80000000); |
| 2607 | c = (source1 > source2); |
| 2608 | v = ((source1 & 0x80000000) == (source2 & 0x80000000) |
| 2609 | && (source1 & 0x80000000) != (difference & 0x80000000)); |
| 2610 | |
| 2611 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 2612 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 2613 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 2614 | } |
| 2615 | |
| 2616 | // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd |
| 2617 | 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and |
| 2618 | "and" |
| 2619 | *am33 |
| 2620 | *am33_2 |
| 2621 | { |
| 2622 | int z, n; |
| 2623 | int srcreg1, srcreg2, dstreg; |
| 2624 | |
| 2625 | PC = cia; |
| 2626 | srcreg1 = translate_rreg (SD_, RM2); |
| 2627 | srcreg2 = translate_rreg (SD_, RN0); |
| 2628 | dstreg = translate_rreg (SD_, RD0); |
| 2629 | |
| 2630 | State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2]; |
| 2631 | |
| 2632 | z = (State.regs[dstreg] == 0); |
| 2633 | n = (State.regs[dstreg] & 0x80000000); |
| 2634 | |
| 2635 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 2636 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2637 | } |
| 2638 | |
| 2639 | // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd |
| 2640 | 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or |
| 2641 | "or" |
| 2642 | *am33 |
| 2643 | *am33_2 |
| 2644 | { |
| 2645 | int z, n; |
| 2646 | int srcreg1, srcreg2, dstreg; |
| 2647 | |
| 2648 | PC = cia; |
| 2649 | srcreg1 = translate_rreg (SD_, RM2); |
| 2650 | srcreg2 = translate_rreg (SD_, RN0); |
| 2651 | dstreg = translate_rreg (SD_, RD0); |
| 2652 | |
| 2653 | State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2]; |
| 2654 | |
| 2655 | z = (State.regs[dstreg] == 0); |
| 2656 | n = (State.regs[dstreg] & 0x80000000); |
| 2657 | |
| 2658 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 2659 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2660 | } |
| 2661 | |
| 2662 | // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd |
| 2663 | 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor |
| 2664 | "xor" |
| 2665 | *am33 |
| 2666 | *am33_2 |
| 2667 | { |
| 2668 | int z, n; |
| 2669 | int srcreg1, srcreg2, dstreg; |
| 2670 | |
| 2671 | PC = cia; |
| 2672 | srcreg1 = translate_rreg (SD_, RM2); |
| 2673 | srcreg2 = translate_rreg (SD_, RN0); |
| 2674 | dstreg = translate_rreg (SD_, RD0); |
| 2675 | |
| 2676 | State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2]; |
| 2677 | |
| 2678 | z = (State.regs[dstreg] == 0); |
| 2679 | n = (State.regs[dstreg] & 0x80000000); |
| 2680 | |
| 2681 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 2682 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2683 | } |
| 2684 | |
| 2685 | // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd |
| 2686 | 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr |
| 2687 | "asr" |
| 2688 | *am33 |
| 2689 | *am33_2 |
| 2690 | { |
| 2691 | int z, c, n; |
| 2692 | signed32 temp; |
| 2693 | int srcreg1, srcreg2, dstreg; |
| 2694 | |
| 2695 | PC = cia; |
| 2696 | srcreg1 = translate_rreg (SD_, RM2); |
| 2697 | srcreg2 = translate_rreg (SD_, RN0); |
| 2698 | dstreg = translate_rreg (SD_, RD0); |
| 2699 | |
| 2700 | temp = State.regs[srcreg2]; |
| 2701 | c = temp & 1; |
| 2702 | temp >>= State.regs[srcreg1]; |
| 2703 | State.regs[dstreg] = temp; |
| 2704 | |
| 2705 | z = (State.regs[dstreg] == 0); |
| 2706 | n = (State.regs[dstreg] & 0x80000000); |
| 2707 | |
| 2708 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 2709 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2710 | } |
| 2711 | |
| 2712 | // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd |
| 2713 | 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr |
| 2714 | "lsr" |
| 2715 | *am33 |
| 2716 | *am33_2 |
| 2717 | { |
| 2718 | int z, c, n; |
| 2719 | int srcreg1, srcreg2, dstreg; |
| 2720 | |
| 2721 | PC = cia; |
| 2722 | srcreg1 = translate_rreg (SD_, RM2); |
| 2723 | srcreg2 = translate_rreg (SD_, RN0); |
| 2724 | dstreg = translate_rreg (SD_, RD0); |
| 2725 | |
| 2726 | c = State.regs[srcreg2] & 1; |
| 2727 | State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1]; |
| 2728 | |
| 2729 | z = (State.regs[dstreg] == 0); |
| 2730 | n = (State.regs[dstreg] & 0x80000000); |
| 2731 | |
| 2732 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 2733 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2734 | } |
| 2735 | |
| 2736 | // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd |
| 2737 | 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl |
| 2738 | "asl" |
| 2739 | *am33 |
| 2740 | *am33_2 |
| 2741 | { |
| 2742 | int z, n; |
| 2743 | int srcreg1, srcreg2, dstreg; |
| 2744 | |
| 2745 | PC = cia; |
| 2746 | srcreg1 = translate_rreg (SD_, RM2); |
| 2747 | srcreg2 = translate_rreg (SD_, RN0); |
| 2748 | dstreg = translate_rreg (SD_, RD0); |
| 2749 | |
| 2750 | State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1]; |
| 2751 | |
| 2752 | z = (State.regs[dstreg] == 0); |
| 2753 | n = (State.regs[dstreg] & 0x80000000); |
| 2754 | |
| 2755 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 2756 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2757 | } |
| 2758 | |
| 2759 | // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2 |
| 2760 | 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul |
| 2761 | "mul" |
| 2762 | *am33 |
| 2763 | *am33_2 |
| 2764 | { |
| 2765 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 2766 | signed64 temp; |
| 2767 | int n, z; |
| 2768 | |
| 2769 | PC = cia; |
| 2770 | srcreg1 = translate_rreg (SD_, RM2); |
| 2771 | srcreg2 = translate_rreg (SD_, RN0); |
| 2772 | dstreg1 = translate_rreg (SD_, RD0); |
| 2773 | dstreg2 = translate_rreg (SD_, RD2); |
| 2774 | |
| 2775 | temp = ((signed64)(signed32)State.regs[srcreg1] |
| 2776 | * (signed64)(signed32)State.regs[srcreg2]); |
| 2777 | State.regs[dstreg2] = temp & 0xffffffff; |
| 2778 | State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; |
| 2779 | |
| 2780 | z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); |
| 2781 | n = (State.regs[dstreg1] & 0x80000000); |
| 2782 | |
| 2783 | PSW &= ~(PSW_Z | PSW_N); |
| 2784 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2785 | } |
| 2786 | |
| 2787 | // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2 |
| 2788 | 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu |
| 2789 | "mulu" |
| 2790 | *am33 |
| 2791 | *am33_2 |
| 2792 | { |
| 2793 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 2794 | signed64 temp; |
| 2795 | int n, z; |
| 2796 | |
| 2797 | PC = cia; |
| 2798 | srcreg1 = translate_rreg (SD_, RM2); |
| 2799 | srcreg2 = translate_rreg (SD_, RN0); |
| 2800 | dstreg1 = translate_rreg (SD_, RD0); |
| 2801 | dstreg2 = translate_rreg (SD_, RD2); |
| 2802 | |
| 2803 | temp = ((unsigned64)State.regs[srcreg1] |
| 2804 | * (unsigned64)State.regs[srcreg2]); |
| 2805 | State.regs[dstreg2] = temp & 0xffffffff; |
| 2806 | State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; |
| 2807 | |
| 2808 | z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); |
| 2809 | n = (State.regs[dstreg1] & 0x80000000); |
| 2810 | |
| 2811 | PSW &= ~(PSW_Z | PSW_N); |
| 2812 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); |
| 2813 | } |
| 2814 | |
| 2815 | // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn |
| 2816 | 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov |
| 2817 | "mov" |
| 2818 | *am33 |
| 2819 | *am33_2 |
| 2820 | { |
| 2821 | int dstreg; |
| 2822 | |
| 2823 | PC = cia; |
| 2824 | dstreg = translate_rreg (SD_, RN2); |
| 2825 | State.regs[dstreg] = load_word (IMM8); |
| 2826 | } |
| 2827 | |
| 2828 | // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8) |
| 2829 | 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov |
| 2830 | "mov" |
| 2831 | *am33 |
| 2832 | *am33_2 |
| 2833 | { |
| 2834 | int srcreg; |
| 2835 | |
| 2836 | PC = cia; |
| 2837 | srcreg = translate_rreg (SD_, RM2); |
| 2838 | store_word (IMM8, State.regs[srcreg]); |
| 2839 | } |
| 2840 | |
| 2841 | // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn |
| 2842 | 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu |
| 2843 | "movbu" |
| 2844 | *am33 |
| 2845 | *am33_2 |
| 2846 | { |
| 2847 | int dstreg; |
| 2848 | |
| 2849 | PC = cia; |
| 2850 | dstreg = translate_rreg (SD_, RN2); |
| 2851 | State.regs[dstreg] = load_byte (IMM8); |
| 2852 | } |
| 2853 | |
| 2854 | // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8) |
| 2855 | 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu |
| 2856 | "movbu" |
| 2857 | *am33 |
| 2858 | *am33_2 |
| 2859 | { |
| 2860 | int srcreg; |
| 2861 | |
| 2862 | PC = cia; |
| 2863 | srcreg = translate_rreg (SD_, RM2); |
| 2864 | store_byte (IMM8, State.regs[srcreg]); |
| 2865 | } |
| 2866 | |
| 2867 | // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn |
| 2868 | 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu |
| 2869 | "movhu" |
| 2870 | *am33 |
| 2871 | *am33_2 |
| 2872 | { |
| 2873 | int dstreg; |
| 2874 | |
| 2875 | PC = cia; |
| 2876 | dstreg = translate_rreg (SD_, RN2); |
| 2877 | State.regs[dstreg] = load_half (IMM8); |
| 2878 | } |
| 2879 | |
| 2880 | // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8) |
| 2881 | 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu |
| 2882 | "movhu" |
| 2883 | *am33 |
| 2884 | *am33_2 |
| 2885 | { |
| 2886 | int srcreg; |
| 2887 | |
| 2888 | PC = cia; |
| 2889 | srcreg = translate_rreg (SD_, RM2); |
| 2890 | store_half (IMM8, State.regs[srcreg]); |
| 2891 | } |
| 2892 | |
| 2893 | // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn |
| 2894 | 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov |
| 2895 | "mov" |
| 2896 | *am33 |
| 2897 | *am33_2 |
| 2898 | { |
| 2899 | int srcreg1, srcreg2, dstreg; |
| 2900 | |
| 2901 | PC = cia; |
| 2902 | srcreg1 = translate_rreg (SD_, RM0); |
| 2903 | srcreg2 = translate_rreg (SD_, RI0); |
| 2904 | dstreg = translate_rreg (SD_, RN0); |
| 2905 | State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]); |
| 2906 | } |
| 2907 | |
| 2908 | // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm) |
| 2909 | 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov |
| 2910 | "mov" |
| 2911 | *am33 |
| 2912 | *am33_2 |
| 2913 | { |
| 2914 | int srcreg, dstreg1, dstreg2; |
| 2915 | |
| 2916 | PC = cia; |
| 2917 | srcreg = translate_rreg (SD_, RM0); |
| 2918 | dstreg1 = translate_rreg (SD_, RI0); |
| 2919 | dstreg2 = translate_rreg (SD_, RN0); |
| 2920 | store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); |
| 2921 | } |
| 2922 | |
| 2923 | // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn |
| 2924 | 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu |
| 2925 | "movbu" |
| 2926 | *am33 |
| 2927 | *am33_2 |
| 2928 | { |
| 2929 | int srcreg1, srcreg2, dstreg; |
| 2930 | |
| 2931 | PC = cia; |
| 2932 | srcreg1 = translate_rreg (SD_, RM0); |
| 2933 | srcreg2 = translate_rreg (SD_, RI0); |
| 2934 | dstreg = translate_rreg (SD_, RN0); |
| 2935 | State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]); |
| 2936 | } |
| 2937 | |
| 2938 | // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm) |
| 2939 | 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu |
| 2940 | "movbu" |
| 2941 | *am33 |
| 2942 | *am33_2 |
| 2943 | { |
| 2944 | int srcreg, dstreg1, dstreg2; |
| 2945 | |
| 2946 | PC = cia; |
| 2947 | srcreg = translate_rreg (SD_, RM0); |
| 2948 | dstreg1 = translate_rreg (SD_, RI0); |
| 2949 | dstreg2 = translate_rreg (SD_, RN0); |
| 2950 | store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); |
| 2951 | } |
| 2952 | |
| 2953 | // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn |
| 2954 | 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu |
| 2955 | "movhu" |
| 2956 | *am33 |
| 2957 | *am33_2 |
| 2958 | { |
| 2959 | int srcreg1, srcreg2, dstreg; |
| 2960 | |
| 2961 | PC = cia; |
| 2962 | srcreg1 = translate_rreg (SD_, RM0); |
| 2963 | srcreg2 = translate_rreg (SD_, RI0); |
| 2964 | dstreg = translate_rreg (SD_, RN0); |
| 2965 | State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]); |
| 2966 | } |
| 2967 | |
| 2968 | // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm) |
| 2969 | 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu |
| 2970 | "movhu" |
| 2971 | *am33 |
| 2972 | *am33_2 |
| 2973 | { |
| 2974 | int srcreg, dstreg1, dstreg2; |
| 2975 | |
| 2976 | PC = cia; |
| 2977 | srcreg = translate_rreg (SD_, RM0); |
| 2978 | dstreg1 = translate_rreg (SD_, RI0); |
| 2979 | dstreg2 = translate_rreg (SD_, RN0); |
| 2980 | store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); |
| 2981 | } |
| 2982 | |
| 2983 | // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2 |
| 2984 | 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac |
| 2985 | "mac" |
| 2986 | *am33 |
| 2987 | *am33_2 |
| 2988 | { |
| 2989 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 2990 | signed64 temp; |
| 2991 | unsigned32 sum; |
| 2992 | int c, v; |
| 2993 | |
| 2994 | PC = cia; |
| 2995 | srcreg1 = translate_rreg (SD_, RM2); |
| 2996 | srcreg2 = translate_rreg (SD_, RN0); |
| 2997 | dstreg1 = translate_rreg (SD_, RD0); |
| 2998 | dstreg2 = translate_rreg (SD_, RD2); |
| 2999 | |
| 3000 | temp = ((signed64)(signed32)State.regs[srcreg1] |
| 3001 | * (signed64)(signed32)State.regs[srcreg2]); |
| 3002 | |
| 3003 | sum = State.regs[dstreg2] + (temp & 0xffffffff); |
| 3004 | c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); |
| 3005 | State.regs[dstreg2] = sum; |
| 3006 | temp >>= 32; |
| 3007 | temp &= 0xffffffff; |
| 3008 | sum = State.regs[dstreg1] + temp + c; |
| 3009 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) |
| 3010 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3011 | State.regs[dstreg1] = sum; |
| 3012 | if (v) |
| 3013 | { |
| 3014 | State.regs[REG_MCVF] = 1; |
| 3015 | PSW &= ~(PSW_V); |
| 3016 | PSW |= (( v ? PSW_V : 0)); |
| 3017 | } |
| 3018 | } |
| 3019 | |
| 3020 | // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2 |
| 3021 | 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu |
| 3022 | "macu" |
| 3023 | *am33 |
| 3024 | *am33_2 |
| 3025 | { |
| 3026 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 3027 | signed64 temp; |
| 3028 | unsigned32 sum; |
| 3029 | int c, v; |
| 3030 | |
| 3031 | PC = cia; |
| 3032 | srcreg1 = translate_rreg (SD_, RM2); |
| 3033 | srcreg2 = translate_rreg (SD_, RN0); |
| 3034 | dstreg1 = translate_rreg (SD_, RD0); |
| 3035 | dstreg2 = translate_rreg (SD_, RD2); |
| 3036 | |
| 3037 | temp = ((unsigned64)State.regs[srcreg1] |
| 3038 | * (unsigned64)State.regs[srcreg2]); |
| 3039 | |
| 3040 | sum = State.regs[dstreg2] + (temp & 0xffffffff); |
| 3041 | c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); |
| 3042 | State.regs[dstreg2] = sum; |
| 3043 | temp >>= 32; |
| 3044 | temp &= 0xffffffff; |
| 3045 | sum = State.regs[dstreg1] + temp + c; |
| 3046 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) |
| 3047 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3048 | State.regs[dstreg1] = sum; |
| 3049 | if (v) |
| 3050 | { |
| 3051 | State.regs[REG_MCVF] = 1; |
| 3052 | PSW &= ~(PSW_V); |
| 3053 | PSW |= (( v ? PSW_V : 0)); |
| 3054 | } |
| 3055 | } |
| 3056 | |
| 3057 | // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1 |
| 3058 | 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb |
| 3059 | "macb" |
| 3060 | *am33 |
| 3061 | *am33_2 |
| 3062 | { |
| 3063 | int srcreg1, srcreg2, dstreg; |
| 3064 | signed32 temp, sum; |
| 3065 | int v; |
| 3066 | |
| 3067 | PC = cia; |
| 3068 | srcreg1 = translate_rreg (SD_, RM2); |
| 3069 | srcreg2 = translate_rreg (SD_, RN0); |
| 3070 | dstreg = translate_rreg (SD_, RD0); |
| 3071 | |
| 3072 | temp = ((signed32)(State.regs[srcreg2] & 0xff) |
| 3073 | * (signed32)(State.regs[srcreg1] & 0xff)); |
| 3074 | sum = State.regs[dstreg] + temp; |
| 3075 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) |
| 3076 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3077 | State.regs[dstreg] = sum; |
| 3078 | if (v) |
| 3079 | { |
| 3080 | State.regs[REG_MCVF] = 1; |
| 3081 | PSW &= ~(PSW_V); |
| 3082 | PSW |= ((v ? PSW_V : 0)); |
| 3083 | } |
| 3084 | } |
| 3085 | |
| 3086 | // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1 |
| 3087 | 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu |
| 3088 | "macbu" |
| 3089 | *am33 |
| 3090 | *am33_2 |
| 3091 | { |
| 3092 | int srcreg1, srcreg2, dstreg; |
| 3093 | signed32 temp, sum; |
| 3094 | int v; |
| 3095 | |
| 3096 | PC = cia; |
| 3097 | srcreg1 = translate_rreg (SD_, RM2); |
| 3098 | srcreg2 = translate_rreg (SD_, RN0); |
| 3099 | dstreg = translate_rreg (SD_, RD0); |
| 3100 | |
| 3101 | temp = ((unsigned32)(State.regs[srcreg2] & 0xff) |
| 3102 | * (unsigned32)(State.regs[srcreg1] & 0xff)); |
| 3103 | sum = State.regs[dstreg] + temp; |
| 3104 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) |
| 3105 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3106 | State.regs[dstreg] = sum; |
| 3107 | if (v) |
| 3108 | { |
| 3109 | State.regs[REG_MCVF] = 1; |
| 3110 | PSW &= ~(PSW_V); |
| 3111 | PSW |= ((v ? PSW_V : 0)); |
| 3112 | } |
| 3113 | } |
| 3114 | |
| 3115 | // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2 |
| 3116 | 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach |
| 3117 | "mach" |
| 3118 | *am33 |
| 3119 | *am33_2 |
| 3120 | { |
| 3121 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 3122 | signed64 temp, sum; |
| 3123 | int v; |
| 3124 | |
| 3125 | PC = cia; |
| 3126 | srcreg1 = translate_rreg (SD_, RM2); |
| 3127 | srcreg2 = translate_rreg (SD_, RN0); |
| 3128 | dstreg1 = translate_rreg (SD_, RD0); |
| 3129 | dstreg2 = translate_rreg (SD_, RD0); |
| 3130 | |
| 3131 | temp = ((signed32)(State.regs[srcreg2] & 0xffff) |
| 3132 | * (signed32)(State.regs[srcreg1] & 0xffff)); |
| 3133 | State.regs[dstreg2] += (temp & 0xffffffff); |
| 3134 | sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); |
| 3135 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) |
| 3136 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3137 | State.regs[dstreg1] = sum; |
| 3138 | if (v) |
| 3139 | { |
| 3140 | State.regs[REG_MCVF] = 1; |
| 3141 | PSW &= ~(PSW_V); |
| 3142 | PSW |= ((v ? PSW_V : 0)); |
| 3143 | } |
| 3144 | } |
| 3145 | |
| 3146 | // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2 |
| 3147 | 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu |
| 3148 | "machu" |
| 3149 | *am33 |
| 3150 | *am33_2 |
| 3151 | { |
| 3152 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 3153 | signed64 temp, sum; |
| 3154 | int v; |
| 3155 | |
| 3156 | PC = cia; |
| 3157 | srcreg1 = translate_rreg (SD_, RM2); |
| 3158 | srcreg2 = translate_rreg (SD_, RN0); |
| 3159 | dstreg1 = translate_rreg (SD_, RD0); |
| 3160 | dstreg2 = translate_rreg (SD_, RD0); |
| 3161 | |
| 3162 | temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) |
| 3163 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); |
| 3164 | State.regs[dstreg2] += (temp & 0xffffffff); |
| 3165 | sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); |
| 3166 | v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) |
| 3167 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3168 | State.regs[dstreg1] = sum; |
| 3169 | if (v) |
| 3170 | { |
| 3171 | State.regs[REG_MCVF] = 1; |
| 3172 | PSW &= ~(PSW_V); |
| 3173 | PSW |= ((v ? PSW_V : 0)); |
| 3174 | } |
| 3175 | } |
| 3176 | |
| 3177 | // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1 |
| 3178 | 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach |
| 3179 | "dmach" |
| 3180 | *am33 |
| 3181 | *am33_2 |
| 3182 | { |
| 3183 | int srcreg1, srcreg2, dstreg; |
| 3184 | signed32 temp, temp2, sum; |
| 3185 | int v; |
| 3186 | |
| 3187 | PC = cia; |
| 3188 | srcreg1 = translate_rreg (SD_, RM2); |
| 3189 | srcreg2 = translate_rreg (SD_, RN0); |
| 3190 | dstreg = translate_rreg (SD_, RD0); |
| 3191 | |
| 3192 | temp = ((signed32)(State.regs[srcreg2] & 0xffff) |
| 3193 | * (signed32)(State.regs[srcreg1] & 0xffff)); |
| 3194 | temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) |
| 3195 | * (signed32)((State.regs[srcreg2] >> 16) & 0xffff)); |
| 3196 | sum = temp + temp2 + State.regs[dstreg]; |
| 3197 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) |
| 3198 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3199 | State.regs[dstreg] = sum; |
| 3200 | if (v) |
| 3201 | { |
| 3202 | State.regs[REG_MCVF] = 1; |
| 3203 | PSW &= ~(PSW_V); |
| 3204 | PSW |= ((v ? PSW_V : 0)); |
| 3205 | } |
| 3206 | } |
| 3207 | |
| 3208 | // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1 |
| 3209 | 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu |
| 3210 | "dmachu" |
| 3211 | *am33 |
| 3212 | *am33_2 |
| 3213 | { |
| 3214 | int srcreg1, srcreg2, dstreg; |
| 3215 | signed32 temp, temp2, sum; |
| 3216 | int v; |
| 3217 | |
| 3218 | PC = cia; |
| 3219 | srcreg1 = translate_rreg (SD_, RM2); |
| 3220 | srcreg2 = translate_rreg (SD_, RN0); |
| 3221 | dstreg = translate_rreg (SD_, RD0); |
| 3222 | |
| 3223 | temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) |
| 3224 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); |
| 3225 | temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) |
| 3226 | * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); |
| 3227 | sum = temp + temp2 + State.regs[dstreg]; |
| 3228 | v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) |
| 3229 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3230 | State.regs[dstreg] = sum; |
| 3231 | if (v) |
| 3232 | { |
| 3233 | State.regs[REG_MCVF] = 1; |
| 3234 | PSW &= ~(PSW_V); |
| 3235 | PSW |= ((v ? PSW_V : 0)); |
| 3236 | } |
| 3237 | } |
| 3238 | |
| 3239 | // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2 |
| 3240 | 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh |
| 3241 | "dmulh" |
| 3242 | *am33 |
| 3243 | *am33_2 |
| 3244 | { |
| 3245 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 3246 | signed64 temp; |
| 3247 | |
| 3248 | PC = cia; |
| 3249 | srcreg1 = translate_rreg (SD_, RM2); |
| 3250 | srcreg2 = translate_rreg (SD_, RN0); |
| 3251 | dstreg1 = translate_rreg (SD_, RD0); |
| 3252 | dstreg2 = translate_rreg (SD_, RD2); |
| 3253 | |
| 3254 | temp = ((signed32)(State.regs[srcreg1] & 0xffff) |
| 3255 | * (signed32)(State.regs[srcreg1] & 0xffff)); |
| 3256 | State.regs[dstreg2] = temp; |
| 3257 | temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) |
| 3258 | * (signed32)((State.regs[srcreg1] >>16) & 0xffff)); |
| 3259 | State.regs[dstreg1] = temp; |
| 3260 | } |
| 3261 | |
| 3262 | // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2 |
| 3263 | 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu |
| 3264 | "dmulhu" |
| 3265 | *am33 |
| 3266 | *am33_2 |
| 3267 | { |
| 3268 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 3269 | signed64 temp; |
| 3270 | |
| 3271 | PC = cia; |
| 3272 | srcreg1 = translate_rreg (SD_, RM2); |
| 3273 | srcreg2 = translate_rreg (SD_, RN0); |
| 3274 | dstreg1 = translate_rreg (SD_, RD0); |
| 3275 | dstreg2 = translate_rreg (SD_, RD2); |
| 3276 | |
| 3277 | temp = ((unsigned32)(State.regs[srcreg1] & 0xffff) |
| 3278 | * (unsigned32)(State.regs[srcreg1] & 0xffff)); |
| 3279 | State.regs[dstreg2] = temp; |
| 3280 | temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) |
| 3281 | * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff)); |
| 3282 | State.regs[dstreg1] = temp; |
| 3283 | } |
| 3284 | |
| 3285 | // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn |
| 3286 | 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24 |
| 3287 | "sat24" |
| 3288 | *am33 |
| 3289 | *am33_2 |
| 3290 | { |
| 3291 | int srcreg, dstreg; |
| 3292 | int value, n, z; |
| 3293 | |
| 3294 | PC = cia; |
| 3295 | srcreg = translate_rreg (SD_, RM2); |
| 3296 | dstreg = translate_rreg (SD_, RN0); |
| 3297 | |
| 3298 | value = State.regs[srcreg]; |
| 3299 | |
| 3300 | if (value >= 0x7fffff) |
| 3301 | State.regs[dstreg] = 0x7fffff; |
| 3302 | else if (value <= 0xff800000) |
| 3303 | State.regs[dstreg] = 0xff800000; |
| 3304 | else |
| 3305 | State.regs[dstreg] = value; |
| 3306 | |
| 3307 | n = (State.regs[dstreg] & 0x800000) != 0; |
| 3308 | z = (State.regs[dstreg] == 0); |
| 3309 | PSW &= ~(PSW_Z | PSW_N); |
| 3310 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 3311 | } |
| 3312 | |
| 3313 | // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1 |
| 3314 | 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch |
| 3315 | "bsch" |
| 3316 | *am33 |
| 3317 | *am33_2 |
| 3318 | { |
| 3319 | int temp, c, i; |
| 3320 | int srcreg1, srcreg2, dstreg; |
| 3321 | int start; |
| 3322 | |
| 3323 | PC = cia; |
| 3324 | srcreg1 = translate_rreg (SD_, RM2); |
| 3325 | srcreg2 = translate_rreg (SD_, RN0); |
| 3326 | dstreg = translate_rreg (SD_, RD0); |
| 3327 | |
| 3328 | temp = State.regs[srcreg1]; |
| 3329 | start = (State.regs[srcreg2] & 0x1f) - 1; |
| 3330 | if (start == -1) |
| 3331 | start = 31; |
| 3332 | |
| 3333 | c = 0; |
| 3334 | for (i = start; i >= 0; i--) |
| 3335 | { |
| 3336 | if (temp & (1 << i)) |
| 3337 | { |
| 3338 | c = 1; |
| 3339 | State.regs[dstreg] = i; |
| 3340 | break; |
| 3341 | } |
| 3342 | } |
| 3343 | |
| 3344 | if (i < 0) |
| 3345 | { |
| 3346 | c = 0; |
| 3347 | State.regs[dstreg] = 0; |
| 3348 | } |
| 3349 | PSW &= ~(PSW_C); |
| 3350 | PSW |= (c ? PSW_C : 0); |
| 3351 | } |
| 3352 | |
| 3353 | // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn |
| 3354 | 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov |
| 3355 | "mov" |
| 3356 | *am33 |
| 3357 | *am33_2 |
| 3358 | { |
| 3359 | int dstreg; |
| 3360 | |
| 3361 | PC = cia; |
| 3362 | dstreg = translate_rreg (SD_, RN0); |
| 3363 | State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3364 | } |
| 3365 | |
| 3366 | // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn |
| 3367 | 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu |
| 3368 | "movu" |
| 3369 | *am33 |
| 3370 | *am33_2 |
| 3371 | { |
| 3372 | int dstreg; |
| 3373 | |
| 3374 | PC = cia; |
| 3375 | dstreg = translate_rreg (SD_, RN0); |
| 3376 | State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; |
| 3377 | } |
| 3378 | |
| 3379 | // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn |
| 3380 | 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add |
| 3381 | "add" |
| 3382 | *am33 |
| 3383 | *am33_2 |
| 3384 | { |
| 3385 | int dstreg; |
| 3386 | |
| 3387 | PC = cia; |
| 3388 | dstreg = translate_rreg (SD_, RN0); |
| 3389 | genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); |
| 3390 | } |
| 3391 | |
| 3392 | // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn |
| 3393 | 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc |
| 3394 | "addc" |
| 3395 | *am33 |
| 3396 | *am33_2 |
| 3397 | { |
| 3398 | int dstreg, z, n, c, v; |
| 3399 | unsigned32 sum, imm, reg2; |
| 3400 | |
| 3401 | PC = cia; |
| 3402 | dstreg = translate_rreg (SD_, RN0); |
| 3403 | |
| 3404 | imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3405 | reg2 = State.regs[dstreg]; |
| 3406 | sum = imm + reg2 + ((PSW & PSW_C) != 0); |
| 3407 | State.regs[dstreg] = sum; |
| 3408 | |
| 3409 | z = ((PSW & PSW_Z) != 0) && (sum == 0); |
| 3410 | n = (sum & 0x80000000); |
| 3411 | c = (sum < imm) || (sum < reg2); |
| 3412 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) |
| 3413 | && (reg2 & 0x80000000) != (sum & 0x80000000)); |
| 3414 | |
| 3415 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 3416 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 3417 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 3418 | } |
| 3419 | |
| 3420 | // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn |
| 3421 | 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub |
| 3422 | "sub" |
| 3423 | *am33 |
| 3424 | *am33_2 |
| 3425 | { |
| 3426 | int dstreg; |
| 3427 | |
| 3428 | PC = cia; |
| 3429 | dstreg = translate_rreg (SD_, RN0); |
| 3430 | genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); |
| 3431 | } |
| 3432 | |
| 3433 | // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn |
| 3434 | 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc |
| 3435 | "subc" |
| 3436 | *am33 |
| 3437 | *am33_2 |
| 3438 | { |
| 3439 | int dstreg, z, n, c, v; |
| 3440 | unsigned32 difference, imm, reg2; |
| 3441 | |
| 3442 | PC = cia; |
| 3443 | dstreg = translate_rreg (SD_, RN0); |
| 3444 | |
| 3445 | imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3446 | reg2 = State.regs[dstreg]; |
| 3447 | difference = reg2 - imm - ((PSW & PSW_C) != 0); |
| 3448 | State.regs[dstreg] = difference; |
| 3449 | |
| 3450 | z = ((PSW & PSW_Z) != 0) && (difference == 0); |
| 3451 | n = (difference & 0x80000000); |
| 3452 | c = (imm > reg2); |
| 3453 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) |
| 3454 | && (reg2 & 0x80000000) != (difference & 0x80000000)); |
| 3455 | |
| 3456 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 3457 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 3458 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 3459 | } |
| 3460 | |
| 3461 | // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn |
| 3462 | 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp |
| 3463 | "cmp" |
| 3464 | *am33 |
| 3465 | *am33_2 |
| 3466 | { |
| 3467 | int srcreg; |
| 3468 | |
| 3469 | PC = cia; |
| 3470 | srcreg = translate_rreg (SD_, RN0); |
| 3471 | genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]); |
| 3472 | } |
| 3473 | |
| 3474 | // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn |
| 3475 | 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov |
| 3476 | "mov" |
| 3477 | *am33 |
| 3478 | *am33_2 |
| 3479 | { |
| 3480 | int dstreg; |
| 3481 | |
| 3482 | PC = cia; |
| 3483 | dstreg = translate_xreg (SD_, XRN0); |
| 3484 | |
| 3485 | State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; |
| 3486 | } |
| 3487 | |
| 3488 | // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn |
| 3489 | 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and |
| 3490 | "and" |
| 3491 | *am33 |
| 3492 | *am33_2 |
| 3493 | { |
| 3494 | int dstreg; |
| 3495 | int z,n; |
| 3496 | |
| 3497 | PC = cia; |
| 3498 | dstreg = translate_rreg (SD_, RN0); |
| 3499 | |
| 3500 | State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); |
| 3501 | z = (State.regs[dstreg] == 0); |
| 3502 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3503 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 3504 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 3505 | } |
| 3506 | |
| 3507 | // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn |
| 3508 | 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or |
| 3509 | "or" |
| 3510 | *am33 |
| 3511 | *am33_2 |
| 3512 | { |
| 3513 | int dstreg; |
| 3514 | int z,n; |
| 3515 | |
| 3516 | PC = cia; |
| 3517 | dstreg = translate_rreg (SD_, RN0); |
| 3518 | |
| 3519 | State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); |
| 3520 | z = (State.regs[dstreg] == 0); |
| 3521 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3522 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 3523 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 3524 | } |
| 3525 | |
| 3526 | // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn |
| 3527 | 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor |
| 3528 | "xor" |
| 3529 | *am33 |
| 3530 | *am33_2 |
| 3531 | { |
| 3532 | int dstreg; |
| 3533 | int z,n; |
| 3534 | |
| 3535 | PC = cia; |
| 3536 | dstreg = translate_rreg (SD_, RN0); |
| 3537 | |
| 3538 | State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); |
| 3539 | z = (State.regs[dstreg] == 0); |
| 3540 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3541 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 3542 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 3543 | } |
| 3544 | |
| 3545 | // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn |
| 3546 | 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr |
| 3547 | "asr" |
| 3548 | *am33 |
| 3549 | *am33_2 |
| 3550 | { |
| 3551 | int dstreg; |
| 3552 | signed32 temp; |
| 3553 | int c, z, n; |
| 3554 | |
| 3555 | PC = cia; |
| 3556 | dstreg = translate_rreg (SD_, RN0); |
| 3557 | |
| 3558 | temp = State.regs[dstreg]; |
| 3559 | c = temp & 1; |
| 3560 | temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3561 | State.regs[dstreg] = temp; |
| 3562 | z = (State.regs[dstreg] == 0); |
| 3563 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3564 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 3565 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 3566 | } |
| 3567 | |
| 3568 | |
| 3569 | // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn |
| 3570 | 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr |
| 3571 | "lsr" |
| 3572 | *am33 |
| 3573 | *am33_2 |
| 3574 | { |
| 3575 | int dstreg; |
| 3576 | int z, n, c; |
| 3577 | |
| 3578 | PC = cia; |
| 3579 | dstreg = translate_rreg (SD_, RN0); |
| 3580 | |
| 3581 | c = State.regs[dstreg] & 1; |
| 3582 | State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3583 | z = (State.regs[dstreg] == 0); |
| 3584 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3585 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 3586 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 3587 | } |
| 3588 | |
| 3589 | // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn |
| 3590 | 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl |
| 3591 | "asl" |
| 3592 | *am33 |
| 3593 | *am33_2 |
| 3594 | { |
| 3595 | int dstreg; |
| 3596 | int z, n; |
| 3597 | |
| 3598 | PC = cia; |
| 3599 | dstreg = translate_rreg (SD_, RN0); |
| 3600 | |
| 3601 | State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3602 | z = (State.regs[dstreg] == 0); |
| 3603 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3604 | PSW &= ~(PSW_Z | PSW_N); |
| 3605 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 3606 | } |
| 3607 | |
| 3608 | // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn |
| 3609 | 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul |
| 3610 | "mul" |
| 3611 | *am33 |
| 3612 | *am33_2 |
| 3613 | { |
| 3614 | int dstreg; |
| 3615 | unsigned64 temp; |
| 3616 | int z, n; |
| 3617 | |
| 3618 | PC = cia; |
| 3619 | dstreg = translate_rreg (SD_, RN0); |
| 3620 | |
| 3621 | temp = ((signed64)(signed32)State.regs[dstreg] |
| 3622 | * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); |
| 3623 | State.regs[dstreg] = temp & 0xffffffff; |
| 3624 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 3625 | z = (State.regs[dstreg] == 0); |
| 3626 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3627 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 3628 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 3629 | } |
| 3630 | |
| 3631 | // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn |
| 3632 | 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu |
| 3633 | "mulu" |
| 3634 | *am33 |
| 3635 | *am33_2 |
| 3636 | { |
| 3637 | int dstreg; |
| 3638 | unsigned64 temp; |
| 3639 | int z, n; |
| 3640 | |
| 3641 | PC = cia; |
| 3642 | dstreg = translate_rreg (SD_, RN0); |
| 3643 | |
| 3644 | temp = ((unsigned64)State.regs[dstreg] |
| 3645 | * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); |
| 3646 | State.regs[dstreg] = temp & 0xffffffff; |
| 3647 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 3648 | z = (State.regs[dstreg] == 0); |
| 3649 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 3650 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 3651 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 3652 | } |
| 3653 | |
| 3654 | // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn |
| 3655 | 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst |
| 3656 | "btst" |
| 3657 | *am33 |
| 3658 | *am33_2 |
| 3659 | { |
| 3660 | int srcreg; |
| 3661 | |
| 3662 | PC = cia; |
| 3663 | srcreg = translate_rreg (SD_, RN0); |
| 3664 | genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); |
| 3665 | } |
| 3666 | |
| 3667 | // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn |
| 3668 | 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov |
| 3669 | "mov" |
| 3670 | *am33 |
| 3671 | *am33_2 |
| 3672 | { |
| 3673 | int srcreg, dstreg; |
| 3674 | |
| 3675 | PC = cia; |
| 3676 | srcreg = translate_rreg (SD_, RM0); |
| 3677 | dstreg = translate_rreg (SD_, RN2); |
| 3678 | State.regs[dstreg] = load_word (State.regs[srcreg] |
| 3679 | + EXTEND24 (FETCH24 (IMM24A, |
| 3680 | IMM24B, IMM24C))); |
| 3681 | } |
| 3682 | |
| 3683 | // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn) |
| 3684 | 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov |
| 3685 | "mov" |
| 3686 | *am33 |
| 3687 | *am33_2 |
| 3688 | { |
| 3689 | int srcreg, dstreg; |
| 3690 | |
| 3691 | PC = cia; |
| 3692 | srcreg = translate_rreg (SD_, RM2); |
| 3693 | dstreg = translate_rreg (SD_, RN0); |
| 3694 | store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), |
| 3695 | State.regs[srcreg]); |
| 3696 | } |
| 3697 | |
| 3698 | // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn |
| 3699 | 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu |
| 3700 | "movbu" |
| 3701 | *am33 |
| 3702 | *am33_2 |
| 3703 | { |
| 3704 | int srcreg, dstreg; |
| 3705 | |
| 3706 | PC = cia; |
| 3707 | srcreg = translate_rreg (SD_, RM0); |
| 3708 | dstreg = translate_rreg (SD_, RN2); |
| 3709 | State.regs[dstreg] = load_byte (State.regs[srcreg] |
| 3710 | + EXTEND24 (FETCH24 (IMM24A, |
| 3711 | IMM24B, IMM24C))); |
| 3712 | } |
| 3713 | |
| 3714 | // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn) |
| 3715 | 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu |
| 3716 | "movbu" |
| 3717 | *am33 |
| 3718 | *am33_2 |
| 3719 | { |
| 3720 | int srcreg, dstreg; |
| 3721 | |
| 3722 | PC = cia; |
| 3723 | srcreg = translate_rreg (SD_, RM2); |
| 3724 | dstreg = translate_rreg (SD_, RN0); |
| 3725 | store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), |
| 3726 | State.regs[srcreg]); |
| 3727 | } |
| 3728 | |
| 3729 | // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn |
| 3730 | 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu |
| 3731 | "movhu" |
| 3732 | *am33 |
| 3733 | *am33_2 |
| 3734 | { |
| 3735 | int srcreg, dstreg; |
| 3736 | |
| 3737 | PC = cia; |
| 3738 | srcreg = translate_rreg (SD_, RM0); |
| 3739 | dstreg = translate_rreg (SD_, RN2); |
| 3740 | State.regs[dstreg] = load_half (State.regs[srcreg] |
| 3741 | + EXTEND24 (FETCH24 (IMM24A, |
| 3742 | IMM24B, IMM24C))); |
| 3743 | } |
| 3744 | |
| 3745 | // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn) |
| 3746 | 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu |
| 3747 | "movhu" |
| 3748 | *am33 |
| 3749 | *am33_2 |
| 3750 | { |
| 3751 | int srcreg, dstreg; |
| 3752 | |
| 3753 | PC = cia; |
| 3754 | srcreg = translate_rreg (SD_, RM2); |
| 3755 | dstreg = translate_rreg (SD_, RN0); |
| 3756 | store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), |
| 3757 | State.regs[srcreg]); |
| 3758 | } |
| 3759 | |
| 3760 | // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn |
| 3761 | 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov |
| 3762 | "mov" |
| 3763 | *am33 |
| 3764 | *am33_2 |
| 3765 | { |
| 3766 | int srcreg, dstreg; |
| 3767 | |
| 3768 | PC = cia; |
| 3769 | srcreg = translate_rreg (SD_, RM0); |
| 3770 | dstreg = translate_rreg (SD_, RN2); |
| 3771 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 3772 | State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3773 | } |
| 3774 | |
| 3775 | // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+) |
| 3776 | 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov |
| 3777 | "mov" |
| 3778 | *am33 |
| 3779 | *am33_2 |
| 3780 | { |
| 3781 | int srcreg, dstreg; |
| 3782 | |
| 3783 | PC = cia; |
| 3784 | srcreg = translate_rreg (SD_, RM2); |
| 3785 | dstreg = translate_rreg (SD_, RN0); |
| 3786 | store_word (State.regs[dstreg], State.regs[srcreg]); |
| 3787 | State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3788 | } |
| 3789 | |
| 3790 | |
| 3791 | // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn |
| 3792 | 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov |
| 3793 | "mov" |
| 3794 | *am33 |
| 3795 | *am33_2 |
| 3796 | { |
| 3797 | int dstreg; |
| 3798 | |
| 3799 | PC = cia; |
| 3800 | dstreg = translate_rreg (SD_, RN2); |
| 3801 | State.regs[dstreg] = load_word (State.regs[REG_SP] |
| 3802 | + FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3803 | } |
| 3804 | |
| 3805 | // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp) |
| 3806 | 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov |
| 3807 | "mov" |
| 3808 | *am33 |
| 3809 | *am33_2 |
| 3810 | { |
| 3811 | int srcreg; |
| 3812 | |
| 3813 | PC = cia; |
| 3814 | srcreg = translate_rreg (SD_, RM2); |
| 3815 | store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), |
| 3816 | State.regs[srcreg]); |
| 3817 | } |
| 3818 | |
| 3819 | // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn |
| 3820 | 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu |
| 3821 | "movbu" |
| 3822 | *am33 |
| 3823 | *am33_2 |
| 3824 | { |
| 3825 | int dstreg; |
| 3826 | |
| 3827 | PC = cia; |
| 3828 | dstreg = translate_rreg (SD_, RN2); |
| 3829 | State.regs[dstreg] = load_byte (State.regs[REG_SP] |
| 3830 | + FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3831 | } |
| 3832 | |
| 3833 | // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp) |
| 3834 | 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu |
| 3835 | "movbu" |
| 3836 | *am33 |
| 3837 | *am33_2 |
| 3838 | { |
| 3839 | int srcreg; |
| 3840 | |
| 3841 | PC = cia; |
| 3842 | srcreg = translate_rreg (SD_, RM2); |
| 3843 | store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), |
| 3844 | State.regs[srcreg]); |
| 3845 | } |
| 3846 | |
| 3847 | // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn |
| 3848 | 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu |
| 3849 | "movhu" |
| 3850 | *am33 |
| 3851 | *am33_2 |
| 3852 | { |
| 3853 | int dstreg; |
| 3854 | |
| 3855 | PC = cia; |
| 3856 | dstreg = translate_rreg (SD_, RN2); |
| 3857 | State.regs[dstreg] = load_half (State.regs[REG_SP] |
| 3858 | + FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3859 | } |
| 3860 | |
| 3861 | // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp) |
| 3862 | 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu |
| 3863 | "movhu" |
| 3864 | *am33 |
| 3865 | *am33_2 |
| 3866 | { |
| 3867 | int srcreg; |
| 3868 | |
| 3869 | PC = cia; |
| 3870 | srcreg = translate_rreg (SD_, RM2); |
| 3871 | store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), |
| 3872 | State.regs[srcreg]); |
| 3873 | } |
| 3874 | |
| 3875 | // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn |
| 3876 | 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu |
| 3877 | "movhu" |
| 3878 | *am33 |
| 3879 | *am33_2 |
| 3880 | { |
| 3881 | int srcreg, dstreg; |
| 3882 | |
| 3883 | PC = cia; |
| 3884 | srcreg = translate_rreg (SD_, RM0); |
| 3885 | dstreg = translate_rreg (SD_, RN2); |
| 3886 | State.regs[dstreg] = load_half (State.regs[srcreg]); |
| 3887 | State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3888 | } |
| 3889 | |
| 3890 | // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+) |
| 3891 | 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu |
| 3892 | "movhu" |
| 3893 | *am33 |
| 3894 | *am33_2 |
| 3895 | { |
| 3896 | int srcreg, dstreg; |
| 3897 | |
| 3898 | PC = cia; |
| 3899 | srcreg = translate_rreg (SD_, RM2); |
| 3900 | dstreg = translate_rreg (SD_, RN0); |
| 3901 | store_half (State.regs[dstreg], State.regs[srcreg]); |
| 3902 | State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 3903 | } |
| 3904 | |
| 3905 | // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn |
| 3906 | 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac |
| 3907 | "mac" |
| 3908 | *am33 |
| 3909 | *am33_2 |
| 3910 | { |
| 3911 | int srcreg; |
| 3912 | signed64 temp, sum; |
| 3913 | int c, v; |
| 3914 | |
| 3915 | PC = cia; |
| 3916 | srcreg = translate_rreg (SD_, RN2); |
| 3917 | |
| 3918 | temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)) |
| 3919 | * (signed64)State.regs[srcreg]); |
| 3920 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 3921 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 3922 | State.regs[REG_MCRL] = sum; |
| 3923 | temp >>= 32; |
| 3924 | temp &= 0xffffffff; |
| 3925 | sum = State.regs[REG_MCRH] + temp + c; |
| 3926 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 3927 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3928 | State.regs[REG_MCRH] = sum; |
| 3929 | if (v) |
| 3930 | State.regs[REG_MCVF] = 1; |
| 3931 | } |
| 3932 | |
| 3933 | // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn |
| 3934 | 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu |
| 3935 | "macu" |
| 3936 | *am33 |
| 3937 | *am33_2 |
| 3938 | { |
| 3939 | int srcreg; |
| 3940 | signed64 temp, sum; |
| 3941 | int c, v; |
| 3942 | |
| 3943 | PC = cia; |
| 3944 | srcreg = translate_rreg (SD_, RN2); |
| 3945 | |
| 3946 | temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) |
| 3947 | * (unsigned64)State.regs[srcreg]); |
| 3948 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 3949 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 3950 | State.regs[REG_MCRL] = sum; |
| 3951 | temp >>= 32; |
| 3952 | temp &= 0xffffffff; |
| 3953 | sum = State.regs[REG_MCRH] + temp + c; |
| 3954 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 3955 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3956 | State.regs[REG_MCRH] = sum; |
| 3957 | if (v) |
| 3958 | State.regs[REG_MCVF] = 1; |
| 3959 | } |
| 3960 | |
| 3961 | // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn |
| 3962 | 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb |
| 3963 | "macb" |
| 3964 | *am33 |
| 3965 | *am33_2 |
| 3966 | { |
| 3967 | int srcreg; |
| 3968 | signed64 temp, sum; |
| 3969 | int c, v; |
| 3970 | |
| 3971 | PC = cia; |
| 3972 | srcreg = translate_rreg (SD_, RN2); |
| 3973 | |
| 3974 | temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)) |
| 3975 | * (signed64)State.regs[srcreg] & 0xff); |
| 3976 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 3977 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 3978 | State.regs[REG_MCRL] = sum; |
| 3979 | temp >>= 32; |
| 3980 | temp &= 0xffffffff; |
| 3981 | sum = State.regs[REG_MCRH] + temp + c; |
| 3982 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 3983 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 3984 | State.regs[REG_MCRH] = sum; |
| 3985 | if (v) |
| 3986 | State.regs[REG_MCVF] = 1; |
| 3987 | } |
| 3988 | |
| 3989 | // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn |
| 3990 | 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu |
| 3991 | "macbu" |
| 3992 | *am33 |
| 3993 | *am33_2 |
| 3994 | { |
| 3995 | int srcreg; |
| 3996 | signed64 temp, sum; |
| 3997 | int c, v; |
| 3998 | |
| 3999 | PC = cia; |
| 4000 | srcreg = translate_rreg (SD_, RN2); |
| 4001 | |
| 4002 | temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) |
| 4003 | * (unsigned64)State.regs[srcreg] & 0xff); |
| 4004 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 4005 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 4006 | State.regs[REG_MCRL] = sum; |
| 4007 | temp >>= 32; |
| 4008 | temp &= 0xffffffff; |
| 4009 | sum = State.regs[REG_MCRH] + temp + c; |
| 4010 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 4011 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4012 | State.regs[REG_MCRH] = sum; |
| 4013 | if (v) |
| 4014 | State.regs[REG_MCVF] = 1; |
| 4015 | } |
| 4016 | |
| 4017 | // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn |
| 4018 | 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach |
| 4019 | "mach" |
| 4020 | *am33 |
| 4021 | *am33_2 |
| 4022 | { |
| 4023 | int srcreg; |
| 4024 | signed64 temp, sum; |
| 4025 | int c, v; |
| 4026 | |
| 4027 | PC = cia; |
| 4028 | srcreg = translate_rreg (SD_, RN2); |
| 4029 | |
| 4030 | temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C)) |
| 4031 | * (signed64)State.regs[srcreg] & 0xffff); |
| 4032 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 4033 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 4034 | State.regs[REG_MCRL] = sum; |
| 4035 | temp >>= 32; |
| 4036 | temp &= 0xffffffff; |
| 4037 | sum = State.regs[REG_MCRH] + temp + c; |
| 4038 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 4039 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4040 | State.regs[REG_MCRH] = sum; |
| 4041 | if (v) |
| 4042 | State.regs[REG_MCVF] = 1; |
| 4043 | } |
| 4044 | |
| 4045 | // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn |
| 4046 | 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu |
| 4047 | "machu" |
| 4048 | *am33 |
| 4049 | *am33_2 |
| 4050 | { |
| 4051 | int srcreg; |
| 4052 | signed64 temp, sum; |
| 4053 | int c, v; |
| 4054 | |
| 4055 | PC = cia; |
| 4056 | srcreg = translate_rreg (SD_, RN2); |
| 4057 | |
| 4058 | temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff) |
| 4059 | * (unsigned64)State.regs[srcreg] & 0xffff); |
| 4060 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 4061 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 4062 | State.regs[REG_MCRL] = sum; |
| 4063 | temp >>= 32; |
| 4064 | temp &= 0xffffffff; |
| 4065 | sum = State.regs[REG_MCRH] + temp + c; |
| 4066 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 4067 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4068 | State.regs[REG_MCRH] = sum; |
| 4069 | if (v) |
| 4070 | State.regs[REG_MCVF] = 1; |
| 4071 | } |
| 4072 | |
| 4073 | // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn |
| 4074 | 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov |
| 4075 | "mov" |
| 4076 | *am33 |
| 4077 | *am33_2 |
| 4078 | { |
| 4079 | int dstreg; |
| 4080 | |
| 4081 | PC = cia; |
| 4082 | dstreg = translate_rreg (SD_, RN2); |
| 4083 | State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 4084 | } |
| 4085 | |
| 4086 | // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24) |
| 4087 | 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov |
| 4088 | "mov" |
| 4089 | *am33 |
| 4090 | *am33_2 |
| 4091 | { |
| 4092 | int srcreg; |
| 4093 | |
| 4094 | PC = cia; |
| 4095 | srcreg = translate_rreg (SD_, RM2); |
| 4096 | store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); |
| 4097 | } |
| 4098 | |
| 4099 | |
| 4100 | // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn |
| 4101 | 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu |
| 4102 | "movbu" |
| 4103 | *am33 |
| 4104 | *am33_2 |
| 4105 | { |
| 4106 | int dstreg; |
| 4107 | |
| 4108 | PC = cia; |
| 4109 | dstreg = translate_rreg (SD_, RN2); |
| 4110 | State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 4111 | } |
| 4112 | |
| 4113 | // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24) |
| 4114 | 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu |
| 4115 | "movbu" |
| 4116 | *am33 |
| 4117 | *am33_2 |
| 4118 | { |
| 4119 | int srcreg; |
| 4120 | |
| 4121 | PC = cia; |
| 4122 | srcreg = translate_rreg (SD_, RM2); |
| 4123 | store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); |
| 4124 | } |
| 4125 | |
| 4126 | |
| 4127 | // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn |
| 4128 | 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu |
| 4129 | "movhu" |
| 4130 | *am33 |
| 4131 | *am33_2 |
| 4132 | { |
| 4133 | int dstreg; |
| 4134 | |
| 4135 | PC = cia; |
| 4136 | dstreg = translate_rreg (SD_, RN2); |
| 4137 | State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C)); |
| 4138 | } |
| 4139 | |
| 4140 | // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24) |
| 4141 | 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu |
| 4142 | "movhu" |
| 4143 | *am33 |
| 4144 | *am33_2 |
| 4145 | { |
| 4146 | int srcreg; |
| 4147 | |
| 4148 | PC = cia; |
| 4149 | srcreg = translate_rreg (SD_, RM2); |
| 4150 | store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); |
| 4151 | } |
| 4152 | |
| 4153 | |
| 4154 | // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn |
| 4155 | 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov |
| 4156 | "mov" |
| 4157 | *am33 |
| 4158 | *am33_2 |
| 4159 | { |
| 4160 | int dstreg; |
| 4161 | |
| 4162 | PC = cia; |
| 4163 | dstreg = translate_rreg (SD_, RN0); |
| 4164 | State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); |
| 4165 | } |
| 4166 | |
| 4167 | // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn |
| 4168 | 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu |
| 4169 | "movu" |
| 4170 | *am33 |
| 4171 | *am33_2 |
| 4172 | { |
| 4173 | int dstreg; |
| 4174 | |
| 4175 | PC = cia; |
| 4176 | dstreg = translate_rreg (SD_, RN0); |
| 4177 | State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); |
| 4178 | } |
| 4179 | |
| 4180 | // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn |
| 4181 | 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add |
| 4182 | "add" |
| 4183 | *am33 |
| 4184 | *am33_2 |
| 4185 | { |
| 4186 | int dstreg; |
| 4187 | |
| 4188 | PC = cia; |
| 4189 | dstreg = translate_rreg (SD_, RN0); |
| 4190 | genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); |
| 4191 | } |
| 4192 | |
| 4193 | // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn |
| 4194 | 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc |
| 4195 | "addc" |
| 4196 | *am33 |
| 4197 | *am33_2 |
| 4198 | { |
| 4199 | int dstreg; |
| 4200 | unsigned32 imm, reg2, sum; |
| 4201 | int z, n, c, v; |
| 4202 | |
| 4203 | PC = cia; |
| 4204 | dstreg = translate_rreg (SD_, RN0); |
| 4205 | |
| 4206 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4207 | reg2 = State.regs[dstreg]; |
| 4208 | sum = imm + reg2 + ((PSW & PSW_C) != 0); |
| 4209 | State.regs[dstreg] = sum; |
| 4210 | |
| 4211 | z = ((PSW & PSW_Z) != 0) && (sum == 0); |
| 4212 | n = (sum & 0x80000000); |
| 4213 | c = (sum < imm) || (sum < reg2); |
| 4214 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) |
| 4215 | && (reg2 & 0x80000000) != (sum & 0x80000000)); |
| 4216 | |
| 4217 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 4218 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 4219 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 4220 | } |
| 4221 | |
| 4222 | // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn |
| 4223 | 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub |
| 4224 | "sub" |
| 4225 | *am33 |
| 4226 | *am33_2 |
| 4227 | { |
| 4228 | int dstreg; |
| 4229 | |
| 4230 | PC = cia; |
| 4231 | dstreg = translate_rreg (SD_, RN0); |
| 4232 | genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); |
| 4233 | } |
| 4234 | |
| 4235 | // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn |
| 4236 | 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc |
| 4237 | "subc" |
| 4238 | *am33 |
| 4239 | *am33_2 |
| 4240 | { |
| 4241 | int dstreg; |
| 4242 | unsigned32 imm, reg2, difference; |
| 4243 | int z, n, c, v; |
| 4244 | |
| 4245 | PC = cia; |
| 4246 | dstreg = translate_rreg (SD_, RN0); |
| 4247 | |
| 4248 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4249 | reg2 = State.regs[dstreg]; |
| 4250 | difference = reg2 - imm - ((PSW & PSW_C) != 0); |
| 4251 | State.regs[dstreg] = difference; |
| 4252 | |
| 4253 | z = ((PSW & PSW_Z) != 0) && (difference == 0); |
| 4254 | n = (difference & 0x80000000); |
| 4255 | c = (imm > reg2); |
| 4256 | v = ((reg2 & 0x80000000) == (imm & 0x80000000) |
| 4257 | && (reg2 & 0x80000000) != (difference & 0x80000000)); |
| 4258 | |
| 4259 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 4260 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| 4261 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
| 4262 | } |
| 4263 | |
| 4264 | // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn |
| 4265 | 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp |
| 4266 | "cmp" |
| 4267 | *am33 |
| 4268 | *am33_2 |
| 4269 | { |
| 4270 | int srcreg; |
| 4271 | |
| 4272 | PC = cia; |
| 4273 | srcreg = translate_rreg (SD_, RN0); |
| 4274 | genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); |
| 4275 | } |
| 4276 | |
| 4277 | // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn |
| 4278 | 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov |
| 4279 | "mov" |
| 4280 | *am33 |
| 4281 | *am33_2 |
| 4282 | { |
| 4283 | int dstreg; |
| 4284 | |
| 4285 | PC = cia; |
| 4286 | dstreg = translate_xreg (SD_, XRN0); |
| 4287 | |
| 4288 | State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); |
| 4289 | } |
| 4290 | |
| 4291 | // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn |
| 4292 | 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and |
| 4293 | "and" |
| 4294 | *am33 |
| 4295 | *am33_2 |
| 4296 | { |
| 4297 | int dstreg; |
| 4298 | int z,n; |
| 4299 | |
| 4300 | PC = cia; |
| 4301 | dstreg = translate_rreg (SD_, RN0); |
| 4302 | |
| 4303 | State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4304 | z = (State.regs[dstreg] == 0); |
| 4305 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4306 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 4307 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 4308 | } |
| 4309 | |
| 4310 | // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn |
| 4311 | 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or |
| 4312 | "or" |
| 4313 | *am33 |
| 4314 | *am33_2 |
| 4315 | { |
| 4316 | int dstreg; |
| 4317 | int z,n; |
| 4318 | |
| 4319 | PC = cia; |
| 4320 | dstreg = translate_rreg (SD_, RN0); |
| 4321 | |
| 4322 | State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4323 | z = (State.regs[dstreg] == 0); |
| 4324 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4325 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 4326 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 4327 | } |
| 4328 | |
| 4329 | // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn |
| 4330 | 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor |
| 4331 | "xor" |
| 4332 | *am33 |
| 4333 | *am33_2 |
| 4334 | { |
| 4335 | int dstreg; |
| 4336 | int z,n; |
| 4337 | |
| 4338 | PC = cia; |
| 4339 | dstreg = translate_rreg (SD_, RN0); |
| 4340 | |
| 4341 | State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4342 | z = (State.regs[dstreg] == 0); |
| 4343 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4344 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 4345 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 4346 | } |
| 4347 | |
| 4348 | // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn |
| 4349 | 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr |
| 4350 | "asr" |
| 4351 | *am33 |
| 4352 | *am33_2 |
| 4353 | { |
| 4354 | int dstreg; |
| 4355 | signed32 temp; |
| 4356 | int c, z, n; |
| 4357 | |
| 4358 | PC = cia; |
| 4359 | dstreg = translate_rreg (SD_, RN0); |
| 4360 | |
| 4361 | temp = State.regs[dstreg]; |
| 4362 | c = temp & 1; |
| 4363 | temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4364 | State.regs[dstreg] = temp; |
| 4365 | z = (State.regs[dstreg] == 0); |
| 4366 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4367 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 4368 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 4369 | } |
| 4370 | |
| 4371 | // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn |
| 4372 | 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr |
| 4373 | "lsr" |
| 4374 | *am33 |
| 4375 | *am33_2 |
| 4376 | { |
| 4377 | int dstreg; |
| 4378 | int z, n, c; |
| 4379 | |
| 4380 | PC = cia; |
| 4381 | dstreg = translate_rreg (SD_, RN0); |
| 4382 | |
| 4383 | c = State.regs[dstreg] & 1; |
| 4384 | State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4385 | z = (State.regs[dstreg] == 0); |
| 4386 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4387 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
| 4388 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); |
| 4389 | } |
| 4390 | |
| 4391 | // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn |
| 4392 | 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl |
| 4393 | "asl" |
| 4394 | *am33 |
| 4395 | *am33_2 |
| 4396 | { |
| 4397 | int dstreg; |
| 4398 | int z, n; |
| 4399 | |
| 4400 | PC = cia; |
| 4401 | dstreg = translate_rreg (SD_, RN0); |
| 4402 | |
| 4403 | State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4404 | z = (State.regs[dstreg] == 0); |
| 4405 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4406 | PSW &= ~(PSW_Z | PSW_N); |
| 4407 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 4408 | } |
| 4409 | |
| 4410 | // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn |
| 4411 | 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul |
| 4412 | "mul" |
| 4413 | *am33 |
| 4414 | *am33_2 |
| 4415 | { |
| 4416 | int dstreg; |
| 4417 | unsigned64 temp; |
| 4418 | int z, n; |
| 4419 | |
| 4420 | PC = cia; |
| 4421 | dstreg = translate_rreg (SD_, RN0); |
| 4422 | |
| 4423 | temp = ((signed64)(signed32)State.regs[dstreg] |
| 4424 | * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); |
| 4425 | State.regs[dstreg] = temp & 0xffffffff; |
| 4426 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 4427 | z = (State.regs[dstreg] == 0); |
| 4428 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4429 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 4430 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 4431 | } |
| 4432 | |
| 4433 | // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn |
| 4434 | 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu |
| 4435 | "mulu" |
| 4436 | *am33 |
| 4437 | *am33_2 |
| 4438 | { |
| 4439 | int dstreg; |
| 4440 | unsigned64 temp; |
| 4441 | int z, n; |
| 4442 | |
| 4443 | PC = cia; |
| 4444 | dstreg = translate_rreg (SD_, RN0); |
| 4445 | |
| 4446 | temp = ((unsigned64)State.regs[dstreg] |
| 4447 | * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); |
| 4448 | State.regs[dstreg] = temp & 0xffffffff; |
| 4449 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
| 4450 | z = (State.regs[dstreg] == 0); |
| 4451 | n = (State.regs[dstreg] & 0x80000000) != 0; |
| 4452 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
| 4453 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
| 4454 | } |
| 4455 | |
| 4456 | // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn |
| 4457 | 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst |
| 4458 | "btst" |
| 4459 | *am33 |
| 4460 | *am33_2 |
| 4461 | { |
| 4462 | int srcreg; |
| 4463 | |
| 4464 | PC = cia; |
| 4465 | srcreg = translate_rreg (SD_, RN0); |
| 4466 | genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); |
| 4467 | } |
| 4468 | |
| 4469 | // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn |
| 4470 | 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov |
| 4471 | "mov" |
| 4472 | *am33 |
| 4473 | *am33_2 |
| 4474 | { |
| 4475 | int srcreg, dstreg; |
| 4476 | |
| 4477 | PC = cia; |
| 4478 | srcreg = translate_rreg (SD_, RM0); |
| 4479 | dstreg = translate_rreg (SD_, RN2); |
| 4480 | State.regs[dstreg] = load_word (State.regs[srcreg] |
| 4481 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4482 | } |
| 4483 | |
| 4484 | // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn) |
| 4485 | 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov |
| 4486 | "mov" |
| 4487 | *am33 |
| 4488 | *am33_2 |
| 4489 | { |
| 4490 | int srcreg, dstreg; |
| 4491 | |
| 4492 | PC = cia; |
| 4493 | srcreg = translate_rreg (SD_, RM2); |
| 4494 | dstreg = translate_rreg (SD_, RN0); |
| 4495 | store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), |
| 4496 | State.regs[srcreg]); |
| 4497 | } |
| 4498 | |
| 4499 | // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn |
| 4500 | 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu |
| 4501 | "movbu" |
| 4502 | *am33 |
| 4503 | *am33_2 |
| 4504 | { |
| 4505 | int srcreg, dstreg; |
| 4506 | |
| 4507 | PC = cia; |
| 4508 | srcreg = translate_rreg (SD_, RM0); |
| 4509 | dstreg = translate_rreg (SD_, RN2); |
| 4510 | State.regs[dstreg] = load_byte (State.regs[srcreg] |
| 4511 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4512 | } |
| 4513 | |
| 4514 | // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn) |
| 4515 | 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu |
| 4516 | "movbu" |
| 4517 | *am33 |
| 4518 | *am33_2 |
| 4519 | { |
| 4520 | int srcreg, dstreg; |
| 4521 | |
| 4522 | PC = cia; |
| 4523 | srcreg = translate_rreg (SD_, RM2); |
| 4524 | dstreg = translate_rreg (SD_, RN0); |
| 4525 | store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), |
| 4526 | State.regs[srcreg]); |
| 4527 | } |
| 4528 | |
| 4529 | // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn |
| 4530 | 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu |
| 4531 | "movhu" |
| 4532 | *am33 |
| 4533 | *am33_2 |
| 4534 | { |
| 4535 | int srcreg, dstreg; |
| 4536 | |
| 4537 | PC = cia; |
| 4538 | srcreg = translate_rreg (SD_, RM0); |
| 4539 | dstreg = translate_rreg (SD_, RN2); |
| 4540 | State.regs[dstreg] = load_half (State.regs[srcreg] |
| 4541 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4542 | } |
| 4543 | |
| 4544 | // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn) |
| 4545 | 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu |
| 4546 | "movhu" |
| 4547 | *am33 |
| 4548 | *am33_2 |
| 4549 | { |
| 4550 | int srcreg, dstreg; |
| 4551 | |
| 4552 | PC = cia; |
| 4553 | srcreg = translate_rreg (SD_, RM2); |
| 4554 | dstreg = translate_rreg (SD_, RN0); |
| 4555 | store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), |
| 4556 | State.regs[srcreg]); |
| 4557 | } |
| 4558 | |
| 4559 | // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn |
| 4560 | 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov |
| 4561 | "mov" |
| 4562 | *am33 |
| 4563 | *am33_2 |
| 4564 | { |
| 4565 | int srcreg, dstreg; |
| 4566 | |
| 4567 | PC = cia; |
| 4568 | srcreg = translate_rreg (SD_, RM0); |
| 4569 | dstreg = translate_rreg (SD_, RN2); |
| 4570 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 4571 | State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4572 | } |
| 4573 | |
| 4574 | // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+) |
| 4575 | 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov |
| 4576 | "mov" |
| 4577 | *am33 |
| 4578 | *am33_2 |
| 4579 | { |
| 4580 | int srcreg, dstreg; |
| 4581 | |
| 4582 | PC = cia; |
| 4583 | srcreg = translate_rreg (SD_, RM2); |
| 4584 | dstreg = translate_rreg (SD_, RN0); |
| 4585 | store_word (State.regs[dstreg], State.regs[srcreg]); |
| 4586 | State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4587 | } |
| 4588 | |
| 4589 | |
| 4590 | // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn |
| 4591 | 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov |
| 4592 | "mov" |
| 4593 | *am33 |
| 4594 | *am33_2 |
| 4595 | { |
| 4596 | int dstreg; |
| 4597 | |
| 4598 | PC = cia; |
| 4599 | dstreg = translate_rreg (SD_, RN2); |
| 4600 | State.regs[dstreg] = load_word (State.regs[REG_SP] |
| 4601 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4602 | } |
| 4603 | |
| 4604 | // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp) |
| 4605 | 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov |
| 4606 | "mov" |
| 4607 | *am33 |
| 4608 | *am33_2 |
| 4609 | { |
| 4610 | int srcreg; |
| 4611 | |
| 4612 | PC = cia; |
| 4613 | srcreg = translate_rreg (SD_, RM2); |
| 4614 | store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), |
| 4615 | State.regs[srcreg]); |
| 4616 | } |
| 4617 | |
| 4618 | // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn |
| 4619 | 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu |
| 4620 | "movbu" |
| 4621 | *am33 |
| 4622 | *am33_2 |
| 4623 | { |
| 4624 | int dstreg; |
| 4625 | |
| 4626 | PC = cia; |
| 4627 | dstreg = translate_rreg (SD_, RN2); |
| 4628 | State.regs[dstreg] = load_byte (State.regs[REG_SP] |
| 4629 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4630 | } |
| 4631 | |
| 4632 | // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp) |
| 4633 | 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu |
| 4634 | "movbu" |
| 4635 | *am33 |
| 4636 | *am33_2 |
| 4637 | { |
| 4638 | int srcreg; |
| 4639 | |
| 4640 | PC = cia; |
| 4641 | srcreg = translate_rreg (SD_, RM2); |
| 4642 | store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), |
| 4643 | State.regs[srcreg]); |
| 4644 | } |
| 4645 | |
| 4646 | // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn |
| 4647 | 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu |
| 4648 | "movhu" |
| 4649 | *am33 |
| 4650 | *am33_2 |
| 4651 | { |
| 4652 | int dstreg; |
| 4653 | |
| 4654 | PC = cia; |
| 4655 | dstreg = translate_rreg (SD_, RN2); |
| 4656 | State.regs[dstreg] = load_half (State.regs[REG_SP] |
| 4657 | + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4658 | } |
| 4659 | |
| 4660 | // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp) |
| 4661 | 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu |
| 4662 | "movhu" |
| 4663 | *am33 |
| 4664 | *am33_2 |
| 4665 | { |
| 4666 | int srcreg; |
| 4667 | |
| 4668 | PC = cia; |
| 4669 | srcreg = translate_rreg (SD_, RM2); |
| 4670 | store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), |
| 4671 | State.regs[srcreg]); |
| 4672 | } |
| 4673 | |
| 4674 | |
| 4675 | // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn |
| 4676 | 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu |
| 4677 | "movhu" |
| 4678 | *am33 |
| 4679 | *am33_2 |
| 4680 | { |
| 4681 | int srcreg, dstreg; |
| 4682 | |
| 4683 | PC = cia; |
| 4684 | srcreg = translate_rreg (SD_, RM0); |
| 4685 | dstreg = translate_rreg (SD_, RN2); |
| 4686 | State.regs[dstreg] = load_half (State.regs[srcreg]); |
| 4687 | State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4688 | } |
| 4689 | |
| 4690 | // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+) |
| 4691 | 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu |
| 4692 | "movhu" |
| 4693 | *am33 |
| 4694 | *am33_2 |
| 4695 | { |
| 4696 | int srcreg, dstreg; |
| 4697 | |
| 4698 | PC = cia; |
| 4699 | srcreg = translate_rreg (SD_, RM2); |
| 4700 | dstreg = translate_rreg (SD_, RN0); |
| 4701 | store_half (State.regs[dstreg], State.regs[srcreg]); |
| 4702 | State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4703 | } |
| 4704 | |
| 4705 | |
| 4706 | // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn |
| 4707 | 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac |
| 4708 | "mac" |
| 4709 | *am33 |
| 4710 | *am33_2 |
| 4711 | { |
| 4712 | int srcreg, imm; |
| 4713 | signed64 temp, sum; |
| 4714 | int c, v; |
| 4715 | |
| 4716 | PC = cia; |
| 4717 | srcreg = translate_rreg (SD_, RN0); |
| 4718 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4719 | |
| 4720 | temp = ((signed64)(signed32)State.regs[srcreg] |
| 4721 | * (signed64)(signed32)imm); |
| 4722 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 4723 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 4724 | State.regs[REG_MCRL] = sum; |
| 4725 | temp >>= 32; |
| 4726 | temp &= 0xffffffff; |
| 4727 | sum = State.regs[REG_MCRH] + temp + c; |
| 4728 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 4729 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4730 | State.regs[REG_MCRH] = sum; |
| 4731 | if (v) |
| 4732 | State.regs[REG_MCVF] = 1; |
| 4733 | } |
| 4734 | |
| 4735 | // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn |
| 4736 | 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu |
| 4737 | "macu" |
| 4738 | *am33 |
| 4739 | *am33_2 |
| 4740 | { |
| 4741 | int srcreg, imm; |
| 4742 | signed64 temp, sum; |
| 4743 | int c, v; |
| 4744 | |
| 4745 | PC = cia; |
| 4746 | srcreg = translate_rreg (SD_, RN0); |
| 4747 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4748 | |
| 4749 | temp = ((unsigned64)State.regs[srcreg] |
| 4750 | * (unsigned64)imm); |
| 4751 | sum = State.regs[REG_MCRL] + (temp & 0xffffffff); |
| 4752 | c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); |
| 4753 | State.regs[REG_MCRL] = sum; |
| 4754 | temp >>= 32; |
| 4755 | temp &= 0xffffffff; |
| 4756 | sum = State.regs[REG_MCRH] + temp + c; |
| 4757 | v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) |
| 4758 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4759 | State.regs[REG_MCRH] = sum; |
| 4760 | if (v) |
| 4761 | State.regs[REG_MCVF] = 1; |
| 4762 | } |
| 4763 | |
| 4764 | // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn |
| 4765 | 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb |
| 4766 | "macb" |
| 4767 | *am33 |
| 4768 | *am33_2 |
| 4769 | { |
| 4770 | int srcreg, imm; |
| 4771 | signed32 temp, sum; |
| 4772 | int v; |
| 4773 | |
| 4774 | PC = cia; |
| 4775 | srcreg = translate_rreg (SD_, RN0); |
| 4776 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4777 | |
| 4778 | temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff) |
| 4779 | * (signed32)(signed8)(imm & 0xff)); |
| 4780 | sum = State.regs[REG_MCRL] + temp; |
| 4781 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 4782 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4783 | State.regs[REG_MCRL] = sum; |
| 4784 | if (v) |
| 4785 | State.regs[REG_MCVF] = 1; |
| 4786 | } |
| 4787 | |
| 4788 | // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn |
| 4789 | 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu |
| 4790 | "macbu" |
| 4791 | *am33 |
| 4792 | *am33_2 |
| 4793 | { |
| 4794 | int srcreg, imm; |
| 4795 | signed32 temp, sum; |
| 4796 | int v; |
| 4797 | |
| 4798 | PC = cia; |
| 4799 | srcreg = translate_rreg (SD_, RN0); |
| 4800 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4801 | |
| 4802 | temp = ((unsigned32)(State.regs[srcreg] & 0xff) |
| 4803 | * (unsigned32)(imm & 0xff)); |
| 4804 | sum = State.regs[REG_MCRL] + temp; |
| 4805 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 4806 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4807 | State.regs[REG_MCRL] = sum; |
| 4808 | if (v) |
| 4809 | State.regs[REG_MCVF] = 1; |
| 4810 | } |
| 4811 | |
| 4812 | // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn |
| 4813 | 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach |
| 4814 | "mach" |
| 4815 | *am33 |
| 4816 | *am33_2 |
| 4817 | { |
| 4818 | int srcreg, imm; |
| 4819 | signed32 temp, sum; |
| 4820 | int v; |
| 4821 | |
| 4822 | PC = cia; |
| 4823 | srcreg = translate_rreg (SD_, RN0); |
| 4824 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4825 | |
| 4826 | temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) |
| 4827 | * (signed32)(signed16)(imm & 0xffff)); |
| 4828 | sum = State.regs[REG_MCRL] + temp; |
| 4829 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 4830 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4831 | State.regs[REG_MCRL] = sum; |
| 4832 | if (v) |
| 4833 | State.regs[REG_MCVF] = 1; |
| 4834 | } |
| 4835 | |
| 4836 | // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn |
| 4837 | 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu |
| 4838 | "machu" |
| 4839 | *am33 |
| 4840 | *am33_2 |
| 4841 | { |
| 4842 | int srcreg, imm; |
| 4843 | signed32 temp, sum; |
| 4844 | int v; |
| 4845 | |
| 4846 | PC = cia; |
| 4847 | srcreg = translate_rreg (SD_, RN0); |
| 4848 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4849 | |
| 4850 | temp = ((unsigned32)(State.regs[srcreg] & 0xffff) |
| 4851 | * (unsigned32)(imm & 0xffff)); |
| 4852 | sum = State.regs[REG_MCRL] + temp; |
| 4853 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 4854 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4855 | State.regs[REG_MCRL] = sum; |
| 4856 | if (v) |
| 4857 | State.regs[REG_MCVF] = 1; |
| 4858 | } |
| 4859 | |
| 4860 | // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn |
| 4861 | 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach |
| 4862 | "dmach" |
| 4863 | *am33 |
| 4864 | *am33_2 |
| 4865 | { |
| 4866 | int srcreg, imm; |
| 4867 | signed32 temp, temp2, sum; |
| 4868 | int v; |
| 4869 | |
| 4870 | PC = cia; |
| 4871 | srcreg = translate_rreg (SD_, RN0); |
| 4872 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4873 | |
| 4874 | temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) |
| 4875 | * (signed32)(signed16)(imm & 0xffff)); |
| 4876 | temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff) |
| 4877 | * (signed32)(signed16)((imm >> 16) & 0xffff)); |
| 4878 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 4879 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 4880 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4881 | State.regs[REG_MCRL] = sum; |
| 4882 | if (v) |
| 4883 | State.regs[REG_MCVF] = 1; |
| 4884 | } |
| 4885 | |
| 4886 | // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn |
| 4887 | 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu |
| 4888 | "dmachu" |
| 4889 | *am33 |
| 4890 | *am33_2 |
| 4891 | { |
| 4892 | int srcreg, imm; |
| 4893 | signed32 temp, temp2, sum; |
| 4894 | int v; |
| 4895 | |
| 4896 | PC = cia; |
| 4897 | srcreg = translate_rreg (SD_, RN0); |
| 4898 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4899 | |
| 4900 | temp = ((unsigned32)(State.regs[srcreg] & 0xffff) |
| 4901 | * (unsigned32)(imm & 0xffff)); |
| 4902 | temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff) |
| 4903 | * (unsigned32)((imm >> 16) & 0xffff)); |
| 4904 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 4905 | v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) |
| 4906 | && (temp & 0x80000000) != (sum & 0x80000000)); |
| 4907 | State.regs[REG_MCRL] = sum; |
| 4908 | if (v) |
| 4909 | State.regs[REG_MCVF] = 1; |
| 4910 | } |
| 4911 | |
| 4912 | // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn |
| 4913 | 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh |
| 4914 | "dmulh" |
| 4915 | *am33 |
| 4916 | *am33_2 |
| 4917 | { |
| 4918 | int imm, dstreg; |
| 4919 | signed32 temp; |
| 4920 | |
| 4921 | PC = cia; |
| 4922 | dstreg = translate_rreg (SD_, RN0); |
| 4923 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4924 | |
| 4925 | temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) |
| 4926 | * (signed32)(signed16)(imm & 0xffff)); |
| 4927 | State.regs[REG_MDRQ] = temp; |
| 4928 | temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) |
| 4929 | * (signed32)(signed16)((imm>>16) & 0xffff)); |
| 4930 | State.regs[dstreg] = temp; |
| 4931 | } |
| 4932 | |
| 4933 | // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn |
| 4934 | 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu |
| 4935 | "dmulhu" |
| 4936 | *am33 |
| 4937 | *am33_2 |
| 4938 | { |
| 4939 | int imm, dstreg; |
| 4940 | signed32 temp; |
| 4941 | |
| 4942 | PC = cia; |
| 4943 | dstreg = translate_rreg (SD_, RN0); |
| 4944 | imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); |
| 4945 | |
| 4946 | temp = ((unsigned32)(State.regs[dstreg] & 0xffff) |
| 4947 | * (unsigned32)(imm & 0xffff)); |
| 4948 | State.regs[REG_MDRQ] = temp; |
| 4949 | temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) |
| 4950 | * (unsigned32)((imm >>16) & 0xffff)); |
| 4951 | State.regs[dstreg] = temp; |
| 4952 | } |
| 4953 | |
| 4954 | // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn |
| 4955 | 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov |
| 4956 | "mov" |
| 4957 | *am33 |
| 4958 | *am33_2 |
| 4959 | { |
| 4960 | int dstreg; |
| 4961 | |
| 4962 | PC = cia; |
| 4963 | dstreg = translate_rreg (SD_, RN2); |
| 4964 | State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4965 | } |
| 4966 | |
| 4967 | // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32) |
| 4968 | 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov |
| 4969 | "mov" |
| 4970 | *am33 |
| 4971 | *am33_2 |
| 4972 | { |
| 4973 | int srcreg; |
| 4974 | |
| 4975 | PC = cia; |
| 4976 | srcreg = translate_rreg (SD_, RM2); |
| 4977 | store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); |
| 4978 | } |
| 4979 | |
| 4980 | // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn |
| 4981 | 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu |
| 4982 | "movbu" |
| 4983 | *am33 |
| 4984 | *am33_2 |
| 4985 | { |
| 4986 | int dstreg; |
| 4987 | |
| 4988 | PC = cia; |
| 4989 | dstreg = translate_rreg (SD_, RN2); |
| 4990 | State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 4991 | } |
| 4992 | |
| 4993 | // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32) |
| 4994 | 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu |
| 4995 | "movbu" |
| 4996 | *am33 |
| 4997 | *am33_2 |
| 4998 | { |
| 4999 | int srcreg; |
| 5000 | |
| 5001 | PC = cia; |
| 5002 | srcreg = translate_rreg (SD_, RM2); |
| 5003 | store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); |
| 5004 | } |
| 5005 | |
| 5006 | // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn |
| 5007 | 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu |
| 5008 | "movhu" |
| 5009 | *am33 |
| 5010 | *am33_2 |
| 5011 | { |
| 5012 | int dstreg; |
| 5013 | |
| 5014 | PC = cia; |
| 5015 | dstreg = translate_rreg (SD_, RN2); |
| 5016 | State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); |
| 5017 | } |
| 5018 | |
| 5019 | // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32) |
| 5020 | 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu |
| 5021 | "movhu" |
| 5022 | *am33 |
| 5023 | *am33_2 |
| 5024 | { |
| 5025 | int srcreg; |
| 5026 | |
| 5027 | PC = cia; |
| 5028 | srcreg = translate_rreg (SD_, RM2); |
| 5029 | store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); |
| 5030 | } |
| 5031 | |
| 5032 | // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2 |
| 5033 | 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add |
| 5034 | "add_add" |
| 5035 | *am33 |
| 5036 | *am33_2 |
| 5037 | { |
| 5038 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5039 | int result1; |
| 5040 | |
| 5041 | PC = cia; |
| 5042 | srcreg1 = translate_rreg (SD_, RM1); |
| 5043 | srcreg2 = translate_rreg (SD_, RM2); |
| 5044 | dstreg1 = translate_rreg (SD_, RN1); |
| 5045 | dstreg2 = translate_rreg (SD_, RN2); |
| 5046 | |
| 5047 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5048 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 5049 | State.regs[dstreg1] = result1; |
| 5050 | } |
| 5051 | |
| 5052 | // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2 |
| 5053 | 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add |
| 5054 | "add_add" |
| 5055 | *am33 |
| 5056 | *am33_2 |
| 5057 | { |
| 5058 | int srcreg1, dstreg1, dstreg2; |
| 5059 | int result1; |
| 5060 | |
| 5061 | PC = cia; |
| 5062 | srcreg1 = translate_rreg (SD_, RM1); |
| 5063 | dstreg1 = translate_rreg (SD_, RN1); |
| 5064 | dstreg2 = translate_rreg (SD_, RN2); |
| 5065 | |
| 5066 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5067 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 5068 | State.regs[dstreg1] = result1; |
| 5069 | } |
| 5070 | |
| 5071 | // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2 |
| 5072 | 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub |
| 5073 | "add_sub" |
| 5074 | *am33 |
| 5075 | *am33_2 |
| 5076 | { |
| 5077 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5078 | int result1; |
| 5079 | |
| 5080 | PC = cia; |
| 5081 | srcreg1 = translate_rreg (SD_, RM1); |
| 5082 | srcreg2 = translate_rreg (SD_, RM2); |
| 5083 | dstreg1 = translate_rreg (SD_, RN1); |
| 5084 | dstreg2 = translate_rreg (SD_, RN2); |
| 5085 | |
| 5086 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5087 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 5088 | State.regs[dstreg1] = result1; |
| 5089 | } |
| 5090 | |
| 5091 | // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2 |
| 5092 | 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub |
| 5093 | "add_sub" |
| 5094 | *am33 |
| 5095 | *am33_2 |
| 5096 | { |
| 5097 | int srcreg1, dstreg1, dstreg2; |
| 5098 | int result1; |
| 5099 | |
| 5100 | PC = cia; |
| 5101 | srcreg1 = translate_rreg (SD_, RM1); |
| 5102 | dstreg1 = translate_rreg (SD_, RN1); |
| 5103 | dstreg2 = translate_rreg (SD_, RN2); |
| 5104 | |
| 5105 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5106 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 5107 | State.regs[dstreg1] = result1; |
| 5108 | } |
| 5109 | |
| 5110 | // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2 |
| 5111 | 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp |
| 5112 | "add_cmp" |
| 5113 | *am33 |
| 5114 | *am33_2 |
| 5115 | { |
| 5116 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5117 | |
| 5118 | PC = cia; |
| 5119 | srcreg1 = translate_rreg (SD_, RM1); |
| 5120 | srcreg2 = translate_rreg (SD_, RM2); |
| 5121 | dstreg1 = translate_rreg (SD_, RN1); |
| 5122 | dstreg2 = translate_rreg (SD_, RN2); |
| 5123 | |
| 5124 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 5125 | State.regs[dstreg1] += State.regs[srcreg1]; |
| 5126 | } |
| 5127 | |
| 5128 | // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2 |
| 5129 | 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp |
| 5130 | "add_cmp" |
| 5131 | *am33 |
| 5132 | *am33_2 |
| 5133 | { |
| 5134 | int srcreg1, dstreg1, dstreg2; |
| 5135 | |
| 5136 | PC = cia; |
| 5137 | srcreg1 = translate_rreg (SD_, RM1); |
| 5138 | dstreg1 = translate_rreg (SD_, RN1); |
| 5139 | dstreg2 = translate_rreg (SD_, RN2); |
| 5140 | |
| 5141 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 5142 | State.regs[dstreg1] += State.regs[srcreg1]; |
| 5143 | } |
| 5144 | |
| 5145 | // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2 |
| 5146 | 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov |
| 5147 | "add_mov" |
| 5148 | *am33 |
| 5149 | *am33_2 |
| 5150 | { |
| 5151 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5152 | int result1; |
| 5153 | |
| 5154 | PC = cia; |
| 5155 | srcreg1 = translate_rreg (SD_, RM1); |
| 5156 | srcreg2 = translate_rreg (SD_, RM2); |
| 5157 | dstreg1 = translate_rreg (SD_, RN1); |
| 5158 | dstreg2 = translate_rreg (SD_, RN2); |
| 5159 | |
| 5160 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5161 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 5162 | State.regs[dstreg1] = result1; |
| 5163 | } |
| 5164 | |
| 5165 | // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2 |
| 5166 | 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov |
| 5167 | "add_mov" |
| 5168 | *am33 |
| 5169 | *am33_2 |
| 5170 | { |
| 5171 | int srcreg1, dstreg1, dstreg2; |
| 5172 | int result1; |
| 5173 | |
| 5174 | PC = cia; |
| 5175 | srcreg1 = translate_rreg (SD_, RM1); |
| 5176 | dstreg1 = translate_rreg (SD_, RN1); |
| 5177 | dstreg2 = translate_rreg (SD_, RN2); |
| 5178 | |
| 5179 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5180 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 5181 | State.regs[dstreg1] = result1; |
| 5182 | } |
| 5183 | |
| 5184 | // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2 |
| 5185 | 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr |
| 5186 | "add_asr" |
| 5187 | *am33 |
| 5188 | *am33_2 |
| 5189 | { |
| 5190 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5191 | int result1; |
| 5192 | signed int temp; |
| 5193 | |
| 5194 | PC = cia; |
| 5195 | srcreg1 = translate_rreg (SD_, RM1); |
| 5196 | srcreg2 = translate_rreg (SD_, RM2); |
| 5197 | dstreg1 = translate_rreg (SD_, RN1); |
| 5198 | dstreg2 = translate_rreg (SD_, RN2); |
| 5199 | |
| 5200 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5201 | temp = State.regs[dstreg2]; |
| 5202 | temp >>= State.regs[srcreg2]; |
| 5203 | State.regs[dstreg2] = temp; |
| 5204 | State.regs[dstreg1] = result1; |
| 5205 | } |
| 5206 | |
| 5207 | // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2 |
| 5208 | 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr |
| 5209 | "add_asr" |
| 5210 | *am33 |
| 5211 | *am33_2 |
| 5212 | { |
| 5213 | int srcreg1, dstreg1, dstreg2; |
| 5214 | int result1; |
| 5215 | signed int temp; |
| 5216 | |
| 5217 | PC = cia; |
| 5218 | srcreg1 = translate_rreg (SD_, RM1); |
| 5219 | dstreg1 = translate_rreg (SD_, RN1); |
| 5220 | dstreg2 = translate_rreg (SD_, RN2); |
| 5221 | |
| 5222 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5223 | temp = State.regs[dstreg2]; |
| 5224 | temp >>= IMM4; |
| 5225 | State.regs[dstreg2] = temp; |
| 5226 | State.regs[dstreg1] = result1; |
| 5227 | } |
| 5228 | |
| 5229 | // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2 |
| 5230 | 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr |
| 5231 | "add_lsr" |
| 5232 | *am33 |
| 5233 | *am33_2 |
| 5234 | { |
| 5235 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5236 | int result1; |
| 5237 | |
| 5238 | PC = cia; |
| 5239 | srcreg1 = translate_rreg (SD_, RM1); |
| 5240 | srcreg2 = translate_rreg (SD_, RM2); |
| 5241 | dstreg1 = translate_rreg (SD_, RN1); |
| 5242 | dstreg2 = translate_rreg (SD_, RN2); |
| 5243 | |
| 5244 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5245 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 5246 | State.regs[dstreg1] = result1; |
| 5247 | } |
| 5248 | |
| 5249 | // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2 |
| 5250 | 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr |
| 5251 | "add_lsr" |
| 5252 | *am33 |
| 5253 | *am33_2 |
| 5254 | { |
| 5255 | int srcreg1, dstreg1, dstreg2; |
| 5256 | int result1; |
| 5257 | |
| 5258 | PC = cia; |
| 5259 | srcreg1 = translate_rreg (SD_, RM1); |
| 5260 | dstreg1 = translate_rreg (SD_, RN1); |
| 5261 | dstreg2 = translate_rreg (SD_, RN2); |
| 5262 | |
| 5263 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5264 | State.regs[dstreg2] >>= IMM4; |
| 5265 | State.regs[dstreg1] = result1; |
| 5266 | } |
| 5267 | |
| 5268 | |
| 5269 | // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2 |
| 5270 | 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl |
| 5271 | "add_asl" |
| 5272 | *am33 |
| 5273 | *am33_2 |
| 5274 | { |
| 5275 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5276 | int result1; |
| 5277 | |
| 5278 | PC = cia; |
| 5279 | srcreg1 = translate_rreg (SD_, RM1); |
| 5280 | srcreg2 = translate_rreg (SD_, RM2); |
| 5281 | dstreg1 = translate_rreg (SD_, RN1); |
| 5282 | dstreg2 = translate_rreg (SD_, RN2); |
| 5283 | |
| 5284 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5285 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 5286 | State.regs[dstreg1] = result1; |
| 5287 | } |
| 5288 | |
| 5289 | // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2 |
| 5290 | 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl |
| 5291 | "add_asl" |
| 5292 | *am33 |
| 5293 | *am33_2 |
| 5294 | { |
| 5295 | int srcreg1, dstreg1, dstreg2; |
| 5296 | int result1; |
| 5297 | |
| 5298 | PC = cia; |
| 5299 | srcreg1 = translate_rreg (SD_, RM1); |
| 5300 | dstreg1 = translate_rreg (SD_, RN1); |
| 5301 | dstreg2 = translate_rreg (SD_, RN2); |
| 5302 | |
| 5303 | result1 = State.regs[dstreg1] + State.regs[srcreg1]; |
| 5304 | State.regs[dstreg2] <<= IMM4; |
| 5305 | State.regs[dstreg1] = result1; |
| 5306 | } |
| 5307 | |
| 5308 | // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2 |
| 5309 | 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add |
| 5310 | "cmp_add" |
| 5311 | *am33 |
| 5312 | *am33_2 |
| 5313 | { |
| 5314 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5315 | |
| 5316 | PC = cia; |
| 5317 | srcreg1 = translate_rreg (SD_, RM1); |
| 5318 | srcreg2 = translate_rreg (SD_, RM2); |
| 5319 | dstreg1 = translate_rreg (SD_, RN1); |
| 5320 | dstreg2 = translate_rreg (SD_, RN2); |
| 5321 | |
| 5322 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5323 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 5324 | } |
| 5325 | |
| 5326 | // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2 |
| 5327 | 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add |
| 5328 | "cmp_add" |
| 5329 | *am33 |
| 5330 | *am33_2 |
| 5331 | { |
| 5332 | int srcreg1, dstreg1, dstreg2; |
| 5333 | |
| 5334 | PC = cia; |
| 5335 | srcreg1 = translate_rreg (SD_, RM1); |
| 5336 | dstreg1 = translate_rreg (SD_, RN1); |
| 5337 | dstreg2 = translate_rreg (SD_, RN2); |
| 5338 | |
| 5339 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5340 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 5341 | } |
| 5342 | |
| 5343 | // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2 |
| 5344 | 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub |
| 5345 | "cmp_sub" |
| 5346 | *am33 |
| 5347 | *am33_2 |
| 5348 | { |
| 5349 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5350 | |
| 5351 | PC = cia; |
| 5352 | srcreg1 = translate_rreg (SD_, RM1); |
| 5353 | srcreg2 = translate_rreg (SD_, RM2); |
| 5354 | dstreg1 = translate_rreg (SD_, RN1); |
| 5355 | dstreg2 = translate_rreg (SD_, RN2); |
| 5356 | |
| 5357 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5358 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 5359 | } |
| 5360 | |
| 5361 | // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2 |
| 5362 | 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub |
| 5363 | "cmp_sub" |
| 5364 | *am33 |
| 5365 | *am33_2 |
| 5366 | { |
| 5367 | int srcreg1, dstreg1, dstreg2; |
| 5368 | |
| 5369 | PC = cia; |
| 5370 | srcreg1 = translate_rreg (SD_, RM1); |
| 5371 | dstreg1 = translate_rreg (SD_, RN1); |
| 5372 | dstreg2 = translate_rreg (SD_, RN2); |
| 5373 | |
| 5374 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5375 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 5376 | } |
| 5377 | |
| 5378 | // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2 |
| 5379 | 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov |
| 5380 | "cmp_mov" |
| 5381 | *am33 |
| 5382 | *am33_2 |
| 5383 | { |
| 5384 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5385 | |
| 5386 | PC = cia; |
| 5387 | srcreg1 = translate_rreg (SD_, RM1); |
| 5388 | srcreg2 = translate_rreg (SD_, RM2); |
| 5389 | dstreg1 = translate_rreg (SD_, RN1); |
| 5390 | dstreg2 = translate_rreg (SD_, RN2); |
| 5391 | |
| 5392 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5393 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 5394 | } |
| 5395 | |
| 5396 | // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2 |
| 5397 | 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov |
| 5398 | "cmp_mov" |
| 5399 | *am33 |
| 5400 | *am33_2 |
| 5401 | { |
| 5402 | int srcreg1, dstreg1, dstreg2; |
| 5403 | |
| 5404 | PC = cia; |
| 5405 | srcreg1 = translate_rreg (SD_, RM1); |
| 5406 | dstreg1 = translate_rreg (SD_, RN1); |
| 5407 | dstreg2 = translate_rreg (SD_, RN2); |
| 5408 | |
| 5409 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5410 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 5411 | } |
| 5412 | |
| 5413 | // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2 |
| 5414 | 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr |
| 5415 | "cmp_asr" |
| 5416 | *am33 |
| 5417 | *am33_2 |
| 5418 | { |
| 5419 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5420 | signed int temp; |
| 5421 | |
| 5422 | PC = cia; |
| 5423 | srcreg1 = translate_rreg (SD_, RM1); |
| 5424 | srcreg2 = translate_rreg (SD_, RM2); |
| 5425 | dstreg1 = translate_rreg (SD_, RN1); |
| 5426 | dstreg2 = translate_rreg (SD_, RN2); |
| 5427 | |
| 5428 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5429 | temp = State.regs[dstreg2]; |
| 5430 | temp >>= State.regs[srcreg2]; |
| 5431 | State.regs[dstreg2] = temp; |
| 5432 | } |
| 5433 | |
| 5434 | // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2 |
| 5435 | 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr |
| 5436 | "cmp_asr" |
| 5437 | *am33 |
| 5438 | *am33_2 |
| 5439 | { |
| 5440 | int srcreg1, dstreg1, dstreg2; |
| 5441 | signed int temp; |
| 5442 | |
| 5443 | PC = cia; |
| 5444 | srcreg1 = translate_rreg (SD_, RM1); |
| 5445 | dstreg1 = translate_rreg (SD_, RN1); |
| 5446 | dstreg2 = translate_rreg (SD_, RN2); |
| 5447 | |
| 5448 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5449 | temp = State.regs[dstreg2]; |
| 5450 | temp >>= IMM4; |
| 5451 | State.regs[dstreg2] = temp; |
| 5452 | } |
| 5453 | |
| 5454 | // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2 |
| 5455 | 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr |
| 5456 | "cmp_lsr" |
| 5457 | *am33 |
| 5458 | *am33_2 |
| 5459 | { |
| 5460 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5461 | |
| 5462 | PC = cia; |
| 5463 | srcreg1 = translate_rreg (SD_, RM1); |
| 5464 | srcreg2 = translate_rreg (SD_, RM2); |
| 5465 | dstreg1 = translate_rreg (SD_, RN1); |
| 5466 | dstreg2 = translate_rreg (SD_, RN2); |
| 5467 | |
| 5468 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5469 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 5470 | } |
| 5471 | |
| 5472 | // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2 |
| 5473 | 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr |
| 5474 | "cmp_lsr" |
| 5475 | *am33 |
| 5476 | *am33_2 |
| 5477 | { |
| 5478 | int srcreg1, dstreg1, dstreg2; |
| 5479 | |
| 5480 | PC = cia; |
| 5481 | srcreg1 = translate_rreg (SD_, RM1); |
| 5482 | dstreg1 = translate_rreg (SD_, RN1); |
| 5483 | dstreg2 = translate_rreg (SD_, RN2); |
| 5484 | |
| 5485 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5486 | State.regs[dstreg2] >>= IMM4; |
| 5487 | } |
| 5488 | |
| 5489 | |
| 5490 | // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2 |
| 5491 | 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl |
| 5492 | "cmp_asl" |
| 5493 | *am33 |
| 5494 | *am33_2 |
| 5495 | { |
| 5496 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5497 | |
| 5498 | PC = cia; |
| 5499 | srcreg1 = translate_rreg (SD_, RM1); |
| 5500 | srcreg2 = translate_rreg (SD_, RM2); |
| 5501 | dstreg1 = translate_rreg (SD_, RN1); |
| 5502 | dstreg2 = translate_rreg (SD_, RN2); |
| 5503 | |
| 5504 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5505 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 5506 | } |
| 5507 | |
| 5508 | // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2 |
| 5509 | 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl |
| 5510 | "cmp_asl" |
| 5511 | *am33 |
| 5512 | *am33_2 |
| 5513 | { |
| 5514 | int srcreg1, dstreg1, dstreg2; |
| 5515 | |
| 5516 | PC = cia; |
| 5517 | srcreg1 = translate_rreg (SD_, RM1); |
| 5518 | dstreg1 = translate_rreg (SD_, RN1); |
| 5519 | dstreg2 = translate_rreg (SD_, RN2); |
| 5520 | |
| 5521 | genericCmp (State.regs[srcreg1], State.regs[dstreg1]); |
| 5522 | State.regs[dstreg2] <<= IMM4; |
| 5523 | } |
| 5524 | |
| 5525 | // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2 |
| 5526 | 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add |
| 5527 | "sub_add" |
| 5528 | *am33 |
| 5529 | *am33_2 |
| 5530 | { |
| 5531 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5532 | int result1; |
| 5533 | |
| 5534 | PC = cia; |
| 5535 | srcreg1 = translate_rreg (SD_, RM1); |
| 5536 | srcreg2 = translate_rreg (SD_, RM2); |
| 5537 | dstreg1 = translate_rreg (SD_, RN1); |
| 5538 | dstreg2 = translate_rreg (SD_, RN2); |
| 5539 | |
| 5540 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5541 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 5542 | State.regs[dstreg1] = result1; |
| 5543 | } |
| 5544 | |
| 5545 | // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2 |
| 5546 | 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add |
| 5547 | "sub_add" |
| 5548 | *am33 |
| 5549 | *am33_2 |
| 5550 | { |
| 5551 | int srcreg1, dstreg1, dstreg2; |
| 5552 | int result1; |
| 5553 | |
| 5554 | PC = cia; |
| 5555 | srcreg1 = translate_rreg (SD_, RM1); |
| 5556 | dstreg1 = translate_rreg (SD_, RN1); |
| 5557 | dstreg2 = translate_rreg (SD_, RN2); |
| 5558 | |
| 5559 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5560 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 5561 | State.regs[dstreg1] = result1; |
| 5562 | } |
| 5563 | |
| 5564 | // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2 |
| 5565 | 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub |
| 5566 | "sub_sub" |
| 5567 | *am33 |
| 5568 | *am33_2 |
| 5569 | { |
| 5570 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5571 | int result1; |
| 5572 | |
| 5573 | PC = cia; |
| 5574 | srcreg1 = translate_rreg (SD_, RM1); |
| 5575 | srcreg2 = translate_rreg (SD_, RM2); |
| 5576 | dstreg1 = translate_rreg (SD_, RN1); |
| 5577 | dstreg2 = translate_rreg (SD_, RN2); |
| 5578 | |
| 5579 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5580 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 5581 | State.regs[dstreg1] = result1; |
| 5582 | } |
| 5583 | |
| 5584 | // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2 |
| 5585 | 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub |
| 5586 | "sub_sub" |
| 5587 | *am33 |
| 5588 | *am33_2 |
| 5589 | { |
| 5590 | int srcreg1, dstreg1, dstreg2; |
| 5591 | int result1; |
| 5592 | |
| 5593 | PC = cia; |
| 5594 | srcreg1 = translate_rreg (SD_, RM1); |
| 5595 | dstreg1 = translate_rreg (SD_, RN1); |
| 5596 | dstreg2 = translate_rreg (SD_, RN2); |
| 5597 | |
| 5598 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5599 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 5600 | State.regs[dstreg1] = result1; |
| 5601 | } |
| 5602 | |
| 5603 | // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2 |
| 5604 | 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp |
| 5605 | "sub_cmp" |
| 5606 | *am33 |
| 5607 | *am33_2 |
| 5608 | { |
| 5609 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5610 | |
| 5611 | PC = cia; |
| 5612 | srcreg1 = translate_rreg (SD_, RM1); |
| 5613 | srcreg2 = translate_rreg (SD_, RM2); |
| 5614 | dstreg1 = translate_rreg (SD_, RN1); |
| 5615 | dstreg2 = translate_rreg (SD_, RN2); |
| 5616 | |
| 5617 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 5618 | State.regs[dstreg1] -= State.regs[srcreg1]; |
| 5619 | } |
| 5620 | |
| 5621 | // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2 |
| 5622 | 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp |
| 5623 | "sub_cmp" |
| 5624 | *am33 |
| 5625 | *am33_2 |
| 5626 | { |
| 5627 | int srcreg1, dstreg1, dstreg2; |
| 5628 | |
| 5629 | PC = cia; |
| 5630 | srcreg1 = translate_rreg (SD_, RM1); |
| 5631 | dstreg1 = translate_rreg (SD_, RN1); |
| 5632 | dstreg2 = translate_rreg (SD_, RN2); |
| 5633 | |
| 5634 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 5635 | State.regs[dstreg1] -= State.regs[srcreg1]; |
| 5636 | } |
| 5637 | |
| 5638 | // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2 |
| 5639 | 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov |
| 5640 | "sub_mov" |
| 5641 | *am33 |
| 5642 | *am33_2 |
| 5643 | { |
| 5644 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5645 | int result1; |
| 5646 | |
| 5647 | PC = cia; |
| 5648 | srcreg1 = translate_rreg (SD_, RM1); |
| 5649 | srcreg2 = translate_rreg (SD_, RM2); |
| 5650 | dstreg1 = translate_rreg (SD_, RN1); |
| 5651 | dstreg2 = translate_rreg (SD_, RN2); |
| 5652 | |
| 5653 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5654 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 5655 | State.regs[dstreg1] = result1; |
| 5656 | } |
| 5657 | |
| 5658 | // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2 |
| 5659 | 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov |
| 5660 | "sub_mov" |
| 5661 | *am33 |
| 5662 | *am33_2 |
| 5663 | { |
| 5664 | int srcreg1, dstreg1, dstreg2; |
| 5665 | int result1; |
| 5666 | |
| 5667 | PC = cia; |
| 5668 | srcreg1 = translate_rreg (SD_, RM1); |
| 5669 | dstreg1 = translate_rreg (SD_, RN1); |
| 5670 | dstreg2 = translate_rreg (SD_, RN2); |
| 5671 | |
| 5672 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5673 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 5674 | State.regs[dstreg1] = result1; |
| 5675 | } |
| 5676 | |
| 5677 | // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2 |
| 5678 | 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr |
| 5679 | "sub_asr" |
| 5680 | *am33 |
| 5681 | *am33_2 |
| 5682 | { |
| 5683 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5684 | int result1; |
| 5685 | signed int temp; |
| 5686 | |
| 5687 | PC = cia; |
| 5688 | srcreg1 = translate_rreg (SD_, RM1); |
| 5689 | srcreg2 = translate_rreg (SD_, RM2); |
| 5690 | dstreg1 = translate_rreg (SD_, RN1); |
| 5691 | dstreg2 = translate_rreg (SD_, RN2); |
| 5692 | |
| 5693 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5694 | temp = State.regs[dstreg2]; |
| 5695 | temp >>= State.regs[srcreg2]; |
| 5696 | State.regs[dstreg2] = temp; |
| 5697 | State.regs[dstreg1] = result1; |
| 5698 | } |
| 5699 | |
| 5700 | // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2 |
| 5701 | 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr |
| 5702 | "sub_asr" |
| 5703 | *am33 |
| 5704 | *am33_2 |
| 5705 | { |
| 5706 | int srcreg1, dstreg1, dstreg2; |
| 5707 | int result1; |
| 5708 | signed int temp; |
| 5709 | |
| 5710 | PC = cia; |
| 5711 | srcreg1 = translate_rreg (SD_, RM1); |
| 5712 | dstreg1 = translate_rreg (SD_, RN1); |
| 5713 | dstreg2 = translate_rreg (SD_, RN2); |
| 5714 | |
| 5715 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5716 | temp = State.regs[dstreg2]; |
| 5717 | temp >>= IMM4; |
| 5718 | State.regs[dstreg2] = temp; |
| 5719 | State.regs[dstreg1] = result1; |
| 5720 | } |
| 5721 | |
| 5722 | // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2 |
| 5723 | 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr |
| 5724 | "sub_lsr" |
| 5725 | *am33 |
| 5726 | *am33_2 |
| 5727 | { |
| 5728 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5729 | int result1; |
| 5730 | |
| 5731 | PC = cia; |
| 5732 | srcreg1 = translate_rreg (SD_, RM1); |
| 5733 | srcreg2 = translate_rreg (SD_, RM2); |
| 5734 | dstreg1 = translate_rreg (SD_, RN1); |
| 5735 | dstreg2 = translate_rreg (SD_, RN2); |
| 5736 | |
| 5737 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5738 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 5739 | State.regs[dstreg1] = result1; |
| 5740 | } |
| 5741 | |
| 5742 | // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2 |
| 5743 | 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr |
| 5744 | "sub_lsr" |
| 5745 | *am33 |
| 5746 | *am33_2 |
| 5747 | { |
| 5748 | int srcreg1, dstreg1, dstreg2; |
| 5749 | int result1; |
| 5750 | |
| 5751 | PC = cia; |
| 5752 | srcreg1 = translate_rreg (SD_, RM1); |
| 5753 | dstreg1 = translate_rreg (SD_, RN1); |
| 5754 | dstreg2 = translate_rreg (SD_, RN2); |
| 5755 | |
| 5756 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5757 | State.regs[dstreg2] >>= IMM4; |
| 5758 | State.regs[dstreg1] = result1; |
| 5759 | } |
| 5760 | |
| 5761 | |
| 5762 | // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2 |
| 5763 | 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl |
| 5764 | "sub_asl" |
| 5765 | *am33 |
| 5766 | *am33_2 |
| 5767 | { |
| 5768 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5769 | int result1; |
| 5770 | |
| 5771 | PC = cia; |
| 5772 | srcreg1 = translate_rreg (SD_, RM1); |
| 5773 | srcreg2 = translate_rreg (SD_, RM2); |
| 5774 | dstreg1 = translate_rreg (SD_, RN1); |
| 5775 | dstreg2 = translate_rreg (SD_, RN2); |
| 5776 | |
| 5777 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5778 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 5779 | State.regs[dstreg1] = result1; |
| 5780 | } |
| 5781 | |
| 5782 | // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2 |
| 5783 | 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl |
| 5784 | "sub_asl" |
| 5785 | *am33 |
| 5786 | *am33_2 |
| 5787 | { |
| 5788 | int srcreg1, dstreg1, dstreg2; |
| 5789 | int result1; |
| 5790 | |
| 5791 | PC = cia; |
| 5792 | srcreg1 = translate_rreg (SD_, RM1); |
| 5793 | dstreg1 = translate_rreg (SD_, RN1); |
| 5794 | dstreg2 = translate_rreg (SD_, RN2); |
| 5795 | |
| 5796 | result1 = State.regs[dstreg1] - State.regs[srcreg1]; |
| 5797 | State.regs[dstreg2] <<= IMM4; |
| 5798 | State.regs[dstreg1] = result1; |
| 5799 | } |
| 5800 | |
| 5801 | // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2 |
| 5802 | 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add |
| 5803 | "mov_add" |
| 5804 | *am33 |
| 5805 | *am33_2 |
| 5806 | { |
| 5807 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5808 | int result1; |
| 5809 | |
| 5810 | PC = cia; |
| 5811 | srcreg1 = translate_rreg (SD_, RM1); |
| 5812 | srcreg2 = translate_rreg (SD_, RM2); |
| 5813 | dstreg1 = translate_rreg (SD_, RN1); |
| 5814 | dstreg2 = translate_rreg (SD_, RN2); |
| 5815 | |
| 5816 | result1 = State.regs[srcreg1]; |
| 5817 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 5818 | State.regs[dstreg1] = result1; |
| 5819 | } |
| 5820 | |
| 5821 | // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2 |
| 5822 | 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add |
| 5823 | "mov_add" |
| 5824 | *am33 |
| 5825 | *am33_2 |
| 5826 | { |
| 5827 | int srcreg1, dstreg1, dstreg2; |
| 5828 | int result1; |
| 5829 | |
| 5830 | PC = cia; |
| 5831 | srcreg1 = translate_rreg (SD_, RM1); |
| 5832 | dstreg1 = translate_rreg (SD_, RN1); |
| 5833 | dstreg2 = translate_rreg (SD_, RN2); |
| 5834 | |
| 5835 | result1 = State.regs[srcreg1]; |
| 5836 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 5837 | State.regs[dstreg1] = result1; |
| 5838 | } |
| 5839 | |
| 5840 | // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2 |
| 5841 | 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub |
| 5842 | "mov_sub" |
| 5843 | *am33 |
| 5844 | *am33_2 |
| 5845 | { |
| 5846 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5847 | int result1; |
| 5848 | |
| 5849 | PC = cia; |
| 5850 | srcreg1 = translate_rreg (SD_, RM1); |
| 5851 | srcreg2 = translate_rreg (SD_, RM2); |
| 5852 | dstreg1 = translate_rreg (SD_, RN1); |
| 5853 | dstreg2 = translate_rreg (SD_, RN2); |
| 5854 | |
| 5855 | result1 = State.regs[srcreg1]; |
| 5856 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 5857 | State.regs[dstreg1] = result1; |
| 5858 | } |
| 5859 | |
| 5860 | // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2 |
| 5861 | 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub |
| 5862 | "mov_sub" |
| 5863 | *am33 |
| 5864 | *am33_2 |
| 5865 | { |
| 5866 | int srcreg1, dstreg1, dstreg2; |
| 5867 | int result1; |
| 5868 | |
| 5869 | PC = cia; |
| 5870 | srcreg1 = translate_rreg (SD_, RM1); |
| 5871 | dstreg1 = translate_rreg (SD_, RN1); |
| 5872 | dstreg2 = translate_rreg (SD_, RN2); |
| 5873 | |
| 5874 | result1 = State.regs[srcreg1]; |
| 5875 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 5876 | State.regs[dstreg1] = result1; |
| 5877 | } |
| 5878 | |
| 5879 | // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2 |
| 5880 | 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp |
| 5881 | "mov_cmp" |
| 5882 | *am33 |
| 5883 | *am33_2 |
| 5884 | { |
| 5885 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5886 | |
| 5887 | PC = cia; |
| 5888 | srcreg1 = translate_rreg (SD_, RM1); |
| 5889 | srcreg2 = translate_rreg (SD_, RM2); |
| 5890 | dstreg1 = translate_rreg (SD_, RN1); |
| 5891 | dstreg2 = translate_rreg (SD_, RN2); |
| 5892 | |
| 5893 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 5894 | State.regs[dstreg1] = State.regs[srcreg1]; |
| 5895 | } |
| 5896 | |
| 5897 | // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2 |
| 5898 | 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp |
| 5899 | "mov_cmp" |
| 5900 | *am33 |
| 5901 | *am33_2 |
| 5902 | { |
| 5903 | int srcreg1, dstreg1, dstreg2; |
| 5904 | |
| 5905 | PC = cia; |
| 5906 | srcreg1 = translate_rreg (SD_, RM1); |
| 5907 | dstreg1 = translate_rreg (SD_, RN1); |
| 5908 | dstreg2 = translate_rreg (SD_, RN2); |
| 5909 | |
| 5910 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 5911 | State.regs[dstreg1] = State.regs[srcreg1]; |
| 5912 | } |
| 5913 | |
| 5914 | // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2 |
| 5915 | 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov |
| 5916 | "mov_mov" |
| 5917 | *am33 |
| 5918 | *am33_2 |
| 5919 | { |
| 5920 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5921 | int result1; |
| 5922 | |
| 5923 | PC = cia; |
| 5924 | srcreg1 = translate_rreg (SD_, RM1); |
| 5925 | srcreg2 = translate_rreg (SD_, RM2); |
| 5926 | dstreg1 = translate_rreg (SD_, RN1); |
| 5927 | dstreg2 = translate_rreg (SD_, RN2); |
| 5928 | |
| 5929 | result1 = State.regs[srcreg1]; |
| 5930 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 5931 | State.regs[dstreg1] = result1; |
| 5932 | } |
| 5933 | |
| 5934 | // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2 |
| 5935 | 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov |
| 5936 | "mov_mov" |
| 5937 | *am33 |
| 5938 | *am33_2 |
| 5939 | { |
| 5940 | int srcreg1, dstreg1, dstreg2; |
| 5941 | int result1; |
| 5942 | |
| 5943 | PC = cia; |
| 5944 | srcreg1 = translate_rreg (SD_, RM1); |
| 5945 | dstreg1 = translate_rreg (SD_, RN1); |
| 5946 | dstreg2 = translate_rreg (SD_, RN2); |
| 5947 | |
| 5948 | result1 = State.regs[srcreg1]; |
| 5949 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 5950 | State.regs[dstreg1] = result1; |
| 5951 | } |
| 5952 | |
| 5953 | // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2 |
| 5954 | 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr |
| 5955 | "mov_asr" |
| 5956 | *am33 |
| 5957 | *am33_2 |
| 5958 | { |
| 5959 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 5960 | int result1; |
| 5961 | signed int temp; |
| 5962 | |
| 5963 | PC = cia; |
| 5964 | srcreg1 = translate_rreg (SD_, RM1); |
| 5965 | srcreg2 = translate_rreg (SD_, RM2); |
| 5966 | dstreg1 = translate_rreg (SD_, RN1); |
| 5967 | dstreg2 = translate_rreg (SD_, RN2); |
| 5968 | |
| 5969 | result1 = State.regs[srcreg1]; |
| 5970 | temp = State.regs[dstreg2]; |
| 5971 | temp >>= State.regs[srcreg2]; |
| 5972 | State.regs[dstreg2] = temp; |
| 5973 | State.regs[dstreg1] = result1; |
| 5974 | } |
| 5975 | |
| 5976 | // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2 |
| 5977 | 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr |
| 5978 | "mov_asr" |
| 5979 | *am33 |
| 5980 | *am33_2 |
| 5981 | { |
| 5982 | int srcreg1, dstreg1, dstreg2; |
| 5983 | int result1; |
| 5984 | signed int temp; |
| 5985 | |
| 5986 | PC = cia; |
| 5987 | srcreg1 = translate_rreg (SD_, RM1); |
| 5988 | dstreg1 = translate_rreg (SD_, RN1); |
| 5989 | dstreg2 = translate_rreg (SD_, RN2); |
| 5990 | |
| 5991 | result1 = State.regs[srcreg1]; |
| 5992 | temp = State.regs[dstreg2]; |
| 5993 | temp >>= IMM4; |
| 5994 | State.regs[dstreg2] = temp; |
| 5995 | State.regs[dstreg1] = result1; |
| 5996 | } |
| 5997 | |
| 5998 | // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2 |
| 5999 | 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr |
| 6000 | "mov_lsr" |
| 6001 | *am33 |
| 6002 | *am33_2 |
| 6003 | { |
| 6004 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 6005 | int result1; |
| 6006 | |
| 6007 | PC = cia; |
| 6008 | srcreg1 = translate_rreg (SD_, RM1); |
| 6009 | srcreg2 = translate_rreg (SD_, RM2); |
| 6010 | dstreg1 = translate_rreg (SD_, RN1); |
| 6011 | dstreg2 = translate_rreg (SD_, RN2); |
| 6012 | |
| 6013 | result1 = State.regs[srcreg1]; |
| 6014 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 6015 | State.regs[dstreg1] = result1; |
| 6016 | } |
| 6017 | |
| 6018 | // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2 |
| 6019 | 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr |
| 6020 | "mov_lsr" |
| 6021 | *am33 |
| 6022 | *am33_2 |
| 6023 | { |
| 6024 | int srcreg1, dstreg1, dstreg2; |
| 6025 | int result1; |
| 6026 | |
| 6027 | PC = cia; |
| 6028 | srcreg1 = translate_rreg (SD_, RM1); |
| 6029 | dstreg1 = translate_rreg (SD_, RN1); |
| 6030 | dstreg2 = translate_rreg (SD_, RN2); |
| 6031 | |
| 6032 | result1 = State.regs[srcreg1]; |
| 6033 | State.regs[dstreg2] >>= IMM4; |
| 6034 | State.regs[dstreg1] = result1; |
| 6035 | } |
| 6036 | |
| 6037 | |
| 6038 | // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2 |
| 6039 | 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl |
| 6040 | "mov_asl" |
| 6041 | *am33 |
| 6042 | *am33_2 |
| 6043 | { |
| 6044 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 6045 | int result1; |
| 6046 | |
| 6047 | PC = cia; |
| 6048 | srcreg1 = translate_rreg (SD_, RM1); |
| 6049 | srcreg2 = translate_rreg (SD_, RM2); |
| 6050 | dstreg1 = translate_rreg (SD_, RN1); |
| 6051 | dstreg2 = translate_rreg (SD_, RN2); |
| 6052 | |
| 6053 | result1 = State.regs[srcreg1]; |
| 6054 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 6055 | State.regs[dstreg1] = result1; |
| 6056 | } |
| 6057 | |
| 6058 | // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2 |
| 6059 | 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl |
| 6060 | "mov_asl" |
| 6061 | *am33 |
| 6062 | *am33_2 |
| 6063 | { |
| 6064 | int srcreg1, dstreg1, dstreg2; |
| 6065 | int result1; |
| 6066 | |
| 6067 | PC = cia; |
| 6068 | srcreg1 = translate_rreg (SD_, RM1); |
| 6069 | dstreg1 = translate_rreg (SD_, RN1); |
| 6070 | dstreg2 = translate_rreg (SD_, RN2); |
| 6071 | |
| 6072 | result1 = State.regs[srcreg1]; |
| 6073 | State.regs[dstreg2] <<= IMM4; |
| 6074 | State.regs[dstreg1] = result1; |
| 6075 | } |
| 6076 | |
| 6077 | // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2 |
| 6078 | 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add |
| 6079 | "add_add" |
| 6080 | *am33 |
| 6081 | *am33_2 |
| 6082 | { |
| 6083 | int srcreg2, dstreg1, dstreg2; |
| 6084 | int result1; |
| 6085 | |
| 6086 | PC = cia; |
| 6087 | srcreg2 = translate_rreg (SD_, RM2); |
| 6088 | dstreg1 = translate_rreg (SD_, RN1); |
| 6089 | dstreg2 = translate_rreg (SD_, RN2); |
| 6090 | |
| 6091 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6092 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 6093 | State.regs[dstreg1] = result1; |
| 6094 | } |
| 6095 | |
| 6096 | // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2 |
| 6097 | 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add |
| 6098 | "add_add" |
| 6099 | *am33 |
| 6100 | *am33_2 |
| 6101 | { |
| 6102 | int dstreg1, dstreg2; |
| 6103 | int result1; |
| 6104 | |
| 6105 | PC = cia; |
| 6106 | dstreg1 = translate_rreg (SD_, RN1); |
| 6107 | dstreg2 = translate_rreg (SD_, RN2); |
| 6108 | |
| 6109 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6110 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 6111 | State.regs[dstreg1] = result1; |
| 6112 | } |
| 6113 | |
| 6114 | // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2 |
| 6115 | 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub |
| 6116 | "add_sub" |
| 6117 | *am33 |
| 6118 | *am33_2 |
| 6119 | { |
| 6120 | int srcreg2, dstreg1, dstreg2; |
| 6121 | int result1; |
| 6122 | |
| 6123 | PC = cia; |
| 6124 | srcreg2 = translate_rreg (SD_, RM2); |
| 6125 | dstreg1 = translate_rreg (SD_, RN1); |
| 6126 | dstreg2 = translate_rreg (SD_, RN2); |
| 6127 | |
| 6128 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6129 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 6130 | State.regs[dstreg1] = result1; |
| 6131 | } |
| 6132 | |
| 6133 | // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2 |
| 6134 | 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub |
| 6135 | "add_sub" |
| 6136 | *am33 |
| 6137 | *am33_2 |
| 6138 | { |
| 6139 | int dstreg1, dstreg2; |
| 6140 | int result1; |
| 6141 | |
| 6142 | PC = cia; |
| 6143 | dstreg1 = translate_rreg (SD_, RN1); |
| 6144 | dstreg2 = translate_rreg (SD_, RN2); |
| 6145 | |
| 6146 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6147 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 6148 | State.regs[dstreg1] = result1; |
| 6149 | } |
| 6150 | |
| 6151 | // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2 |
| 6152 | 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp |
| 6153 | "add_cmp" |
| 6154 | *am33 |
| 6155 | *am33_2 |
| 6156 | { |
| 6157 | int srcreg2, dstreg1, dstreg2; |
| 6158 | |
| 6159 | PC = cia; |
| 6160 | srcreg2 = translate_rreg (SD_, RM2); |
| 6161 | dstreg1 = translate_rreg (SD_, RN1); |
| 6162 | dstreg2 = translate_rreg (SD_, RN2); |
| 6163 | |
| 6164 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 6165 | State.regs[dstreg1] += EXTEND4 (IMM4A); |
| 6166 | } |
| 6167 | |
| 6168 | // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2 |
| 6169 | 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp |
| 6170 | "add_cmp" |
| 6171 | *am33 |
| 6172 | *am33_2 |
| 6173 | { |
| 6174 | int dstreg1, dstreg2; |
| 6175 | |
| 6176 | PC = cia; |
| 6177 | dstreg1 = translate_rreg (SD_, RN1); |
| 6178 | dstreg2 = translate_rreg (SD_, RN2); |
| 6179 | |
| 6180 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 6181 | State.regs[dstreg1] += EXTEND4 (IMM4A); |
| 6182 | } |
| 6183 | |
| 6184 | // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2 |
| 6185 | 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov |
| 6186 | "add_mov" |
| 6187 | *am33 |
| 6188 | *am33_2 |
| 6189 | { |
| 6190 | int srcreg2, dstreg1, dstreg2; |
| 6191 | int result1; |
| 6192 | |
| 6193 | PC = cia; |
| 6194 | srcreg2 = translate_rreg (SD_, RM2); |
| 6195 | dstreg1 = translate_rreg (SD_, RN1); |
| 6196 | dstreg2 = translate_rreg (SD_, RN2); |
| 6197 | |
| 6198 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6199 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 6200 | State.regs[dstreg1] = result1; |
| 6201 | } |
| 6202 | |
| 6203 | // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2 |
| 6204 | 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov |
| 6205 | "add_mov" |
| 6206 | *am33 |
| 6207 | *am33_2 |
| 6208 | { |
| 6209 | int dstreg1, dstreg2; |
| 6210 | int result1; |
| 6211 | |
| 6212 | PC = cia; |
| 6213 | dstreg1 = translate_rreg (SD_, RN1); |
| 6214 | dstreg2 = translate_rreg (SD_, RN2); |
| 6215 | |
| 6216 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6217 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 6218 | State.regs[dstreg1] = result1; |
| 6219 | } |
| 6220 | |
| 6221 | // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2 |
| 6222 | 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr |
| 6223 | "add_asr" |
| 6224 | *am33 |
| 6225 | *am33_2 |
| 6226 | { |
| 6227 | int srcreg2, dstreg1, dstreg2; |
| 6228 | int result1; |
| 6229 | signed int temp; |
| 6230 | |
| 6231 | PC = cia; |
| 6232 | srcreg2 = translate_rreg (SD_, RM2); |
| 6233 | dstreg1 = translate_rreg (SD_, RN1); |
| 6234 | dstreg2 = translate_rreg (SD_, RN2); |
| 6235 | |
| 6236 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6237 | temp = State.regs[dstreg2]; |
| 6238 | temp >>= State.regs[srcreg2]; |
| 6239 | State.regs[dstreg2] = temp; |
| 6240 | State.regs[dstreg1] = result1; |
| 6241 | } |
| 6242 | |
| 6243 | // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2 |
| 6244 | 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr |
| 6245 | "add_asr" |
| 6246 | *am33 |
| 6247 | *am33_2 |
| 6248 | { |
| 6249 | int dstreg1, dstreg2; |
| 6250 | int result1; |
| 6251 | signed int temp; |
| 6252 | |
| 6253 | PC = cia; |
| 6254 | dstreg1 = translate_rreg (SD_, RN1); |
| 6255 | dstreg2 = translate_rreg (SD_, RN2); |
| 6256 | |
| 6257 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6258 | temp = State.regs[dstreg2]; |
| 6259 | temp >>= IMM4; |
| 6260 | State.regs[dstreg2] = temp; |
| 6261 | State.regs[dstreg1] = result1; |
| 6262 | } |
| 6263 | |
| 6264 | // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2 |
| 6265 | 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr |
| 6266 | "add_lsr" |
| 6267 | *am33 |
| 6268 | *am33_2 |
| 6269 | { |
| 6270 | int srcreg2, dstreg1, dstreg2; |
| 6271 | int result1; |
| 6272 | |
| 6273 | PC = cia; |
| 6274 | srcreg2 = translate_rreg (SD_, RM2); |
| 6275 | dstreg1 = translate_rreg (SD_, RN1); |
| 6276 | dstreg2 = translate_rreg (SD_, RN2); |
| 6277 | |
| 6278 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6279 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 6280 | State.regs[dstreg1] = result1; |
| 6281 | } |
| 6282 | |
| 6283 | // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2 |
| 6284 | 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr |
| 6285 | "add_lsr" |
| 6286 | *am33 |
| 6287 | *am33_2 |
| 6288 | { |
| 6289 | int dstreg1, dstreg2; |
| 6290 | int result1; |
| 6291 | |
| 6292 | PC = cia; |
| 6293 | dstreg1 = translate_rreg (SD_, RN1); |
| 6294 | dstreg2 = translate_rreg (SD_, RN2); |
| 6295 | |
| 6296 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6297 | State.regs[dstreg2] >>= IMM4; |
| 6298 | State.regs[dstreg1] = result1; |
| 6299 | } |
| 6300 | |
| 6301 | |
| 6302 | // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2 |
| 6303 | 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl |
| 6304 | "add_asl" |
| 6305 | *am33 |
| 6306 | *am33_2 |
| 6307 | { |
| 6308 | int srcreg2, dstreg1, dstreg2; |
| 6309 | int result1; |
| 6310 | |
| 6311 | PC = cia; |
| 6312 | srcreg2 = translate_rreg (SD_, RM2); |
| 6313 | dstreg1 = translate_rreg (SD_, RN1); |
| 6314 | dstreg2 = translate_rreg (SD_, RN2); |
| 6315 | |
| 6316 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6317 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 6318 | State.regs[dstreg1] = result1; |
| 6319 | } |
| 6320 | |
| 6321 | // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2 |
| 6322 | 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl |
| 6323 | "add_asl" |
| 6324 | *am33 |
| 6325 | *am33_2 |
| 6326 | { |
| 6327 | int dstreg1, dstreg2; |
| 6328 | int result1; |
| 6329 | |
| 6330 | PC = cia; |
| 6331 | dstreg1 = translate_rreg (SD_, RN1); |
| 6332 | dstreg2 = translate_rreg (SD_, RN2); |
| 6333 | |
| 6334 | result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); |
| 6335 | State.regs[dstreg2] <<= IMM4; |
| 6336 | State.regs[dstreg1] = result1; |
| 6337 | } |
| 6338 | |
| 6339 | // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2 |
| 6340 | 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add |
| 6341 | "cmp_add" |
| 6342 | *am33 |
| 6343 | *am33_2 |
| 6344 | { |
| 6345 | int srcreg2, dstreg1, dstreg2; |
| 6346 | |
| 6347 | PC = cia; |
| 6348 | srcreg2 = translate_rreg (SD_, RM2); |
| 6349 | dstreg1 = translate_rreg (SD_, RN1); |
| 6350 | dstreg2 = translate_rreg (SD_, RN2); |
| 6351 | |
| 6352 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6353 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 6354 | } |
| 6355 | |
| 6356 | // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2 |
| 6357 | 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add |
| 6358 | "cmp_add" |
| 6359 | *am33 |
| 6360 | *am33_2 |
| 6361 | { |
| 6362 | int dstreg1, dstreg2; |
| 6363 | |
| 6364 | PC = cia; |
| 6365 | dstreg1 = translate_rreg (SD_, RN1); |
| 6366 | dstreg2 = translate_rreg (SD_, RN2); |
| 6367 | |
| 6368 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6369 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 6370 | } |
| 6371 | |
| 6372 | // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2 |
| 6373 | 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub |
| 6374 | "cmp_sub" |
| 6375 | *am33 |
| 6376 | *am33_2 |
| 6377 | { |
| 6378 | int srcreg2, dstreg1, dstreg2; |
| 6379 | |
| 6380 | PC = cia; |
| 6381 | srcreg2 = translate_rreg (SD_, RM2); |
| 6382 | dstreg1 = translate_rreg (SD_, RN1); |
| 6383 | dstreg2 = translate_rreg (SD_, RN2); |
| 6384 | |
| 6385 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6386 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 6387 | } |
| 6388 | |
| 6389 | // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2 |
| 6390 | 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub |
| 6391 | "cmp_sub" |
| 6392 | *am33 |
| 6393 | *am33_2 |
| 6394 | { |
| 6395 | int dstreg1, dstreg2; |
| 6396 | |
| 6397 | PC = cia; |
| 6398 | dstreg1 = translate_rreg (SD_, RN1); |
| 6399 | dstreg2 = translate_rreg (SD_, RN2); |
| 6400 | |
| 6401 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6402 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 6403 | } |
| 6404 | |
| 6405 | // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2 |
| 6406 | 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov |
| 6407 | "cmp_mov" |
| 6408 | *am33 |
| 6409 | *am33_2 |
| 6410 | { |
| 6411 | int srcreg2, dstreg1, dstreg2; |
| 6412 | |
| 6413 | PC = cia; |
| 6414 | srcreg2 = translate_rreg (SD_, RM2); |
| 6415 | dstreg1 = translate_rreg (SD_, RN1); |
| 6416 | dstreg2 = translate_rreg (SD_, RN2); |
| 6417 | |
| 6418 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6419 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 6420 | } |
| 6421 | |
| 6422 | // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2 |
| 6423 | 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov |
| 6424 | "cmp_mov" |
| 6425 | *am33 |
| 6426 | *am33_2 |
| 6427 | { |
| 6428 | int dstreg1, dstreg2; |
| 6429 | |
| 6430 | PC = cia; |
| 6431 | dstreg1 = translate_rreg (SD_, RN1); |
| 6432 | dstreg2 = translate_rreg (SD_, RN2); |
| 6433 | |
| 6434 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6435 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 6436 | } |
| 6437 | |
| 6438 | // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2 |
| 6439 | 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr |
| 6440 | "cmp_asr" |
| 6441 | *am33 |
| 6442 | *am33_2 |
| 6443 | { |
| 6444 | int srcreg2, dstreg1, dstreg2; |
| 6445 | signed int temp; |
| 6446 | |
| 6447 | PC = cia; |
| 6448 | srcreg2 = translate_rreg (SD_, RM2); |
| 6449 | dstreg1 = translate_rreg (SD_, RN1); |
| 6450 | dstreg2 = translate_rreg (SD_, RN2); |
| 6451 | |
| 6452 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6453 | temp = State.regs[dstreg2]; |
| 6454 | temp >>= State.regs[srcreg2]; |
| 6455 | State.regs[dstreg2] = temp; |
| 6456 | } |
| 6457 | |
| 6458 | // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2 |
| 6459 | 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr |
| 6460 | "cmp_asr" |
| 6461 | *am33 |
| 6462 | *am33_2 |
| 6463 | { |
| 6464 | int dstreg1, dstreg2; |
| 6465 | signed int temp; |
| 6466 | |
| 6467 | PC = cia; |
| 6468 | dstreg1 = translate_rreg (SD_, RN1); |
| 6469 | dstreg2 = translate_rreg (SD_, RN2); |
| 6470 | |
| 6471 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6472 | temp = State.regs[dstreg2]; |
| 6473 | temp >>= IMM4; |
| 6474 | State.regs[dstreg2] = temp; |
| 6475 | } |
| 6476 | |
| 6477 | // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2 |
| 6478 | 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr |
| 6479 | "cmp_lsr" |
| 6480 | *am33 |
| 6481 | *am33_2 |
| 6482 | { |
| 6483 | int srcreg2, dstreg1, dstreg2; |
| 6484 | |
| 6485 | PC = cia; |
| 6486 | srcreg2 = translate_rreg (SD_, RM2); |
| 6487 | dstreg1 = translate_rreg (SD_, RN1); |
| 6488 | dstreg2 = translate_rreg (SD_, RN2); |
| 6489 | |
| 6490 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6491 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 6492 | } |
| 6493 | |
| 6494 | // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2 |
| 6495 | 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr |
| 6496 | "cmp_lsr" |
| 6497 | *am33 |
| 6498 | *am33_2 |
| 6499 | { |
| 6500 | int dstreg1, dstreg2; |
| 6501 | |
| 6502 | PC = cia; |
| 6503 | dstreg1 = translate_rreg (SD_, RN1); |
| 6504 | dstreg2 = translate_rreg (SD_, RN2); |
| 6505 | |
| 6506 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6507 | State.regs[dstreg2] >>= IMM4; |
| 6508 | } |
| 6509 | |
| 6510 | |
| 6511 | // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2 |
| 6512 | 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl |
| 6513 | "cmp_asl" |
| 6514 | *am33 |
| 6515 | *am33_2 |
| 6516 | { |
| 6517 | int srcreg2, dstreg1, dstreg2; |
| 6518 | |
| 6519 | PC = cia; |
| 6520 | srcreg2 = translate_rreg (SD_, RM2); |
| 6521 | dstreg1 = translate_rreg (SD_, RN1); |
| 6522 | dstreg2 = translate_rreg (SD_, RN2); |
| 6523 | |
| 6524 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6525 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 6526 | } |
| 6527 | |
| 6528 | // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2 |
| 6529 | 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl |
| 6530 | "cmp_asl" |
| 6531 | *am33 |
| 6532 | *am33_2 |
| 6533 | { |
| 6534 | int dstreg1, dstreg2; |
| 6535 | |
| 6536 | PC = cia; |
| 6537 | dstreg1 = translate_rreg (SD_, RN1); |
| 6538 | dstreg2 = translate_rreg (SD_, RN2); |
| 6539 | |
| 6540 | genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); |
| 6541 | State.regs[dstreg2] <<= IMM4; |
| 6542 | } |
| 6543 | |
| 6544 | // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2 |
| 6545 | 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add |
| 6546 | "sub_add" |
| 6547 | *am33 |
| 6548 | *am33_2 |
| 6549 | { |
| 6550 | int srcreg2, dstreg1, dstreg2; |
| 6551 | int result1; |
| 6552 | |
| 6553 | PC = cia; |
| 6554 | srcreg2 = translate_rreg (SD_, RM2); |
| 6555 | dstreg1 = translate_rreg (SD_, RN1); |
| 6556 | dstreg2 = translate_rreg (SD_, RN2); |
| 6557 | |
| 6558 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6559 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 6560 | State.regs[dstreg1] = result1; |
| 6561 | } |
| 6562 | |
| 6563 | // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2 |
| 6564 | 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add |
| 6565 | "sub_add" |
| 6566 | *am33 |
| 6567 | *am33_2 |
| 6568 | { |
| 6569 | int dstreg1, dstreg2; |
| 6570 | int result1; |
| 6571 | |
| 6572 | PC = cia; |
| 6573 | dstreg1 = translate_rreg (SD_, RN1); |
| 6574 | dstreg2 = translate_rreg (SD_, RN2); |
| 6575 | |
| 6576 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6577 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 6578 | State.regs[dstreg1] = result1; |
| 6579 | } |
| 6580 | |
| 6581 | // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2 |
| 6582 | 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub |
| 6583 | "sub_sub" |
| 6584 | *am33 |
| 6585 | *am33_2 |
| 6586 | { |
| 6587 | int srcreg2, dstreg1, dstreg2; |
| 6588 | int result1; |
| 6589 | |
| 6590 | PC = cia; |
| 6591 | srcreg2 = translate_rreg (SD_, RM2); |
| 6592 | dstreg1 = translate_rreg (SD_, RN1); |
| 6593 | dstreg2 = translate_rreg (SD_, RN2); |
| 6594 | |
| 6595 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6596 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 6597 | State.regs[dstreg1] = result1; |
| 6598 | } |
| 6599 | |
| 6600 | // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2 |
| 6601 | 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub |
| 6602 | "sub_sub" |
| 6603 | *am33 |
| 6604 | *am33_2 |
| 6605 | { |
| 6606 | int dstreg1, dstreg2; |
| 6607 | int result1; |
| 6608 | |
| 6609 | PC = cia; |
| 6610 | dstreg1 = translate_rreg (SD_, RN1); |
| 6611 | dstreg2 = translate_rreg (SD_, RN2); |
| 6612 | |
| 6613 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6614 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 6615 | State.regs[dstreg1] = result1; |
| 6616 | } |
| 6617 | |
| 6618 | // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2 |
| 6619 | 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp |
| 6620 | "sub_cmp" |
| 6621 | *am33 |
| 6622 | *am33_2 |
| 6623 | { |
| 6624 | int srcreg2, dstreg1, dstreg2; |
| 6625 | |
| 6626 | PC = cia; |
| 6627 | srcreg2 = translate_rreg (SD_, RM2); |
| 6628 | dstreg1 = translate_rreg (SD_, RN1); |
| 6629 | dstreg2 = translate_rreg (SD_, RN2); |
| 6630 | |
| 6631 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 6632 | State.regs[dstreg1] -= EXTEND4 (IMM4A); |
| 6633 | } |
| 6634 | |
| 6635 | // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2 |
| 6636 | 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp |
| 6637 | "sub_cmp" |
| 6638 | *am33 |
| 6639 | *am33_2 |
| 6640 | { |
| 6641 | int dstreg1, dstreg2; |
| 6642 | |
| 6643 | PC = cia; |
| 6644 | dstreg1 = translate_rreg (SD_, RN1); |
| 6645 | dstreg2 = translate_rreg (SD_, RN2); |
| 6646 | |
| 6647 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 6648 | State.regs[dstreg1] -= EXTEND4 (IMM4A); |
| 6649 | } |
| 6650 | |
| 6651 | // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2 |
| 6652 | 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov |
| 6653 | "sub_mov" |
| 6654 | *am33 |
| 6655 | *am33_2 |
| 6656 | { |
| 6657 | int srcreg2, dstreg1, dstreg2; |
| 6658 | int result1; |
| 6659 | |
| 6660 | PC = cia; |
| 6661 | srcreg2 = translate_rreg (SD_, RM2); |
| 6662 | dstreg1 = translate_rreg (SD_, RN1); |
| 6663 | dstreg2 = translate_rreg (SD_, RN2); |
| 6664 | |
| 6665 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6666 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 6667 | State.regs[dstreg1] = result1; |
| 6668 | } |
| 6669 | |
| 6670 | // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2 |
| 6671 | 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov |
| 6672 | "sub_mov" |
| 6673 | *am33 |
| 6674 | *am33_2 |
| 6675 | { |
| 6676 | int dstreg1, dstreg2; |
| 6677 | int result1; |
| 6678 | |
| 6679 | PC = cia; |
| 6680 | dstreg1 = translate_rreg (SD_, RN1); |
| 6681 | dstreg2 = translate_rreg (SD_, RN2); |
| 6682 | |
| 6683 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6684 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 6685 | State.regs[dstreg1] = result1; |
| 6686 | } |
| 6687 | |
| 6688 | // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2 |
| 6689 | 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr |
| 6690 | "sub_asr" |
| 6691 | *am33 |
| 6692 | *am33_2 |
| 6693 | { |
| 6694 | int srcreg2, dstreg1, dstreg2; |
| 6695 | int result1; |
| 6696 | signed int temp; |
| 6697 | |
| 6698 | PC = cia; |
| 6699 | srcreg2 = translate_rreg (SD_, RM2); |
| 6700 | dstreg1 = translate_rreg (SD_, RN1); |
| 6701 | dstreg2 = translate_rreg (SD_, RN2); |
| 6702 | |
| 6703 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6704 | temp = State.regs[dstreg2]; |
| 6705 | temp >>= State.regs[srcreg2]; |
| 6706 | State.regs[dstreg2] = temp; |
| 6707 | State.regs[dstreg1] = result1; |
| 6708 | } |
| 6709 | |
| 6710 | // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2 |
| 6711 | 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr |
| 6712 | "sub_asr" |
| 6713 | *am33 |
| 6714 | *am33_2 |
| 6715 | { |
| 6716 | int dstreg1, dstreg2; |
| 6717 | int result1; |
| 6718 | signed int temp; |
| 6719 | |
| 6720 | PC = cia; |
| 6721 | dstreg1 = translate_rreg (SD_, RN1); |
| 6722 | dstreg2 = translate_rreg (SD_, RN2); |
| 6723 | |
| 6724 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6725 | temp = State.regs[dstreg2]; |
| 6726 | temp >>= IMM4; |
| 6727 | State.regs[dstreg2] = temp; |
| 6728 | State.regs[dstreg1] = result1; |
| 6729 | } |
| 6730 | |
| 6731 | // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2 |
| 6732 | 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr |
| 6733 | "sub_lsr" |
| 6734 | *am33 |
| 6735 | *am33_2 |
| 6736 | { |
| 6737 | int srcreg2, dstreg1, dstreg2; |
| 6738 | int result1; |
| 6739 | |
| 6740 | PC = cia; |
| 6741 | srcreg2 = translate_rreg (SD_, RM2); |
| 6742 | dstreg1 = translate_rreg (SD_, RN1); |
| 6743 | dstreg2 = translate_rreg (SD_, RN2); |
| 6744 | |
| 6745 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6746 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 6747 | State.regs[dstreg1] = result1; |
| 6748 | } |
| 6749 | |
| 6750 | // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2 |
| 6751 | 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr |
| 6752 | "sub_lsr" |
| 6753 | *am33 |
| 6754 | *am33_2 |
| 6755 | { |
| 6756 | int dstreg1, dstreg2; |
| 6757 | int result1; |
| 6758 | |
| 6759 | PC = cia; |
| 6760 | dstreg1 = translate_rreg (SD_, RN1); |
| 6761 | dstreg2 = translate_rreg (SD_, RN2); |
| 6762 | |
| 6763 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6764 | State.regs[dstreg2] >>= IMM4; |
| 6765 | State.regs[dstreg1] = result1; |
| 6766 | } |
| 6767 | |
| 6768 | |
| 6769 | // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2 |
| 6770 | 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl |
| 6771 | "sub_asl" |
| 6772 | *am33 |
| 6773 | *am33_2 |
| 6774 | { |
| 6775 | int srcreg2, dstreg1, dstreg2; |
| 6776 | int result1; |
| 6777 | |
| 6778 | PC = cia; |
| 6779 | srcreg2 = translate_rreg (SD_, RM2); |
| 6780 | dstreg1 = translate_rreg (SD_, RN1); |
| 6781 | dstreg2 = translate_rreg (SD_, RN2); |
| 6782 | |
| 6783 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6784 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 6785 | State.regs[dstreg1] = result1; |
| 6786 | } |
| 6787 | |
| 6788 | // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2 |
| 6789 | 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl |
| 6790 | "sub_asl" |
| 6791 | *am33 |
| 6792 | *am33_2 |
| 6793 | { |
| 6794 | int dstreg1, dstreg2; |
| 6795 | int result1; |
| 6796 | |
| 6797 | PC = cia; |
| 6798 | dstreg1 = translate_rreg (SD_, RN1); |
| 6799 | dstreg2 = translate_rreg (SD_, RN2); |
| 6800 | |
| 6801 | result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); |
| 6802 | State.regs[dstreg2] <<= IMM4; |
| 6803 | State.regs[dstreg1] = result1; |
| 6804 | } |
| 6805 | |
| 6806 | // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2 |
| 6807 | 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add |
| 6808 | "mov_add" |
| 6809 | *am33 |
| 6810 | *am33_2 |
| 6811 | { |
| 6812 | int srcreg2, dstreg1, dstreg2; |
| 6813 | int result1; |
| 6814 | |
| 6815 | PC = cia; |
| 6816 | srcreg2 = translate_rreg (SD_, RM2); |
| 6817 | dstreg1 = translate_rreg (SD_, RN1); |
| 6818 | dstreg2 = translate_rreg (SD_, RN2); |
| 6819 | |
| 6820 | result1 = EXTEND4 (IMM4A); |
| 6821 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 6822 | State.regs[dstreg1] = result1; |
| 6823 | } |
| 6824 | |
| 6825 | // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2 |
| 6826 | 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add |
| 6827 | "mov_add" |
| 6828 | *am33 |
| 6829 | *am33_2 |
| 6830 | { |
| 6831 | int dstreg1, dstreg2; |
| 6832 | int result1; |
| 6833 | |
| 6834 | PC = cia; |
| 6835 | dstreg1 = translate_rreg (SD_, RN1); |
| 6836 | dstreg2 = translate_rreg (SD_, RN2); |
| 6837 | |
| 6838 | result1 = EXTEND4 (IMM4A); |
| 6839 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 6840 | State.regs[dstreg1] = result1; |
| 6841 | } |
| 6842 | |
| 6843 | // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2 |
| 6844 | 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub |
| 6845 | "mov_sub" |
| 6846 | *am33 |
| 6847 | *am33_2 |
| 6848 | { |
| 6849 | int srcreg2, dstreg1, dstreg2; |
| 6850 | int result1; |
| 6851 | |
| 6852 | PC = cia; |
| 6853 | srcreg2 = translate_rreg (SD_, RM2); |
| 6854 | dstreg1 = translate_rreg (SD_, RN1); |
| 6855 | dstreg2 = translate_rreg (SD_, RN2); |
| 6856 | |
| 6857 | result1 = EXTEND4 (IMM4A); |
| 6858 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 6859 | State.regs[dstreg1] = result1; |
| 6860 | } |
| 6861 | |
| 6862 | // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2 |
| 6863 | 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub |
| 6864 | "mov_sub" |
| 6865 | *am33 |
| 6866 | *am33_2 |
| 6867 | { |
| 6868 | int dstreg1, dstreg2; |
| 6869 | int result1; |
| 6870 | |
| 6871 | PC = cia; |
| 6872 | dstreg1 = translate_rreg (SD_, RN1); |
| 6873 | dstreg2 = translate_rreg (SD_, RN2); |
| 6874 | |
| 6875 | result1 = EXTEND4 (IMM4A); |
| 6876 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 6877 | State.regs[dstreg1] = result1; |
| 6878 | } |
| 6879 | |
| 6880 | // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2 |
| 6881 | 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp |
| 6882 | "mov_cmp" |
| 6883 | *am33 |
| 6884 | *am33_2 |
| 6885 | { |
| 6886 | int srcreg2, dstreg1, dstreg2; |
| 6887 | |
| 6888 | PC = cia; |
| 6889 | srcreg2 = translate_rreg (SD_, RM2); |
| 6890 | dstreg1 = translate_rreg (SD_, RN1); |
| 6891 | dstreg2 = translate_rreg (SD_, RN2); |
| 6892 | |
| 6893 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 6894 | State.regs[dstreg1] = EXTEND4 (IMM4A); |
| 6895 | } |
| 6896 | |
| 6897 | // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2 |
| 6898 | 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp |
| 6899 | "mov_cmp" |
| 6900 | *am33 |
| 6901 | *am33_2 |
| 6902 | { |
| 6903 | int dstreg1, dstreg2; |
| 6904 | |
| 6905 | PC = cia; |
| 6906 | dstreg1 = translate_rreg (SD_, RN1); |
| 6907 | dstreg2 = translate_rreg (SD_, RN2); |
| 6908 | |
| 6909 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 6910 | State.regs[dstreg1] = EXTEND4 (IMM4A); |
| 6911 | } |
| 6912 | |
| 6913 | // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2 |
| 6914 | 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov |
| 6915 | "mov_mov" |
| 6916 | *am33 |
| 6917 | *am33_2 |
| 6918 | { |
| 6919 | int srcreg2, dstreg1, dstreg2; |
| 6920 | int result1; |
| 6921 | |
| 6922 | PC = cia; |
| 6923 | srcreg2 = translate_rreg (SD_, RM2); |
| 6924 | dstreg1 = translate_rreg (SD_, RN1); |
| 6925 | dstreg2 = translate_rreg (SD_, RN2); |
| 6926 | |
| 6927 | result1 = EXTEND4 (IMM4A); |
| 6928 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 6929 | State.regs[dstreg1] = result1; |
| 6930 | } |
| 6931 | |
| 6932 | // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2 |
| 6933 | 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov |
| 6934 | "mov_mov" |
| 6935 | *am33 |
| 6936 | *am33_2 |
| 6937 | { |
| 6938 | int dstreg1, dstreg2; |
| 6939 | int result1; |
| 6940 | |
| 6941 | PC = cia; |
| 6942 | dstreg1 = translate_rreg (SD_, RN1); |
| 6943 | dstreg2 = translate_rreg (SD_, RN2); |
| 6944 | |
| 6945 | result1 = EXTEND4 (IMM4A); |
| 6946 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 6947 | State.regs[dstreg1] = result1; |
| 6948 | } |
| 6949 | |
| 6950 | // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2 |
| 6951 | 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr |
| 6952 | "mov_asr" |
| 6953 | *am33 |
| 6954 | *am33_2 |
| 6955 | { |
| 6956 | int srcreg2, dstreg1, dstreg2; |
| 6957 | int result1; |
| 6958 | signed int temp; |
| 6959 | |
| 6960 | PC = cia; |
| 6961 | srcreg2 = translate_rreg (SD_, RM2); |
| 6962 | dstreg1 = translate_rreg (SD_, RN1); |
| 6963 | dstreg2 = translate_rreg (SD_, RN2); |
| 6964 | |
| 6965 | result1 = EXTEND4 (IMM4A); |
| 6966 | temp = State.regs[dstreg2]; |
| 6967 | temp >>= State.regs[srcreg2]; |
| 6968 | State.regs[dstreg2] = temp; |
| 6969 | State.regs[dstreg1] = result1; |
| 6970 | } |
| 6971 | |
| 6972 | // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2 |
| 6973 | 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr |
| 6974 | "mov_asr" |
| 6975 | *am33 |
| 6976 | *am33_2 |
| 6977 | { |
| 6978 | int dstreg1, dstreg2; |
| 6979 | int result1; |
| 6980 | signed int temp; |
| 6981 | |
| 6982 | PC = cia; |
| 6983 | dstreg1 = translate_rreg (SD_, RN1); |
| 6984 | dstreg2 = translate_rreg (SD_, RN2); |
| 6985 | |
| 6986 | result1 = EXTEND4 (IMM4A); |
| 6987 | temp = State.regs[dstreg2]; |
| 6988 | temp >>= IMM4; |
| 6989 | State.regs[dstreg2] = temp; |
| 6990 | State.regs[dstreg1] = result1; |
| 6991 | } |
| 6992 | |
| 6993 | // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2 |
| 6994 | 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr |
| 6995 | "mov_lsr" |
| 6996 | *am33 |
| 6997 | *am33_2 |
| 6998 | { |
| 6999 | int srcreg2, dstreg1, dstreg2; |
| 7000 | int result1; |
| 7001 | |
| 7002 | PC = cia; |
| 7003 | srcreg2 = translate_rreg (SD_, RM2); |
| 7004 | dstreg1 = translate_rreg (SD_, RN1); |
| 7005 | dstreg2 = translate_rreg (SD_, RN2); |
| 7006 | |
| 7007 | result1 = EXTEND4 (IMM4A); |
| 7008 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 7009 | State.regs[dstreg1] = result1; |
| 7010 | } |
| 7011 | |
| 7012 | // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2 |
| 7013 | 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr |
| 7014 | "mov_lsr" |
| 7015 | *am33 |
| 7016 | *am33_2 |
| 7017 | { |
| 7018 | int dstreg1, dstreg2; |
| 7019 | int result1; |
| 7020 | |
| 7021 | PC = cia; |
| 7022 | dstreg1 = translate_rreg (SD_, RN1); |
| 7023 | dstreg2 = translate_rreg (SD_, RN2); |
| 7024 | |
| 7025 | result1 = EXTEND4 (IMM4A); |
| 7026 | State.regs[dstreg2] >>= IMM4; |
| 7027 | State.regs[dstreg1] = result1; |
| 7028 | } |
| 7029 | |
| 7030 | |
| 7031 | // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2 |
| 7032 | 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl |
| 7033 | "mov_asl" |
| 7034 | *am33 |
| 7035 | *am33_2 |
| 7036 | { |
| 7037 | int srcreg2, dstreg1, dstreg2; |
| 7038 | int result1; |
| 7039 | |
| 7040 | PC = cia; |
| 7041 | srcreg2 = translate_rreg (SD_, RM2); |
| 7042 | dstreg1 = translate_rreg (SD_, RN1); |
| 7043 | dstreg2 = translate_rreg (SD_, RN2); |
| 7044 | |
| 7045 | result1 = EXTEND4 (IMM4A); |
| 7046 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 7047 | State.regs[dstreg1] = result1; |
| 7048 | } |
| 7049 | |
| 7050 | // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2 |
| 7051 | 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl |
| 7052 | "mov_asl" |
| 7053 | *am33 |
| 7054 | *am33_2 |
| 7055 | { |
| 7056 | int dstreg1, dstreg2; |
| 7057 | int result1; |
| 7058 | |
| 7059 | PC = cia; |
| 7060 | dstreg1 = translate_rreg (SD_, RN1); |
| 7061 | dstreg2 = translate_rreg (SD_, RN2); |
| 7062 | |
| 7063 | result1 = EXTEND4 (IMM4A); |
| 7064 | State.regs[dstreg2] <<= IMM4; |
| 7065 | State.regs[dstreg1] = result1; |
| 7066 | } |
| 7067 | |
| 7068 | // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2 |
| 7069 | 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add |
| 7070 | "and_add" |
| 7071 | *am33 |
| 7072 | *am33_2 |
| 7073 | { |
| 7074 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7075 | int result1; |
| 7076 | |
| 7077 | PC = cia; |
| 7078 | srcreg1 = translate_rreg (SD_, RM1); |
| 7079 | srcreg2 = translate_rreg (SD_, RM2); |
| 7080 | dstreg1 = translate_rreg (SD_, RN1); |
| 7081 | dstreg2 = translate_rreg (SD_, RN2); |
| 7082 | |
| 7083 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7084 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 7085 | State.regs[dstreg1] = result1; |
| 7086 | } |
| 7087 | |
| 7088 | // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2 |
| 7089 | 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add |
| 7090 | "and_add" |
| 7091 | *am33 |
| 7092 | *am33_2 |
| 7093 | { |
| 7094 | int srcreg1, dstreg1, dstreg2; |
| 7095 | int result1; |
| 7096 | |
| 7097 | PC = cia; |
| 7098 | srcreg1 = translate_rreg (SD_, RM1); |
| 7099 | dstreg1 = translate_rreg (SD_, RN1); |
| 7100 | dstreg2 = translate_rreg (SD_, RN2); |
| 7101 | |
| 7102 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7103 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 7104 | State.regs[dstreg1] = result1; |
| 7105 | } |
| 7106 | |
| 7107 | // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2 |
| 7108 | 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub |
| 7109 | "and_sub" |
| 7110 | *am33 |
| 7111 | *am33_2 |
| 7112 | { |
| 7113 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7114 | int result1; |
| 7115 | |
| 7116 | PC = cia; |
| 7117 | srcreg1 = translate_rreg (SD_, RM1); |
| 7118 | srcreg2 = translate_rreg (SD_, RM2); |
| 7119 | dstreg1 = translate_rreg (SD_, RN1); |
| 7120 | dstreg2 = translate_rreg (SD_, RN2); |
| 7121 | |
| 7122 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7123 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 7124 | State.regs[dstreg1] = result1; |
| 7125 | } |
| 7126 | |
| 7127 | // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2 |
| 7128 | 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub |
| 7129 | "and_sub" |
| 7130 | *am33 |
| 7131 | *am33_2 |
| 7132 | { |
| 7133 | int srcreg1, dstreg1, dstreg2; |
| 7134 | int result1; |
| 7135 | |
| 7136 | PC = cia; |
| 7137 | srcreg1 = translate_rreg (SD_, RM1); |
| 7138 | dstreg1 = translate_rreg (SD_, RN1); |
| 7139 | dstreg2 = translate_rreg (SD_, RN2); |
| 7140 | |
| 7141 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7142 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 7143 | State.regs[dstreg1] = result1; |
| 7144 | } |
| 7145 | |
| 7146 | // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2 |
| 7147 | 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp |
| 7148 | "and_cmp" |
| 7149 | *am33 |
| 7150 | *am33_2 |
| 7151 | { |
| 7152 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7153 | |
| 7154 | PC = cia; |
| 7155 | srcreg1 = translate_rreg (SD_, RM1); |
| 7156 | srcreg2 = translate_rreg (SD_, RM2); |
| 7157 | dstreg1 = translate_rreg (SD_, RN1); |
| 7158 | dstreg2 = translate_rreg (SD_, RN2); |
| 7159 | |
| 7160 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 7161 | State.regs[dstreg1] &= State.regs[srcreg1]; |
| 7162 | } |
| 7163 | |
| 7164 | // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2 |
| 7165 | 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp |
| 7166 | "and_cmp" |
| 7167 | *am33 |
| 7168 | *am33_2 |
| 7169 | { |
| 7170 | int srcreg1, dstreg1, dstreg2; |
| 7171 | |
| 7172 | PC = cia; |
| 7173 | srcreg1 = translate_rreg (SD_, RM1); |
| 7174 | dstreg1 = translate_rreg (SD_, RN1); |
| 7175 | dstreg2 = translate_rreg (SD_, RN2); |
| 7176 | |
| 7177 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 7178 | State.regs[dstreg1] &= State.regs[srcreg1]; |
| 7179 | } |
| 7180 | |
| 7181 | // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2 |
| 7182 | 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov |
| 7183 | "and_mov" |
| 7184 | *am33 |
| 7185 | *am33_2 |
| 7186 | { |
| 7187 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7188 | int result1; |
| 7189 | |
| 7190 | PC = cia; |
| 7191 | srcreg1 = translate_rreg (SD_, RM1); |
| 7192 | srcreg2 = translate_rreg (SD_, RM2); |
| 7193 | dstreg1 = translate_rreg (SD_, RN1); |
| 7194 | dstreg2 = translate_rreg (SD_, RN2); |
| 7195 | |
| 7196 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7197 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 7198 | State.regs[dstreg1] = result1; |
| 7199 | } |
| 7200 | |
| 7201 | // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2 |
| 7202 | 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov |
| 7203 | "and_mov" |
| 7204 | *am33 |
| 7205 | *am33_2 |
| 7206 | { |
| 7207 | int srcreg1, dstreg1, dstreg2; |
| 7208 | int result1; |
| 7209 | |
| 7210 | PC = cia; |
| 7211 | srcreg1 = translate_rreg (SD_, RM1); |
| 7212 | dstreg1 = translate_rreg (SD_, RN1); |
| 7213 | dstreg2 = translate_rreg (SD_, RN2); |
| 7214 | |
| 7215 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7216 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 7217 | State.regs[dstreg1] = result1; |
| 7218 | } |
| 7219 | |
| 7220 | // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2 |
| 7221 | 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr |
| 7222 | "and_asr" |
| 7223 | *am33 |
| 7224 | *am33_2 |
| 7225 | { |
| 7226 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7227 | int result1; |
| 7228 | signed int temp; |
| 7229 | |
| 7230 | PC = cia; |
| 7231 | srcreg1 = translate_rreg (SD_, RM1); |
| 7232 | srcreg2 = translate_rreg (SD_, RM2); |
| 7233 | dstreg1 = translate_rreg (SD_, RN1); |
| 7234 | dstreg2 = translate_rreg (SD_, RN2); |
| 7235 | |
| 7236 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7237 | temp = State.regs[dstreg2]; |
| 7238 | temp >>= State.regs[srcreg2]; |
| 7239 | State.regs[dstreg2] = temp; |
| 7240 | State.regs[dstreg1] = result1; |
| 7241 | } |
| 7242 | |
| 7243 | // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2 |
| 7244 | 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr |
| 7245 | "and_asr" |
| 7246 | *am33 |
| 7247 | *am33_2 |
| 7248 | { |
| 7249 | int srcreg1, dstreg1, dstreg2; |
| 7250 | int result1; |
| 7251 | signed int temp; |
| 7252 | |
| 7253 | PC = cia; |
| 7254 | srcreg1 = translate_rreg (SD_, RM1); |
| 7255 | dstreg1 = translate_rreg (SD_, RN1); |
| 7256 | dstreg2 = translate_rreg (SD_, RN2); |
| 7257 | |
| 7258 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7259 | temp = State.regs[dstreg2]; |
| 7260 | temp >>= IMM4; |
| 7261 | State.regs[dstreg2] = temp; |
| 7262 | State.regs[dstreg1] = result1; |
| 7263 | } |
| 7264 | |
| 7265 | // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2 |
| 7266 | 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr |
| 7267 | "and_lsr" |
| 7268 | *am33 |
| 7269 | *am33_2 |
| 7270 | { |
| 7271 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7272 | int result1; |
| 7273 | |
| 7274 | PC = cia; |
| 7275 | srcreg1 = translate_rreg (SD_, RM1); |
| 7276 | srcreg2 = translate_rreg (SD_, RM2); |
| 7277 | dstreg1 = translate_rreg (SD_, RN1); |
| 7278 | dstreg2 = translate_rreg (SD_, RN2); |
| 7279 | |
| 7280 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7281 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 7282 | State.regs[dstreg1] = result1; |
| 7283 | } |
| 7284 | |
| 7285 | // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2 |
| 7286 | 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr |
| 7287 | "and_lsr" |
| 7288 | *am33 |
| 7289 | *am33_2 |
| 7290 | { |
| 7291 | int srcreg1, dstreg1, dstreg2; |
| 7292 | int result1; |
| 7293 | |
| 7294 | PC = cia; |
| 7295 | srcreg1 = translate_rreg (SD_, RM1); |
| 7296 | dstreg1 = translate_rreg (SD_, RN1); |
| 7297 | dstreg2 = translate_rreg (SD_, RN2); |
| 7298 | |
| 7299 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7300 | State.regs[dstreg2] >>= IMM4; |
| 7301 | State.regs[dstreg1] = result1; |
| 7302 | } |
| 7303 | |
| 7304 | |
| 7305 | // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2 |
| 7306 | 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl |
| 7307 | "and_asl" |
| 7308 | *am33 |
| 7309 | *am33_2 |
| 7310 | { |
| 7311 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7312 | int result1; |
| 7313 | |
| 7314 | PC = cia; |
| 7315 | srcreg1 = translate_rreg (SD_, RM1); |
| 7316 | srcreg2 = translate_rreg (SD_, RM2); |
| 7317 | dstreg1 = translate_rreg (SD_, RN1); |
| 7318 | dstreg2 = translate_rreg (SD_, RN2); |
| 7319 | |
| 7320 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7321 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 7322 | State.regs[dstreg1] = result1; |
| 7323 | } |
| 7324 | |
| 7325 | // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2 |
| 7326 | 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl |
| 7327 | "and_asl" |
| 7328 | *am33 |
| 7329 | *am33_2 |
| 7330 | { |
| 7331 | int srcreg1, dstreg1, dstreg2; |
| 7332 | int result1; |
| 7333 | |
| 7334 | PC = cia; |
| 7335 | srcreg1 = translate_rreg (SD_, RM1); |
| 7336 | dstreg1 = translate_rreg (SD_, RN1); |
| 7337 | dstreg2 = translate_rreg (SD_, RN2); |
| 7338 | |
| 7339 | result1 = State.regs[dstreg1] & State.regs[srcreg1]; |
| 7340 | State.regs[dstreg2] <<= IMM4; |
| 7341 | State.regs[dstreg1] = result1; |
| 7342 | } |
| 7343 | |
| 7344 | // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2 |
| 7345 | 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add |
| 7346 | "dmach_add" |
| 7347 | *am33 |
| 7348 | *am33_2 |
| 7349 | { |
| 7350 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7351 | signed32 temp, temp2, sum; |
| 7352 | |
| 7353 | PC = cia; |
| 7354 | srcreg1 = translate_rreg (SD_, RM1); |
| 7355 | srcreg2 = translate_rreg (SD_, RM2); |
| 7356 | dstreg1 = translate_rreg (SD_, RN1); |
| 7357 | dstreg2 = translate_rreg (SD_, RN2); |
| 7358 | |
| 7359 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7360 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7361 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7362 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7363 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7364 | |
| 7365 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 7366 | State.regs[dstreg1] = sum; |
| 7367 | } |
| 7368 | |
| 7369 | // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2 |
| 7370 | 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add |
| 7371 | "dmach_add" |
| 7372 | *am33 |
| 7373 | *am33_2 |
| 7374 | { |
| 7375 | int srcreg1, dstreg1, dstreg2; |
| 7376 | signed32 temp, temp2, sum; |
| 7377 | |
| 7378 | PC = cia; |
| 7379 | srcreg1 = translate_rreg (SD_, RM1); |
| 7380 | dstreg1 = translate_rreg (SD_, RN1); |
| 7381 | dstreg2 = translate_rreg (SD_, RN2); |
| 7382 | |
| 7383 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7384 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7385 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7386 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7387 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7388 | |
| 7389 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 7390 | State.regs[dstreg1] = sum; |
| 7391 | } |
| 7392 | |
| 7393 | // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2 |
| 7394 | 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub |
| 7395 | "dmach_sub" |
| 7396 | *am33 |
| 7397 | *am33_2 |
| 7398 | { |
| 7399 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7400 | signed32 temp, temp2, sum; |
| 7401 | |
| 7402 | PC = cia; |
| 7403 | srcreg1 = translate_rreg (SD_, RM1); |
| 7404 | srcreg2 = translate_rreg (SD_, RM2); |
| 7405 | dstreg1 = translate_rreg (SD_, RN1); |
| 7406 | dstreg2 = translate_rreg (SD_, RN2); |
| 7407 | |
| 7408 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7409 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7410 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7411 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7412 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7413 | |
| 7414 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 7415 | State.regs[dstreg1] = sum; |
| 7416 | } |
| 7417 | |
| 7418 | // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2 |
| 7419 | 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub |
| 7420 | "dmach_sub" |
| 7421 | *am33 |
| 7422 | *am33_2 |
| 7423 | { |
| 7424 | int srcreg1, dstreg1, dstreg2; |
| 7425 | signed32 temp, temp2, sum; |
| 7426 | |
| 7427 | PC = cia; |
| 7428 | srcreg1 = translate_rreg (SD_, RM1); |
| 7429 | dstreg1 = translate_rreg (SD_, RN1); |
| 7430 | dstreg2 = translate_rreg (SD_, RN2); |
| 7431 | |
| 7432 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7433 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7434 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7435 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7436 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7437 | |
| 7438 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 7439 | State.regs[dstreg1] = sum; |
| 7440 | } |
| 7441 | |
| 7442 | // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2 |
| 7443 | 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp |
| 7444 | "dmach_cmp" |
| 7445 | *am33 |
| 7446 | *am33_2 |
| 7447 | { |
| 7448 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7449 | signed32 temp, temp2, sum; |
| 7450 | |
| 7451 | PC = cia; |
| 7452 | srcreg1 = translate_rreg (SD_, RM1); |
| 7453 | srcreg2 = translate_rreg (SD_, RM2); |
| 7454 | dstreg1 = translate_rreg (SD_, RN1); |
| 7455 | dstreg2 = translate_rreg (SD_, RN2); |
| 7456 | |
| 7457 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7458 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7459 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7460 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7461 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7462 | |
| 7463 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 7464 | State.regs[dstreg1] = sum; |
| 7465 | } |
| 7466 | |
| 7467 | // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2 |
| 7468 | 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp |
| 7469 | "dmach_cmp" |
| 7470 | *am33 |
| 7471 | *am33_2 |
| 7472 | { |
| 7473 | int srcreg1, dstreg1, dstreg2; |
| 7474 | signed32 temp, temp2, sum; |
| 7475 | |
| 7476 | PC = cia; |
| 7477 | srcreg1 = translate_rreg (SD_, RM1); |
| 7478 | dstreg1 = translate_rreg (SD_, RN1); |
| 7479 | dstreg2 = translate_rreg (SD_, RN2); |
| 7480 | |
| 7481 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7482 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7483 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7484 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7485 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7486 | |
| 7487 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 7488 | State.regs[dstreg1] = sum; |
| 7489 | } |
| 7490 | |
| 7491 | // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2 |
| 7492 | 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov |
| 7493 | "dmach_mov" |
| 7494 | *am33 |
| 7495 | *am33_2 |
| 7496 | { |
| 7497 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7498 | signed32 temp, temp2, sum; |
| 7499 | |
| 7500 | PC = cia; |
| 7501 | srcreg1 = translate_rreg (SD_, RM1); |
| 7502 | srcreg2 = translate_rreg (SD_, RM2); |
| 7503 | dstreg1 = translate_rreg (SD_, RN1); |
| 7504 | dstreg2 = translate_rreg (SD_, RN2); |
| 7505 | |
| 7506 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7507 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7508 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7509 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7510 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7511 | |
| 7512 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 7513 | State.regs[dstreg1] = sum; |
| 7514 | } |
| 7515 | |
| 7516 | // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2 |
| 7517 | 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov |
| 7518 | "dmach_mov" |
| 7519 | *am33 |
| 7520 | *am33_2 |
| 7521 | { |
| 7522 | int srcreg1, dstreg1, dstreg2; |
| 7523 | signed32 temp, temp2, sum; |
| 7524 | |
| 7525 | PC = cia; |
| 7526 | srcreg1 = translate_rreg (SD_, RM1); |
| 7527 | dstreg1 = translate_rreg (SD_, RN1); |
| 7528 | dstreg2 = translate_rreg (SD_, RN2); |
| 7529 | |
| 7530 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7531 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7532 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7533 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7534 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7535 | |
| 7536 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 7537 | State.regs[dstreg1] = sum; |
| 7538 | } |
| 7539 | |
| 7540 | // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2 |
| 7541 | 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr |
| 7542 | "dmach_asr" |
| 7543 | *am33 |
| 7544 | *am33_2 |
| 7545 | { |
| 7546 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7547 | signed32 temp, temp2, sum; |
| 7548 | |
| 7549 | PC = cia; |
| 7550 | srcreg1 = translate_rreg (SD_, RM1); |
| 7551 | srcreg2 = translate_rreg (SD_, RM2); |
| 7552 | dstreg1 = translate_rreg (SD_, RN1); |
| 7553 | dstreg2 = translate_rreg (SD_, RN2); |
| 7554 | |
| 7555 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7556 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7557 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7558 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7559 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7560 | |
| 7561 | temp = State.regs[dstreg2]; |
| 7562 | temp >>= State.regs[srcreg2]; |
| 7563 | State.regs[dstreg2] = temp; |
| 7564 | State.regs[dstreg1] = sum; |
| 7565 | } |
| 7566 | |
| 7567 | // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2 |
| 7568 | 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr |
| 7569 | "dmach_asr" |
| 7570 | *am33 |
| 7571 | *am33_2 |
| 7572 | { |
| 7573 | int srcreg1, dstreg1, dstreg2; |
| 7574 | signed32 temp, temp2, sum; |
| 7575 | |
| 7576 | PC = cia; |
| 7577 | srcreg1 = translate_rreg (SD_, RM1); |
| 7578 | dstreg1 = translate_rreg (SD_, RN1); |
| 7579 | dstreg2 = translate_rreg (SD_, RN2); |
| 7580 | |
| 7581 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7582 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7583 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7584 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7585 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7586 | |
| 7587 | temp = State.regs[dstreg2]; |
| 7588 | temp >>= IMM4; |
| 7589 | State.regs[dstreg2] = temp; |
| 7590 | State.regs[dstreg1] = sum; |
| 7591 | } |
| 7592 | |
| 7593 | // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2 |
| 7594 | 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr |
| 7595 | "dmach_lsr" |
| 7596 | *am33 |
| 7597 | *am33_2 |
| 7598 | { |
| 7599 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7600 | signed32 temp, temp2, sum; |
| 7601 | |
| 7602 | PC = cia; |
| 7603 | srcreg1 = translate_rreg (SD_, RM1); |
| 7604 | srcreg2 = translate_rreg (SD_, RM2); |
| 7605 | dstreg1 = translate_rreg (SD_, RN1); |
| 7606 | dstreg2 = translate_rreg (SD_, RN2); |
| 7607 | |
| 7608 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7609 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7610 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7611 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7612 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7613 | |
| 7614 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 7615 | State.regs[dstreg1] = sum; |
| 7616 | } |
| 7617 | |
| 7618 | // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2 |
| 7619 | 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr |
| 7620 | "dmach_lsr" |
| 7621 | *am33 |
| 7622 | *am33_2 |
| 7623 | { |
| 7624 | int srcreg1, dstreg1, dstreg2; |
| 7625 | signed32 temp, temp2, sum; |
| 7626 | |
| 7627 | PC = cia; |
| 7628 | srcreg1 = translate_rreg (SD_, RM1); |
| 7629 | dstreg1 = translate_rreg (SD_, RN1); |
| 7630 | dstreg2 = translate_rreg (SD_, RN2); |
| 7631 | |
| 7632 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7633 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7634 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7635 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7636 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7637 | |
| 7638 | State.regs[dstreg2] >>= IMM4; |
| 7639 | State.regs[dstreg1] = sum; |
| 7640 | } |
| 7641 | |
| 7642 | |
| 7643 | // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2 |
| 7644 | 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl |
| 7645 | "dmach_asl" |
| 7646 | *am33 |
| 7647 | *am33_2 |
| 7648 | { |
| 7649 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7650 | signed32 temp, temp2, sum; |
| 7651 | |
| 7652 | PC = cia; |
| 7653 | srcreg1 = translate_rreg (SD_, RM1); |
| 7654 | srcreg2 = translate_rreg (SD_, RM2); |
| 7655 | dstreg1 = translate_rreg (SD_, RN1); |
| 7656 | dstreg2 = translate_rreg (SD_, RN2); |
| 7657 | |
| 7658 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7659 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7660 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7661 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7662 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7663 | |
| 7664 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 7665 | State.regs[dstreg1] = sum; |
| 7666 | } |
| 7667 | |
| 7668 | // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2 |
| 7669 | 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl |
| 7670 | "dmach_asl" |
| 7671 | *am33 |
| 7672 | *am33_2 |
| 7673 | { |
| 7674 | int srcreg1, dstreg1, dstreg2; |
| 7675 | signed32 temp, temp2, sum; |
| 7676 | |
| 7677 | PC = cia; |
| 7678 | srcreg1 = translate_rreg (SD_, RM1); |
| 7679 | dstreg1 = translate_rreg (SD_, RN1); |
| 7680 | dstreg2 = translate_rreg (SD_, RN2); |
| 7681 | |
| 7682 | temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) |
| 7683 | * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); |
| 7684 | temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) |
| 7685 | * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); |
| 7686 | sum = temp + temp2 + State.regs[REG_MCRL]; |
| 7687 | |
| 7688 | State.regs[dstreg2] <<= IMM4; |
| 7689 | State.regs[dstreg1] = sum; |
| 7690 | } |
| 7691 | |
| 7692 | // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2 |
| 7693 | 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add |
| 7694 | "xor_add" |
| 7695 | *am33 |
| 7696 | *am33_2 |
| 7697 | { |
| 7698 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7699 | int result1; |
| 7700 | |
| 7701 | PC = cia; |
| 7702 | srcreg1 = translate_rreg (SD_, RM1); |
| 7703 | srcreg2 = translate_rreg (SD_, RM2); |
| 7704 | dstreg1 = translate_rreg (SD_, RN1); |
| 7705 | dstreg2 = translate_rreg (SD_, RN2); |
| 7706 | |
| 7707 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7708 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 7709 | State.regs[dstreg1] = result1; |
| 7710 | } |
| 7711 | |
| 7712 | // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2 |
| 7713 | 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add |
| 7714 | "xor_add" |
| 7715 | *am33 |
| 7716 | *am33_2 |
| 7717 | { |
| 7718 | int srcreg1, dstreg1, dstreg2; |
| 7719 | int result1; |
| 7720 | |
| 7721 | PC = cia; |
| 7722 | srcreg1 = translate_rreg (SD_, RM1); |
| 7723 | dstreg1 = translate_rreg (SD_, RN1); |
| 7724 | dstreg2 = translate_rreg (SD_, RN2); |
| 7725 | |
| 7726 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7727 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 7728 | State.regs[dstreg1] = result1; |
| 7729 | } |
| 7730 | |
| 7731 | // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2 |
| 7732 | 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub |
| 7733 | "xor_sub" |
| 7734 | *am33 |
| 7735 | *am33_2 |
| 7736 | { |
| 7737 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7738 | int result1; |
| 7739 | |
| 7740 | PC = cia; |
| 7741 | srcreg1 = translate_rreg (SD_, RM1); |
| 7742 | srcreg2 = translate_rreg (SD_, RM2); |
| 7743 | dstreg1 = translate_rreg (SD_, RN1); |
| 7744 | dstreg2 = translate_rreg (SD_, RN2); |
| 7745 | |
| 7746 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7747 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 7748 | State.regs[dstreg1] = result1; |
| 7749 | } |
| 7750 | |
| 7751 | // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2 |
| 7752 | 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub |
| 7753 | "xor_sub" |
| 7754 | *am33 |
| 7755 | *am33_2 |
| 7756 | { |
| 7757 | int srcreg1, dstreg1, dstreg2; |
| 7758 | int result1; |
| 7759 | |
| 7760 | PC = cia; |
| 7761 | srcreg1 = translate_rreg (SD_, RM1); |
| 7762 | dstreg1 = translate_rreg (SD_, RN1); |
| 7763 | dstreg2 = translate_rreg (SD_, RN2); |
| 7764 | |
| 7765 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7766 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 7767 | State.regs[dstreg1] = result1; |
| 7768 | } |
| 7769 | |
| 7770 | // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2 |
| 7771 | 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp |
| 7772 | "xor_cmp" |
| 7773 | *am33 |
| 7774 | *am33_2 |
| 7775 | { |
| 7776 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7777 | |
| 7778 | PC = cia; |
| 7779 | srcreg1 = translate_rreg (SD_, RM1); |
| 7780 | srcreg2 = translate_rreg (SD_, RM2); |
| 7781 | dstreg1 = translate_rreg (SD_, RN1); |
| 7782 | dstreg2 = translate_rreg (SD_, RN2); |
| 7783 | |
| 7784 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 7785 | State.regs[dstreg1] ^= State.regs[srcreg1]; |
| 7786 | } |
| 7787 | |
| 7788 | // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2 |
| 7789 | 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp |
| 7790 | "xor_cmp" |
| 7791 | *am33 |
| 7792 | *am33_2 |
| 7793 | { |
| 7794 | int srcreg1, dstreg1, dstreg2; |
| 7795 | |
| 7796 | PC = cia; |
| 7797 | srcreg1 = translate_rreg (SD_, RM1); |
| 7798 | dstreg1 = translate_rreg (SD_, RN1); |
| 7799 | dstreg2 = translate_rreg (SD_, RN2); |
| 7800 | |
| 7801 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 7802 | State.regs[dstreg1] ^= State.regs[srcreg1]; |
| 7803 | } |
| 7804 | |
| 7805 | // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2 |
| 7806 | 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov |
| 7807 | "xor_mov" |
| 7808 | *am33 |
| 7809 | *am33_2 |
| 7810 | { |
| 7811 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7812 | int result1; |
| 7813 | |
| 7814 | PC = cia; |
| 7815 | srcreg1 = translate_rreg (SD_, RM1); |
| 7816 | srcreg2 = translate_rreg (SD_, RM2); |
| 7817 | dstreg1 = translate_rreg (SD_, RN1); |
| 7818 | dstreg2 = translate_rreg (SD_, RN2); |
| 7819 | |
| 7820 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7821 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 7822 | State.regs[dstreg1] = result1; |
| 7823 | } |
| 7824 | |
| 7825 | // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2 |
| 7826 | 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov |
| 7827 | "xor_mov" |
| 7828 | *am33 |
| 7829 | *am33_2 |
| 7830 | { |
| 7831 | int srcreg1, dstreg1, dstreg2; |
| 7832 | int result1; |
| 7833 | |
| 7834 | PC = cia; |
| 7835 | srcreg1 = translate_rreg (SD_, RM1); |
| 7836 | dstreg1 = translate_rreg (SD_, RN1); |
| 7837 | dstreg2 = translate_rreg (SD_, RN2); |
| 7838 | |
| 7839 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7840 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 7841 | State.regs[dstreg1] = result1; |
| 7842 | } |
| 7843 | |
| 7844 | // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2 |
| 7845 | 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr |
| 7846 | "xor_asr" |
| 7847 | *am33 |
| 7848 | *am33_2 |
| 7849 | { |
| 7850 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7851 | int result1; |
| 7852 | signed int temp; |
| 7853 | |
| 7854 | PC = cia; |
| 7855 | srcreg1 = translate_rreg (SD_, RM1); |
| 7856 | srcreg2 = translate_rreg (SD_, RM2); |
| 7857 | dstreg1 = translate_rreg (SD_, RN1); |
| 7858 | dstreg2 = translate_rreg (SD_, RN2); |
| 7859 | |
| 7860 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7861 | temp = State.regs[dstreg2]; |
| 7862 | temp >>= State.regs[srcreg2]; |
| 7863 | State.regs[dstreg2] = temp; |
| 7864 | State.regs[dstreg1] = result1; |
| 7865 | } |
| 7866 | |
| 7867 | // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2 |
| 7868 | 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr |
| 7869 | "xor_asr" |
| 7870 | *am33 |
| 7871 | *am33_2 |
| 7872 | { |
| 7873 | int srcreg1, dstreg1, dstreg2; |
| 7874 | int result1; |
| 7875 | signed int temp; |
| 7876 | |
| 7877 | PC = cia; |
| 7878 | srcreg1 = translate_rreg (SD_, RM1); |
| 7879 | dstreg1 = translate_rreg (SD_, RN1); |
| 7880 | dstreg2 = translate_rreg (SD_, RN2); |
| 7881 | |
| 7882 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7883 | temp = State.regs[dstreg2]; |
| 7884 | temp >>= IMM4; |
| 7885 | State.regs[dstreg2] = temp; |
| 7886 | State.regs[dstreg1] = result1; |
| 7887 | } |
| 7888 | |
| 7889 | // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2 |
| 7890 | 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr |
| 7891 | "xor_lsr" |
| 7892 | *am33 |
| 7893 | *am33_2 |
| 7894 | { |
| 7895 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7896 | int result1; |
| 7897 | |
| 7898 | PC = cia; |
| 7899 | srcreg1 = translate_rreg (SD_, RM1); |
| 7900 | srcreg2 = translate_rreg (SD_, RM2); |
| 7901 | dstreg1 = translate_rreg (SD_, RN1); |
| 7902 | dstreg2 = translate_rreg (SD_, RN2); |
| 7903 | |
| 7904 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7905 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 7906 | State.regs[dstreg1] = result1; |
| 7907 | } |
| 7908 | |
| 7909 | // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2 |
| 7910 | 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr |
| 7911 | "xor_lsr" |
| 7912 | *am33 |
| 7913 | *am33_2 |
| 7914 | { |
| 7915 | int srcreg1, dstreg1, dstreg2; |
| 7916 | int result1; |
| 7917 | |
| 7918 | PC = cia; |
| 7919 | srcreg1 = translate_rreg (SD_, RM1); |
| 7920 | dstreg1 = translate_rreg (SD_, RN1); |
| 7921 | dstreg2 = translate_rreg (SD_, RN2); |
| 7922 | |
| 7923 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7924 | State.regs[dstreg2] >>= IMM4; |
| 7925 | State.regs[dstreg1] = result1; |
| 7926 | } |
| 7927 | |
| 7928 | |
| 7929 | // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2 |
| 7930 | 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl |
| 7931 | "xor_asl" |
| 7932 | *am33 |
| 7933 | *am33_2 |
| 7934 | { |
| 7935 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7936 | int result1; |
| 7937 | |
| 7938 | PC = cia; |
| 7939 | srcreg1 = translate_rreg (SD_, RM1); |
| 7940 | srcreg2 = translate_rreg (SD_, RM2); |
| 7941 | dstreg1 = translate_rreg (SD_, RN1); |
| 7942 | dstreg2 = translate_rreg (SD_, RN2); |
| 7943 | |
| 7944 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7945 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 7946 | State.regs[dstreg1] = result1; |
| 7947 | } |
| 7948 | |
| 7949 | // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2 |
| 7950 | 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl |
| 7951 | "xor_asl" |
| 7952 | *am33 |
| 7953 | *am33_2 |
| 7954 | { |
| 7955 | int srcreg1, dstreg1, dstreg2; |
| 7956 | int result1; |
| 7957 | |
| 7958 | PC = cia; |
| 7959 | srcreg1 = translate_rreg (SD_, RM1); |
| 7960 | dstreg1 = translate_rreg (SD_, RN1); |
| 7961 | dstreg2 = translate_rreg (SD_, RN2); |
| 7962 | |
| 7963 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7964 | State.regs[dstreg2] <<= IMM4; |
| 7965 | State.regs[dstreg1] = result1; |
| 7966 | } |
| 7967 | |
| 7968 | // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2 |
| 7969 | 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add |
| 7970 | "swhw_add" |
| 7971 | *am33 |
| 7972 | *am33_2 |
| 7973 | { |
| 7974 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 7975 | int result1; |
| 7976 | |
| 7977 | PC = cia; |
| 7978 | srcreg1 = translate_rreg (SD_, RM1); |
| 7979 | srcreg2 = translate_rreg (SD_, RM2); |
| 7980 | dstreg1 = translate_rreg (SD_, RN1); |
| 7981 | dstreg2 = translate_rreg (SD_, RN2); |
| 7982 | |
| 7983 | result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; |
| 7984 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 7985 | State.regs[dstreg1] = result1; |
| 7986 | } |
| 7987 | |
| 7988 | // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2 |
| 7989 | 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add |
| 7990 | "swhw_add" |
| 7991 | *am33 |
| 7992 | *am33_2 |
| 7993 | { |
| 7994 | int srcreg1, dstreg1, dstreg2; |
| 7995 | int result1; |
| 7996 | |
| 7997 | PC = cia; |
| 7998 | srcreg1 = translate_rreg (SD_, RM1); |
| 7999 | dstreg1 = translate_rreg (SD_, RN1); |
| 8000 | dstreg2 = translate_rreg (SD_, RN2); |
| 8001 | |
| 8002 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8003 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8004 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 8005 | State.regs[dstreg1] = result1; |
| 8006 | } |
| 8007 | |
| 8008 | // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2 |
| 8009 | 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub |
| 8010 | "swhw_sub" |
| 8011 | *am33 |
| 8012 | *am33_2 |
| 8013 | { |
| 8014 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8015 | int result1; |
| 8016 | |
| 8017 | PC = cia; |
| 8018 | srcreg1 = translate_rreg (SD_, RM1); |
| 8019 | srcreg2 = translate_rreg (SD_, RM2); |
| 8020 | dstreg1 = translate_rreg (SD_, RN1); |
| 8021 | dstreg2 = translate_rreg (SD_, RN2); |
| 8022 | |
| 8023 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8024 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8025 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 8026 | State.regs[dstreg1] = result1; |
| 8027 | } |
| 8028 | |
| 8029 | // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2 |
| 8030 | 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub |
| 8031 | "swhw_sub" |
| 8032 | *am33 |
| 8033 | *am33_2 |
| 8034 | { |
| 8035 | int srcreg1, dstreg1, dstreg2; |
| 8036 | int result1; |
| 8037 | |
| 8038 | PC = cia; |
| 8039 | srcreg1 = translate_rreg (SD_, RM1); |
| 8040 | dstreg1 = translate_rreg (SD_, RN1); |
| 8041 | dstreg2 = translate_rreg (SD_, RN2); |
| 8042 | |
| 8043 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8044 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8045 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 8046 | State.regs[dstreg1] = result1; |
| 8047 | } |
| 8048 | |
| 8049 | // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2 |
| 8050 | 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp |
| 8051 | "swhw_cmp" |
| 8052 | *am33 |
| 8053 | *am33_2 |
| 8054 | { |
| 8055 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8056 | |
| 8057 | PC = cia; |
| 8058 | srcreg1 = translate_rreg (SD_, RM1); |
| 8059 | srcreg2 = translate_rreg (SD_, RM2); |
| 8060 | dstreg1 = translate_rreg (SD_, RN1); |
| 8061 | dstreg2 = translate_rreg (SD_, RN2); |
| 8062 | |
| 8063 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 8064 | State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8065 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8066 | } |
| 8067 | |
| 8068 | // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2 |
| 8069 | 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp |
| 8070 | "swhw_cmp" |
| 8071 | *am33 |
| 8072 | *am33_2 |
| 8073 | { |
| 8074 | int srcreg1, dstreg1, dstreg2; |
| 8075 | |
| 8076 | PC = cia; |
| 8077 | srcreg1 = translate_rreg (SD_, RM1); |
| 8078 | dstreg1 = translate_rreg (SD_, RN1); |
| 8079 | dstreg2 = translate_rreg (SD_, RN2); |
| 8080 | |
| 8081 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 8082 | State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8083 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8084 | } |
| 8085 | |
| 8086 | // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2 |
| 8087 | 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov |
| 8088 | "swhw_mov" |
| 8089 | *am33 |
| 8090 | *am33_2 |
| 8091 | { |
| 8092 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8093 | int result1; |
| 8094 | |
| 8095 | PC = cia; |
| 8096 | srcreg1 = translate_rreg (SD_, RM1); |
| 8097 | srcreg2 = translate_rreg (SD_, RM2); |
| 8098 | dstreg1 = translate_rreg (SD_, RN1); |
| 8099 | dstreg2 = translate_rreg (SD_, RN2); |
| 8100 | |
| 8101 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8102 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8103 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 8104 | State.regs[dstreg1] = result1; |
| 8105 | } |
| 8106 | |
| 8107 | // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2 |
| 8108 | 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov |
| 8109 | "swhw_mov" |
| 8110 | *am33 |
| 8111 | *am33_2 |
| 8112 | { |
| 8113 | int srcreg1, dstreg1, dstreg2; |
| 8114 | int result1; |
| 8115 | |
| 8116 | PC = cia; |
| 8117 | srcreg1 = translate_rreg (SD_, RM1); |
| 8118 | dstreg1 = translate_rreg (SD_, RN1); |
| 8119 | dstreg2 = translate_rreg (SD_, RN2); |
| 8120 | |
| 8121 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8122 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8123 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 8124 | State.regs[dstreg1] = result1; |
| 8125 | } |
| 8126 | |
| 8127 | // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2 |
| 8128 | 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr |
| 8129 | "swhw_asr" |
| 8130 | *am33 |
| 8131 | *am33_2 |
| 8132 | { |
| 8133 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8134 | int result1; |
| 8135 | signed int temp; |
| 8136 | |
| 8137 | PC = cia; |
| 8138 | srcreg1 = translate_rreg (SD_, RM1); |
| 8139 | srcreg2 = translate_rreg (SD_, RM2); |
| 8140 | dstreg1 = translate_rreg (SD_, RN1); |
| 8141 | dstreg2 = translate_rreg (SD_, RN2); |
| 8142 | |
| 8143 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8144 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8145 | temp = State.regs[dstreg2]; |
| 8146 | temp >>= State.regs[srcreg2]; |
| 8147 | State.regs[dstreg2] = temp; |
| 8148 | State.regs[dstreg1] = result1; |
| 8149 | } |
| 8150 | |
| 8151 | // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2 |
| 8152 | 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr |
| 8153 | "swhw_asr" |
| 8154 | *am33 |
| 8155 | *am33_2 |
| 8156 | { |
| 8157 | int srcreg1, dstreg1, dstreg2; |
| 8158 | int result1; |
| 8159 | signed int temp; |
| 8160 | |
| 8161 | PC = cia; |
| 8162 | srcreg1 = translate_rreg (SD_, RM1); |
| 8163 | dstreg1 = translate_rreg (SD_, RN1); |
| 8164 | dstreg2 = translate_rreg (SD_, RN2); |
| 8165 | |
| 8166 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8167 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8168 | temp = State.regs[dstreg2]; |
| 8169 | temp >>= IMM4; |
| 8170 | State.regs[dstreg2] = temp; |
| 8171 | State.regs[dstreg1] = result1; |
| 8172 | } |
| 8173 | |
| 8174 | // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2 |
| 8175 | 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr |
| 8176 | "swhw_lsr" |
| 8177 | *am33 |
| 8178 | *am33_2 |
| 8179 | { |
| 8180 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8181 | int result1; |
| 8182 | |
| 8183 | PC = cia; |
| 8184 | srcreg1 = translate_rreg (SD_, RM1); |
| 8185 | srcreg2 = translate_rreg (SD_, RM2); |
| 8186 | dstreg1 = translate_rreg (SD_, RN1); |
| 8187 | dstreg2 = translate_rreg (SD_, RN2); |
| 8188 | |
| 8189 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8190 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8191 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 8192 | State.regs[dstreg1] = result1; |
| 8193 | } |
| 8194 | |
| 8195 | // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2 |
| 8196 | 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr |
| 8197 | "swhw_lsr" |
| 8198 | *am33 |
| 8199 | *am33_2 |
| 8200 | { |
| 8201 | int srcreg1, dstreg1, dstreg2; |
| 8202 | int result1; |
| 8203 | |
| 8204 | PC = cia; |
| 8205 | srcreg1 = translate_rreg (SD_, RM1); |
| 8206 | dstreg1 = translate_rreg (SD_, RN1); |
| 8207 | dstreg2 = translate_rreg (SD_, RN2); |
| 8208 | |
| 8209 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8210 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8211 | State.regs[dstreg2] >>= IMM4; |
| 8212 | State.regs[dstreg1] = result1; |
| 8213 | } |
| 8214 | |
| 8215 | |
| 8216 | // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2 |
| 8217 | 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl |
| 8218 | "swhw_asl" |
| 8219 | *am33 |
| 8220 | *am33_2 |
| 8221 | { |
| 8222 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8223 | int result1; |
| 8224 | |
| 8225 | PC = cia; |
| 8226 | srcreg1 = translate_rreg (SD_, RM1); |
| 8227 | srcreg2 = translate_rreg (SD_, RM2); |
| 8228 | dstreg1 = translate_rreg (SD_, RN1); |
| 8229 | dstreg2 = translate_rreg (SD_, RN2); |
| 8230 | |
| 8231 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8232 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8233 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 8234 | State.regs[dstreg1] = result1; |
| 8235 | } |
| 8236 | |
| 8237 | // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2 |
| 8238 | 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl |
| 8239 | "swhw_asl" |
| 8240 | *am33 |
| 8241 | *am33_2 |
| 8242 | { |
| 8243 | int srcreg1, dstreg1, dstreg2; |
| 8244 | int result1; |
| 8245 | |
| 8246 | PC = cia; |
| 8247 | srcreg1 = translate_rreg (SD_, RM1); |
| 8248 | dstreg1 = translate_rreg (SD_, RN1); |
| 8249 | dstreg2 = translate_rreg (SD_, RN2); |
| 8250 | |
| 8251 | result1 = (((State.regs[srcreg1] & 0xffff) << 16) |
| 8252 | | ((State.regs[srcreg1] >> 16) & 0xffff)); |
| 8253 | State.regs[dstreg2] <<= IMM4; |
| 8254 | State.regs[dstreg1] = result1; |
| 8255 | } |
| 8256 | |
| 8257 | // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2 |
| 8258 | 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add |
| 8259 | "or_add" |
| 8260 | *am33 |
| 8261 | *am33_2 |
| 8262 | { |
| 8263 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8264 | int result1; |
| 8265 | |
| 8266 | PC = cia; |
| 8267 | srcreg1 = translate_rreg (SD_, RM1); |
| 8268 | srcreg2 = translate_rreg (SD_, RM2); |
| 8269 | dstreg1 = translate_rreg (SD_, RN1); |
| 8270 | dstreg2 = translate_rreg (SD_, RN2); |
| 8271 | |
| 8272 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8273 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 8274 | State.regs[dstreg1] = result1; |
| 8275 | } |
| 8276 | |
| 8277 | // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2 |
| 8278 | 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add |
| 8279 | "or_add" |
| 8280 | *am33 |
| 8281 | *am33_2 |
| 8282 | { |
| 8283 | int srcreg1, dstreg1, dstreg2; |
| 8284 | int result1; |
| 8285 | |
| 8286 | PC = cia; |
| 8287 | srcreg1 = translate_rreg (SD_, RM1); |
| 8288 | dstreg1 = translate_rreg (SD_, RN1); |
| 8289 | dstreg2 = translate_rreg (SD_, RN2); |
| 8290 | |
| 8291 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8292 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 8293 | State.regs[dstreg1] = result1; |
| 8294 | } |
| 8295 | |
| 8296 | // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2 |
| 8297 | 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub |
| 8298 | "or_sub" |
| 8299 | *am33 |
| 8300 | *am33_2 |
| 8301 | { |
| 8302 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8303 | int result1; |
| 8304 | |
| 8305 | PC = cia; |
| 8306 | srcreg1 = translate_rreg (SD_, RM1); |
| 8307 | srcreg2 = translate_rreg (SD_, RM2); |
| 8308 | dstreg1 = translate_rreg (SD_, RN1); |
| 8309 | dstreg2 = translate_rreg (SD_, RN2); |
| 8310 | |
| 8311 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8312 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 8313 | State.regs[dstreg1] = result1; |
| 8314 | } |
| 8315 | |
| 8316 | // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2 |
| 8317 | 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub |
| 8318 | "or_sub" |
| 8319 | *am33 |
| 8320 | *am33_2 |
| 8321 | { |
| 8322 | int srcreg1, dstreg1, dstreg2; |
| 8323 | int result1; |
| 8324 | |
| 8325 | PC = cia; |
| 8326 | srcreg1 = translate_rreg (SD_, RM1); |
| 8327 | dstreg1 = translate_rreg (SD_, RN1); |
| 8328 | dstreg2 = translate_rreg (SD_, RN2); |
| 8329 | |
| 8330 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8331 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 8332 | State.regs[dstreg1] = result1; |
| 8333 | } |
| 8334 | |
| 8335 | // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2 |
| 8336 | 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp |
| 8337 | "or_cmp" |
| 8338 | *am33 |
| 8339 | *am33_2 |
| 8340 | { |
| 8341 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8342 | |
| 8343 | PC = cia; |
| 8344 | srcreg1 = translate_rreg (SD_, RM1); |
| 8345 | srcreg2 = translate_rreg (SD_, RM2); |
| 8346 | dstreg1 = translate_rreg (SD_, RN1); |
| 8347 | dstreg2 = translate_rreg (SD_, RN2); |
| 8348 | |
| 8349 | genericCmp (State.regs[srcreg2], State.regs[dstreg2]); |
| 8350 | State.regs[dstreg1] |= State.regs[srcreg1]; |
| 8351 | } |
| 8352 | |
| 8353 | // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2 |
| 8354 | 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp |
| 8355 | "or_cmp" |
| 8356 | *am33 |
| 8357 | *am33_2 |
| 8358 | { |
| 8359 | int srcreg1, dstreg1, dstreg2; |
| 8360 | |
| 8361 | PC = cia; |
| 8362 | srcreg1 = translate_rreg (SD_, RM1); |
| 8363 | dstreg1 = translate_rreg (SD_, RN1); |
| 8364 | dstreg2 = translate_rreg (SD_, RN2); |
| 8365 | |
| 8366 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 8367 | State.regs[dstreg1] |= State.regs[srcreg1]; |
| 8368 | } |
| 8369 | |
| 8370 | // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2 |
| 8371 | 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov |
| 8372 | "or_mov" |
| 8373 | *am33 |
| 8374 | *am33_2 |
| 8375 | { |
| 8376 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8377 | int result1; |
| 8378 | |
| 8379 | PC = cia; |
| 8380 | srcreg1 = translate_rreg (SD_, RM1); |
| 8381 | srcreg2 = translate_rreg (SD_, RM2); |
| 8382 | dstreg1 = translate_rreg (SD_, RN1); |
| 8383 | dstreg2 = translate_rreg (SD_, RN2); |
| 8384 | |
| 8385 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8386 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 8387 | State.regs[dstreg1] = result1; |
| 8388 | } |
| 8389 | |
| 8390 | // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2 |
| 8391 | 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov |
| 8392 | "or_mov" |
| 8393 | *am33 |
| 8394 | *am33_2 |
| 8395 | { |
| 8396 | int srcreg1, dstreg1, dstreg2; |
| 8397 | int result1; |
| 8398 | |
| 8399 | PC = cia; |
| 8400 | srcreg1 = translate_rreg (SD_, RM1); |
| 8401 | dstreg1 = translate_rreg (SD_, RN1); |
| 8402 | dstreg2 = translate_rreg (SD_, RN2); |
| 8403 | |
| 8404 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8405 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 8406 | State.regs[dstreg1] = result1; |
| 8407 | } |
| 8408 | |
| 8409 | // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2 |
| 8410 | 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr |
| 8411 | "or_asr" |
| 8412 | *am33 |
| 8413 | *am33_2 |
| 8414 | { |
| 8415 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8416 | int result1; |
| 8417 | signed int temp; |
| 8418 | |
| 8419 | PC = cia; |
| 8420 | srcreg1 = translate_rreg (SD_, RM1); |
| 8421 | srcreg2 = translate_rreg (SD_, RM2); |
| 8422 | dstreg1 = translate_rreg (SD_, RN1); |
| 8423 | dstreg2 = translate_rreg (SD_, RN2); |
| 8424 | |
| 8425 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8426 | temp = State.regs[dstreg2]; |
| 8427 | temp >>= State.regs[srcreg2]; |
| 8428 | State.regs[dstreg2] = temp; |
| 8429 | State.regs[dstreg1] = result1; |
| 8430 | } |
| 8431 | |
| 8432 | // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2 |
| 8433 | 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr |
| 8434 | "or_asr" |
| 8435 | *am33 |
| 8436 | *am33_2 |
| 8437 | { |
| 8438 | int srcreg1, dstreg1, dstreg2; |
| 8439 | int result1; |
| 8440 | signed int temp; |
| 8441 | |
| 8442 | PC = cia; |
| 8443 | srcreg1 = translate_rreg (SD_, RM1); |
| 8444 | dstreg1 = translate_rreg (SD_, RN1); |
| 8445 | dstreg2 = translate_rreg (SD_, RN2); |
| 8446 | |
| 8447 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8448 | temp = State.regs[dstreg2]; |
| 8449 | temp >>= IMM4; |
| 8450 | State.regs[dstreg2] = temp; |
| 8451 | State.regs[dstreg1] = result1; |
| 8452 | } |
| 8453 | |
| 8454 | // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2 |
| 8455 | 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr |
| 8456 | "or_lsr" |
| 8457 | *am33 |
| 8458 | *am33_2 |
| 8459 | { |
| 8460 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8461 | int result1; |
| 8462 | |
| 8463 | PC = cia; |
| 8464 | srcreg1 = translate_rreg (SD_, RM1); |
| 8465 | srcreg2 = translate_rreg (SD_, RM2); |
| 8466 | dstreg1 = translate_rreg (SD_, RN1); |
| 8467 | dstreg2 = translate_rreg (SD_, RN2); |
| 8468 | |
| 8469 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8470 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 8471 | State.regs[dstreg1] = result1; |
| 8472 | } |
| 8473 | |
| 8474 | // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2 |
| 8475 | 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr |
| 8476 | "or_lsr" |
| 8477 | *am33 |
| 8478 | *am33_2 |
| 8479 | { |
| 8480 | int srcreg1, dstreg1, dstreg2; |
| 8481 | int result1; |
| 8482 | |
| 8483 | PC = cia; |
| 8484 | srcreg1 = translate_rreg (SD_, RM1); |
| 8485 | dstreg1 = translate_rreg (SD_, RN1); |
| 8486 | dstreg2 = translate_rreg (SD_, RN2); |
| 8487 | |
| 8488 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8489 | State.regs[dstreg2] >>= IMM4; |
| 8490 | State.regs[dstreg1] = result1; |
| 8491 | } |
| 8492 | |
| 8493 | |
| 8494 | // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2 |
| 8495 | 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl |
| 8496 | "or_asl" |
| 8497 | *am33 |
| 8498 | *am33_2 |
| 8499 | { |
| 8500 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8501 | int result1; |
| 8502 | |
| 8503 | PC = cia; |
| 8504 | srcreg1 = translate_rreg (SD_, RM1); |
| 8505 | srcreg2 = translate_rreg (SD_, RM2); |
| 8506 | dstreg1 = translate_rreg (SD_, RN1); |
| 8507 | dstreg2 = translate_rreg (SD_, RN2); |
| 8508 | |
| 8509 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8510 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 8511 | State.regs[dstreg1] = result1; |
| 8512 | } |
| 8513 | |
| 8514 | // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2 |
| 8515 | 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl |
| 8516 | "or_asl" |
| 8517 | *am33 |
| 8518 | *am33_2 |
| 8519 | { |
| 8520 | int srcreg1, dstreg1, dstreg2; |
| 8521 | int result1; |
| 8522 | |
| 8523 | PC = cia; |
| 8524 | srcreg1 = translate_rreg (SD_, RM1); |
| 8525 | dstreg1 = translate_rreg (SD_, RN1); |
| 8526 | dstreg2 = translate_rreg (SD_, RN2); |
| 8527 | |
| 8528 | result1 = State.regs[dstreg1] | State.regs[srcreg1]; |
| 8529 | State.regs[dstreg2] <<= IMM4; |
| 8530 | State.regs[dstreg1] = result1; |
| 8531 | } |
| 8532 | |
| 8533 | // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2 |
| 8534 | 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add |
| 8535 | "sat16_add" |
| 8536 | *am33 |
| 8537 | *am33_2 |
| 8538 | { |
| 8539 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8540 | int result1; |
| 8541 | |
| 8542 | PC = cia; |
| 8543 | srcreg1 = translate_rreg (SD_, RM1); |
| 8544 | srcreg2 = translate_rreg (SD_, RM2); |
| 8545 | dstreg1 = translate_rreg (SD_, RN1); |
| 8546 | dstreg2 = translate_rreg (SD_, RN2); |
| 8547 | |
| 8548 | if (State.regs[srcreg1] >= 0x7fff) |
| 8549 | result1 = 0x7fff; |
| 8550 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8551 | result1 = 0xffff8000; |
| 8552 | else |
| 8553 | result1 = State.regs[srcreg1]; |
| 8554 | |
| 8555 | State.regs[dstreg2] += State.regs[srcreg2]; |
| 8556 | State.regs[dstreg1] = result1; |
| 8557 | } |
| 8558 | |
| 8559 | // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2 |
| 8560 | 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add |
| 8561 | "sat16_add" |
| 8562 | *am33 |
| 8563 | *am33_2 |
| 8564 | { |
| 8565 | int srcreg1, dstreg1, dstreg2; |
| 8566 | int result1; |
| 8567 | |
| 8568 | PC = cia; |
| 8569 | srcreg1 = translate_rreg (SD_, RM1); |
| 8570 | dstreg1 = translate_rreg (SD_, RN1); |
| 8571 | dstreg2 = translate_rreg (SD_, RN2); |
| 8572 | |
| 8573 | if (State.regs[srcreg1] >= 0x7fff) |
| 8574 | result1 = 0x7fff; |
| 8575 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8576 | result1 = 0xffff8000; |
| 8577 | else |
| 8578 | result1 = State.regs[srcreg1]; |
| 8579 | |
| 8580 | State.regs[dstreg2] += EXTEND4 (IMM4); |
| 8581 | State.regs[dstreg1] = result1; |
| 8582 | } |
| 8583 | |
| 8584 | // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2 |
| 8585 | 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub |
| 8586 | "sat16_sub" |
| 8587 | *am33 |
| 8588 | *am33_2 |
| 8589 | { |
| 8590 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8591 | int result1; |
| 8592 | |
| 8593 | PC = cia; |
| 8594 | srcreg1 = translate_rreg (SD_, RM1); |
| 8595 | srcreg2 = translate_rreg (SD_, RM2); |
| 8596 | dstreg1 = translate_rreg (SD_, RN1); |
| 8597 | dstreg2 = translate_rreg (SD_, RN2); |
| 8598 | |
| 8599 | if (State.regs[srcreg1] >= 0x7fff) |
| 8600 | result1 = 0x7fff; |
| 8601 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8602 | result1 = 0xffff8000; |
| 8603 | else |
| 8604 | result1 = State.regs[srcreg1]; |
| 8605 | |
| 8606 | State.regs[dstreg2] -= State.regs[srcreg2]; |
| 8607 | State.regs[dstreg1] = result1; |
| 8608 | } |
| 8609 | |
| 8610 | // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2 |
| 8611 | 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub |
| 8612 | "sat16_sub" |
| 8613 | *am33 |
| 8614 | *am33_2 |
| 8615 | { |
| 8616 | int srcreg1, dstreg1, dstreg2; |
| 8617 | int result1; |
| 8618 | |
| 8619 | PC = cia; |
| 8620 | srcreg1 = translate_rreg (SD_, RM1); |
| 8621 | dstreg1 = translate_rreg (SD_, RN1); |
| 8622 | dstreg2 = translate_rreg (SD_, RN2); |
| 8623 | |
| 8624 | if (State.regs[srcreg1] >= 0x7fff) |
| 8625 | result1 = 0x7fff; |
| 8626 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8627 | result1 = 0xffff8000; |
| 8628 | else |
| 8629 | result1 = State.regs[srcreg1]; |
| 8630 | |
| 8631 | State.regs[dstreg2] -= EXTEND4 (IMM4); |
| 8632 | State.regs[dstreg1] = result1; |
| 8633 | } |
| 8634 | |
| 8635 | // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2 |
| 8636 | 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp |
| 8637 | "sat16_cmp" |
| 8638 | *am33 |
| 8639 | *am33_2 |
| 8640 | { |
| 8641 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8642 | |
| 8643 | PC = cia; |
| 8644 | srcreg1 = translate_rreg (SD_, RM1); |
| 8645 | srcreg2 = translate_rreg (SD_, RM2); |
| 8646 | dstreg1 = translate_rreg (SD_, RN1); |
| 8647 | dstreg2 = translate_rreg (SD_, RN2); |
| 8648 | |
| 8649 | genericCmp (State.regs[dstreg2], State.regs[dstreg1]); |
| 8650 | if (State.regs[srcreg1] >= 0x7fff) |
| 8651 | State.regs[dstreg1] = 0x7fff; |
| 8652 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8653 | State.regs[dstreg1] = 0xffff8000; |
| 8654 | else |
| 8655 | State.regs[dstreg1] = State.regs[srcreg1]; |
| 8656 | } |
| 8657 | |
| 8658 | // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2 |
| 8659 | 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp |
| 8660 | "sat16_cmp" |
| 8661 | *am33 |
| 8662 | *am33_2 |
| 8663 | { |
| 8664 | int srcreg1, dstreg1, dstreg2; |
| 8665 | |
| 8666 | PC = cia; |
| 8667 | srcreg1 = translate_rreg (SD_, RM1); |
| 8668 | dstreg1 = translate_rreg (SD_, RN1); |
| 8669 | dstreg2 = translate_rreg (SD_, RN2); |
| 8670 | |
| 8671 | genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); |
| 8672 | if (State.regs[srcreg1] >= 0x7fff) |
| 8673 | State.regs[dstreg1] = 0x7fff; |
| 8674 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8675 | State.regs[dstreg1] = 0xffff8000; |
| 8676 | else |
| 8677 | State.regs[dstreg1] = State.regs[srcreg1]; |
| 8678 | } |
| 8679 | |
| 8680 | // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2 |
| 8681 | 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov |
| 8682 | "sat16_mov" |
| 8683 | *am33 |
| 8684 | *am33_2 |
| 8685 | { |
| 8686 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8687 | int result1; |
| 8688 | |
| 8689 | PC = cia; |
| 8690 | srcreg1 = translate_rreg (SD_, RM1); |
| 8691 | srcreg2 = translate_rreg (SD_, RM2); |
| 8692 | dstreg1 = translate_rreg (SD_, RN1); |
| 8693 | dstreg2 = translate_rreg (SD_, RN2); |
| 8694 | |
| 8695 | if (State.regs[srcreg1] >= 0x7fff) |
| 8696 | result1 = 0x7fff; |
| 8697 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8698 | result1 = 0xffff8000; |
| 8699 | else |
| 8700 | result1 = State.regs[srcreg1]; |
| 8701 | |
| 8702 | State.regs[dstreg2] = State.regs[srcreg2]; |
| 8703 | State.regs[dstreg1] = result1; |
| 8704 | } |
| 8705 | |
| 8706 | // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2 |
| 8707 | 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov |
| 8708 | "sat16_mov" |
| 8709 | *am33 |
| 8710 | *am33_2 |
| 8711 | { |
| 8712 | int srcreg1, dstreg1, dstreg2; |
| 8713 | int result1; |
| 8714 | |
| 8715 | PC = cia; |
| 8716 | srcreg1 = translate_rreg (SD_, RM1); |
| 8717 | dstreg1 = translate_rreg (SD_, RN1); |
| 8718 | dstreg2 = translate_rreg (SD_, RN2); |
| 8719 | |
| 8720 | if (State.regs[srcreg1] >= 0x7fff) |
| 8721 | result1 = 0x7fff; |
| 8722 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8723 | result1 = 0xffff8000; |
| 8724 | else |
| 8725 | result1 = State.regs[srcreg1]; |
| 8726 | |
| 8727 | State.regs[dstreg2] = EXTEND4 (IMM4); |
| 8728 | State.regs[dstreg1] = result1; |
| 8729 | } |
| 8730 | |
| 8731 | // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2 |
| 8732 | 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr |
| 8733 | "sat16_asr" |
| 8734 | *am33 |
| 8735 | *am33_2 |
| 8736 | { |
| 8737 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8738 | int result1; |
| 8739 | signed int temp; |
| 8740 | |
| 8741 | PC = cia; |
| 8742 | srcreg1 = translate_rreg (SD_, RM1); |
| 8743 | srcreg2 = translate_rreg (SD_, RM2); |
| 8744 | dstreg1 = translate_rreg (SD_, RN1); |
| 8745 | dstreg2 = translate_rreg (SD_, RN2); |
| 8746 | |
| 8747 | if (State.regs[srcreg1] >= 0x7fff) |
| 8748 | result1 = 0x7fff; |
| 8749 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8750 | result1 = 0xffff8000; |
| 8751 | else |
| 8752 | result1 = State.regs[srcreg1]; |
| 8753 | |
| 8754 | temp = State.regs[dstreg2]; |
| 8755 | temp >>= State.regs[srcreg2]; |
| 8756 | State.regs[dstreg2] = temp; |
| 8757 | State.regs[dstreg1] = result1; |
| 8758 | } |
| 8759 | |
| 8760 | // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2 |
| 8761 | 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr |
| 8762 | "sat16_asr" |
| 8763 | *am33 |
| 8764 | *am33_2 |
| 8765 | { |
| 8766 | int srcreg1, dstreg1, dstreg2; |
| 8767 | int result1; |
| 8768 | signed int temp; |
| 8769 | |
| 8770 | PC = cia; |
| 8771 | srcreg1 = translate_rreg (SD_, RM1); |
| 8772 | dstreg1 = translate_rreg (SD_, RN1); |
| 8773 | dstreg2 = translate_rreg (SD_, RN2); |
| 8774 | |
| 8775 | if (State.regs[srcreg1] >= 0x7fff) |
| 8776 | result1 = 0x7fff; |
| 8777 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8778 | result1 = 0xffff8000; |
| 8779 | else |
| 8780 | result1 = State.regs[srcreg1]; |
| 8781 | |
| 8782 | temp = State.regs[dstreg2]; |
| 8783 | temp >>= IMM4; |
| 8784 | State.regs[dstreg2] = temp; |
| 8785 | State.regs[dstreg1] = result1; |
| 8786 | } |
| 8787 | |
| 8788 | // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2 |
| 8789 | 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr |
| 8790 | "sat16_lsr" |
| 8791 | *am33 |
| 8792 | *am33_2 |
| 8793 | { |
| 8794 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8795 | int result1; |
| 8796 | |
| 8797 | PC = cia; |
| 8798 | srcreg1 = translate_rreg (SD_, RM1); |
| 8799 | srcreg2 = translate_rreg (SD_, RM2); |
| 8800 | dstreg1 = translate_rreg (SD_, RN1); |
| 8801 | dstreg2 = translate_rreg (SD_, RN2); |
| 8802 | |
| 8803 | if (State.regs[srcreg1] >= 0x7fff) |
| 8804 | result1 = 0x7fff; |
| 8805 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8806 | result1 = 0xffff8000; |
| 8807 | else |
| 8808 | result1 = State.regs[srcreg1]; |
| 8809 | |
| 8810 | State.regs[dstreg2] >>= State.regs[srcreg2]; |
| 8811 | State.regs[dstreg1] = result1; |
| 8812 | } |
| 8813 | |
| 8814 | // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2 |
| 8815 | 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr |
| 8816 | "sat16_lsr" |
| 8817 | *am33 |
| 8818 | *am33_2 |
| 8819 | { |
| 8820 | int srcreg1, dstreg1, dstreg2; |
| 8821 | int result1; |
| 8822 | |
| 8823 | PC = cia; |
| 8824 | srcreg1 = translate_rreg (SD_, RM1); |
| 8825 | dstreg1 = translate_rreg (SD_, RN1); |
| 8826 | dstreg2 = translate_rreg (SD_, RN2); |
| 8827 | |
| 8828 | if (State.regs[srcreg1] >= 0x7fff) |
| 8829 | result1 = 0x7fff; |
| 8830 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8831 | result1 = 0xffff8000; |
| 8832 | else |
| 8833 | result1 = State.regs[srcreg1]; |
| 8834 | |
| 8835 | State.regs[dstreg2] >>= IMM4; |
| 8836 | State.regs[dstreg1] = result1; |
| 8837 | } |
| 8838 | |
| 8839 | |
| 8840 | // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2 |
| 8841 | 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl |
| 8842 | "sat16_asl" |
| 8843 | *am33 |
| 8844 | *am33_2 |
| 8845 | { |
| 8846 | int srcreg1, srcreg2, dstreg1, dstreg2; |
| 8847 | int result1; |
| 8848 | |
| 8849 | PC = cia; |
| 8850 | srcreg1 = translate_rreg (SD_, RM1); |
| 8851 | srcreg2 = translate_rreg (SD_, RM2); |
| 8852 | dstreg1 = translate_rreg (SD_, RN1); |
| 8853 | dstreg2 = translate_rreg (SD_, RN2); |
| 8854 | |
| 8855 | if (State.regs[srcreg1] >= 0x7fff) |
| 8856 | result1 = 0x7fff; |
| 8857 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8858 | result1 = 0xffff8000; |
| 8859 | else |
| 8860 | result1 = State.regs[srcreg1]; |
| 8861 | |
| 8862 | State.regs[dstreg2] <<= State.regs[srcreg2]; |
| 8863 | State.regs[dstreg1] = result1; |
| 8864 | } |
| 8865 | |
| 8866 | // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2 |
| 8867 | 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl |
| 8868 | "sat16_asl" |
| 8869 | *am33 |
| 8870 | *am33_2 |
| 8871 | { |
| 8872 | int srcreg1, dstreg1, dstreg2; |
| 8873 | int result1; |
| 8874 | |
| 8875 | PC = cia; |
| 8876 | srcreg1 = translate_rreg (SD_, RM1); |
| 8877 | dstreg1 = translate_rreg (SD_, RN1); |
| 8878 | dstreg2 = translate_rreg (SD_, RN2); |
| 8879 | |
| 8880 | if (State.regs[srcreg1] >= 0x7fff) |
| 8881 | result1 = 0x7fff; |
| 8882 | else if (State.regs[srcreg1] <= 0xffff8000) |
| 8883 | result1 = 0xffff8000; |
| 8884 | else |
| 8885 | result1 = State.regs[srcreg1]; |
| 8886 | |
| 8887 | State.regs[dstreg2] <<= IMM4; |
| 8888 | State.regs[dstreg1] = result1; |
| 8889 | } |
| 8890 | |
| 8891 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn |
| 8892 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt |
| 8893 | "mov_llt" |
| 8894 | *am33 |
| 8895 | *am33_2 |
| 8896 | { |
| 8897 | int srcreg, dstreg; |
| 8898 | |
| 8899 | PC = cia; |
| 8900 | srcreg = translate_rreg (SD_, RM); |
| 8901 | dstreg = translate_rreg (SD_, RN); |
| 8902 | |
| 8903 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 8904 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 8905 | |
| 8906 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) |
| 8907 | { |
| 8908 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 8909 | nia = PC; |
| 8910 | } |
| 8911 | } |
| 8912 | |
| 8913 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn |
| 8914 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt |
| 8915 | "mov_lgt" |
| 8916 | *am33 |
| 8917 | *am33_2 |
| 8918 | { |
| 8919 | int srcreg, dstreg; |
| 8920 | |
| 8921 | PC = cia; |
| 8922 | srcreg = translate_rreg (SD_, RM); |
| 8923 | dstreg = translate_rreg (SD_, RN); |
| 8924 | |
| 8925 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 8926 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 8927 | |
| 8928 | if (!((PSW & PSW_Z) |
| 8929 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) |
| 8930 | { |
| 8931 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 8932 | nia = PC; |
| 8933 | } |
| 8934 | } |
| 8935 | |
| 8936 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn |
| 8937 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge |
| 8938 | "mov_lge" |
| 8939 | *am33 |
| 8940 | *am33_2 |
| 8941 | { |
| 8942 | int srcreg, dstreg; |
| 8943 | |
| 8944 | PC = cia; |
| 8945 | srcreg = translate_rreg (SD_, RM); |
| 8946 | dstreg = translate_rreg (SD_, RN); |
| 8947 | |
| 8948 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 8949 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 8950 | |
| 8951 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) |
| 8952 | { |
| 8953 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 8954 | nia = PC; |
| 8955 | } |
| 8956 | } |
| 8957 | |
| 8958 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn |
| 8959 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle |
| 8960 | "mov_lle" |
| 8961 | *am33 |
| 8962 | *am33_2 |
| 8963 | { |
| 8964 | int srcreg, dstreg; |
| 8965 | |
| 8966 | PC = cia; |
| 8967 | srcreg = translate_rreg (SD_, RM); |
| 8968 | dstreg = translate_rreg (SD_, RN); |
| 8969 | |
| 8970 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 8971 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 8972 | |
| 8973 | if ((PSW & PSW_Z) |
| 8974 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) |
| 8975 | { |
| 8976 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 8977 | nia = PC; |
| 8978 | } |
| 8979 | } |
| 8980 | |
| 8981 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn |
| 8982 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs |
| 8983 | "mov_lcs" |
| 8984 | *am33 |
| 8985 | *am33_2 |
| 8986 | { |
| 8987 | int srcreg, dstreg; |
| 8988 | |
| 8989 | PC = cia; |
| 8990 | srcreg = translate_rreg (SD_, RM); |
| 8991 | dstreg = translate_rreg (SD_, RN); |
| 8992 | |
| 8993 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 8994 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 8995 | |
| 8996 | if (PSW & PSW_C) |
| 8997 | { |
| 8998 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 8999 | nia = PC; |
| 9000 | } |
| 9001 | } |
| 9002 | |
| 9003 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn |
| 9004 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi |
| 9005 | "mov_lhi" |
| 9006 | *am33 |
| 9007 | *am33_2 |
| 9008 | { |
| 9009 | int srcreg, dstreg; |
| 9010 | |
| 9011 | PC = cia; |
| 9012 | srcreg = translate_rreg (SD_, RM); |
| 9013 | dstreg = translate_rreg (SD_, RN); |
| 9014 | |
| 9015 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 9016 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 9017 | |
| 9018 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) |
| 9019 | { |
| 9020 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 9021 | nia = PC; |
| 9022 | } |
| 9023 | } |
| 9024 | |
| 9025 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn |
| 9026 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc |
| 9027 | "mov_lcc" |
| 9028 | *am33 |
| 9029 | *am33_2 |
| 9030 | { |
| 9031 | int srcreg, dstreg; |
| 9032 | |
| 9033 | PC = cia; |
| 9034 | srcreg = translate_rreg (SD_, RM); |
| 9035 | dstreg = translate_rreg (SD_, RN); |
| 9036 | |
| 9037 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 9038 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 9039 | |
| 9040 | if (!(PSW & PSW_C)) |
| 9041 | { |
| 9042 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 9043 | nia = PC; |
| 9044 | } |
| 9045 | } |
| 9046 | |
| 9047 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn |
| 9048 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls |
| 9049 | "mov_lls" |
| 9050 | *am33 |
| 9051 | *am33_2 |
| 9052 | { |
| 9053 | int srcreg, dstreg; |
| 9054 | |
| 9055 | PC = cia; |
| 9056 | srcreg = translate_rreg (SD_, RM); |
| 9057 | dstreg = translate_rreg (SD_, RN); |
| 9058 | |
| 9059 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 9060 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 9061 | |
| 9062 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) |
| 9063 | { |
| 9064 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 9065 | nia = PC; |
| 9066 | } |
| 9067 | } |
| 9068 | |
| 9069 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn |
| 9070 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq |
| 9071 | "mov_leq" |
| 9072 | *am33 |
| 9073 | *am33_2 |
| 9074 | { |
| 9075 | int srcreg, dstreg; |
| 9076 | |
| 9077 | PC = cia; |
| 9078 | srcreg = translate_rreg (SD_, RM); |
| 9079 | dstreg = translate_rreg (SD_, RN); |
| 9080 | |
| 9081 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 9082 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 9083 | |
| 9084 | if (PSW & PSW_Z) |
| 9085 | { |
| 9086 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 9087 | nia = PC; |
| 9088 | } |
| 9089 | } |
| 9090 | |
| 9091 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn |
| 9092 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne |
| 9093 | "mov_lne" |
| 9094 | *am33 |
| 9095 | *am33_2 |
| 9096 | { |
| 9097 | int srcreg, dstreg; |
| 9098 | |
| 9099 | PC = cia; |
| 9100 | srcreg = translate_rreg (SD_, RM); |
| 9101 | dstreg = translate_rreg (SD_, RN); |
| 9102 | |
| 9103 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 9104 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 9105 | |
| 9106 | if (!(PSW & PSW_Z)) |
| 9107 | { |
| 9108 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 9109 | nia = PC; |
| 9110 | } |
| 9111 | } |
| 9112 | |
| 9113 | // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn |
| 9114 | 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra |
| 9115 | "mov_lra" |
| 9116 | *am33 |
| 9117 | *am33_2 |
| 9118 | { |
| 9119 | int srcreg, dstreg; |
| 9120 | |
| 9121 | PC = cia; |
| 9122 | srcreg = translate_rreg (SD_, RM); |
| 9123 | dstreg = translate_rreg (SD_, RN); |
| 9124 | |
| 9125 | State.regs[dstreg] = load_word (State.regs[srcreg]); |
| 9126 | State.regs[srcreg] += EXTEND4 (IMM4); |
| 9127 | |
| 9128 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; |
| 9129 | nia = PC; |
| 9130 | } |
| 9131 | |
| 9132 | :include::am33_2:am33-2.igen |