| 1 | /* Simulator instruction semantics for or1k32bf. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright (C) 1996-2021 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU simulators. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #ifdef DEFINE_LABELS |
| 26 | |
| 27 | /* The labels have the case they have because the enum of insn types |
| 28 | is all uppercase and in the non-stdc case the insn symbol is built |
| 29 | into the enum name. */ |
| 30 | |
| 31 | static struct { |
| 32 | int index; |
| 33 | void *label; |
| 34 | } labels[] = { |
| 35 | { OR1K32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, |
| 36 | { OR1K32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, |
| 37 | { OR1K32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, |
| 38 | { OR1K32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, |
| 39 | { OR1K32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, |
| 40 | { OR1K32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, |
| 41 | { OR1K32BF_INSN_L_J, && case_sem_INSN_L_J }, |
| 42 | { OR1K32BF_INSN_L_ADRP, && case_sem_INSN_L_ADRP }, |
| 43 | { OR1K32BF_INSN_L_JAL, && case_sem_INSN_L_JAL }, |
| 44 | { OR1K32BF_INSN_L_JR, && case_sem_INSN_L_JR }, |
| 45 | { OR1K32BF_INSN_L_JALR, && case_sem_INSN_L_JALR }, |
| 46 | { OR1K32BF_INSN_L_BNF, && case_sem_INSN_L_BNF }, |
| 47 | { OR1K32BF_INSN_L_BF, && case_sem_INSN_L_BF }, |
| 48 | { OR1K32BF_INSN_L_TRAP, && case_sem_INSN_L_TRAP }, |
| 49 | { OR1K32BF_INSN_L_SYS, && case_sem_INSN_L_SYS }, |
| 50 | { OR1K32BF_INSN_L_MSYNC, && case_sem_INSN_L_MSYNC }, |
| 51 | { OR1K32BF_INSN_L_PSYNC, && case_sem_INSN_L_PSYNC }, |
| 52 | { OR1K32BF_INSN_L_CSYNC, && case_sem_INSN_L_CSYNC }, |
| 53 | { OR1K32BF_INSN_L_RFE, && case_sem_INSN_L_RFE }, |
| 54 | { OR1K32BF_INSN_L_NOP_IMM, && case_sem_INSN_L_NOP_IMM }, |
| 55 | { OR1K32BF_INSN_L_MOVHI, && case_sem_INSN_L_MOVHI }, |
| 56 | { OR1K32BF_INSN_L_MACRC, && case_sem_INSN_L_MACRC }, |
| 57 | { OR1K32BF_INSN_L_MFSPR, && case_sem_INSN_L_MFSPR }, |
| 58 | { OR1K32BF_INSN_L_MTSPR, && case_sem_INSN_L_MTSPR }, |
| 59 | { OR1K32BF_INSN_L_LWZ, && case_sem_INSN_L_LWZ }, |
| 60 | { OR1K32BF_INSN_L_LWS, && case_sem_INSN_L_LWS }, |
| 61 | { OR1K32BF_INSN_L_LWA, && case_sem_INSN_L_LWA }, |
| 62 | { OR1K32BF_INSN_L_LBZ, && case_sem_INSN_L_LBZ }, |
| 63 | { OR1K32BF_INSN_L_LBS, && case_sem_INSN_L_LBS }, |
| 64 | { OR1K32BF_INSN_L_LHZ, && case_sem_INSN_L_LHZ }, |
| 65 | { OR1K32BF_INSN_L_LHS, && case_sem_INSN_L_LHS }, |
| 66 | { OR1K32BF_INSN_L_SW, && case_sem_INSN_L_SW }, |
| 67 | { OR1K32BF_INSN_L_SB, && case_sem_INSN_L_SB }, |
| 68 | { OR1K32BF_INSN_L_SH, && case_sem_INSN_L_SH }, |
| 69 | { OR1K32BF_INSN_L_SWA, && case_sem_INSN_L_SWA }, |
| 70 | { OR1K32BF_INSN_L_SLL, && case_sem_INSN_L_SLL }, |
| 71 | { OR1K32BF_INSN_L_SLLI, && case_sem_INSN_L_SLLI }, |
| 72 | { OR1K32BF_INSN_L_SRL, && case_sem_INSN_L_SRL }, |
| 73 | { OR1K32BF_INSN_L_SRLI, && case_sem_INSN_L_SRLI }, |
| 74 | { OR1K32BF_INSN_L_SRA, && case_sem_INSN_L_SRA }, |
| 75 | { OR1K32BF_INSN_L_SRAI, && case_sem_INSN_L_SRAI }, |
| 76 | { OR1K32BF_INSN_L_ROR, && case_sem_INSN_L_ROR }, |
| 77 | { OR1K32BF_INSN_L_RORI, && case_sem_INSN_L_RORI }, |
| 78 | { OR1K32BF_INSN_L_AND, && case_sem_INSN_L_AND }, |
| 79 | { OR1K32BF_INSN_L_OR, && case_sem_INSN_L_OR }, |
| 80 | { OR1K32BF_INSN_L_XOR, && case_sem_INSN_L_XOR }, |
| 81 | { OR1K32BF_INSN_L_ADD, && case_sem_INSN_L_ADD }, |
| 82 | { OR1K32BF_INSN_L_SUB, && case_sem_INSN_L_SUB }, |
| 83 | { OR1K32BF_INSN_L_ADDC, && case_sem_INSN_L_ADDC }, |
| 84 | { OR1K32BF_INSN_L_MUL, && case_sem_INSN_L_MUL }, |
| 85 | { OR1K32BF_INSN_L_MULD, && case_sem_INSN_L_MULD }, |
| 86 | { OR1K32BF_INSN_L_MULU, && case_sem_INSN_L_MULU }, |
| 87 | { OR1K32BF_INSN_L_MULDU, && case_sem_INSN_L_MULDU }, |
| 88 | { OR1K32BF_INSN_L_DIV, && case_sem_INSN_L_DIV }, |
| 89 | { OR1K32BF_INSN_L_DIVU, && case_sem_INSN_L_DIVU }, |
| 90 | { OR1K32BF_INSN_L_FF1, && case_sem_INSN_L_FF1 }, |
| 91 | { OR1K32BF_INSN_L_FL1, && case_sem_INSN_L_FL1 }, |
| 92 | { OR1K32BF_INSN_L_ANDI, && case_sem_INSN_L_ANDI }, |
| 93 | { OR1K32BF_INSN_L_ORI, && case_sem_INSN_L_ORI }, |
| 94 | { OR1K32BF_INSN_L_XORI, && case_sem_INSN_L_XORI }, |
| 95 | { OR1K32BF_INSN_L_ADDI, && case_sem_INSN_L_ADDI }, |
| 96 | { OR1K32BF_INSN_L_ADDIC, && case_sem_INSN_L_ADDIC }, |
| 97 | { OR1K32BF_INSN_L_MULI, && case_sem_INSN_L_MULI }, |
| 98 | { OR1K32BF_INSN_L_EXTHS, && case_sem_INSN_L_EXTHS }, |
| 99 | { OR1K32BF_INSN_L_EXTBS, && case_sem_INSN_L_EXTBS }, |
| 100 | { OR1K32BF_INSN_L_EXTHZ, && case_sem_INSN_L_EXTHZ }, |
| 101 | { OR1K32BF_INSN_L_EXTBZ, && case_sem_INSN_L_EXTBZ }, |
| 102 | { OR1K32BF_INSN_L_EXTWS, && case_sem_INSN_L_EXTWS }, |
| 103 | { OR1K32BF_INSN_L_EXTWZ, && case_sem_INSN_L_EXTWZ }, |
| 104 | { OR1K32BF_INSN_L_CMOV, && case_sem_INSN_L_CMOV }, |
| 105 | { OR1K32BF_INSN_L_SFGTS, && case_sem_INSN_L_SFGTS }, |
| 106 | { OR1K32BF_INSN_L_SFGTSI, && case_sem_INSN_L_SFGTSI }, |
| 107 | { OR1K32BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU }, |
| 108 | { OR1K32BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI }, |
| 109 | { OR1K32BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES }, |
| 110 | { OR1K32BF_INSN_L_SFGESI, && case_sem_INSN_L_SFGESI }, |
| 111 | { OR1K32BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU }, |
| 112 | { OR1K32BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI }, |
| 113 | { OR1K32BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS }, |
| 114 | { OR1K32BF_INSN_L_SFLTSI, && case_sem_INSN_L_SFLTSI }, |
| 115 | { OR1K32BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU }, |
| 116 | { OR1K32BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI }, |
| 117 | { OR1K32BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES }, |
| 118 | { OR1K32BF_INSN_L_SFLESI, && case_sem_INSN_L_SFLESI }, |
| 119 | { OR1K32BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU }, |
| 120 | { OR1K32BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI }, |
| 121 | { OR1K32BF_INSN_L_SFEQ, && case_sem_INSN_L_SFEQ }, |
| 122 | { OR1K32BF_INSN_L_SFEQI, && case_sem_INSN_L_SFEQI }, |
| 123 | { OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE }, |
| 124 | { OR1K32BF_INSN_L_SFNEI, && case_sem_INSN_L_SFNEI }, |
| 125 | { OR1K32BF_INSN_L_MAC, && case_sem_INSN_L_MAC }, |
| 126 | { OR1K32BF_INSN_L_MACI, && case_sem_INSN_L_MACI }, |
| 127 | { OR1K32BF_INSN_L_MACU, && case_sem_INSN_L_MACU }, |
| 128 | { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB }, |
| 129 | { OR1K32BF_INSN_L_MSBU, && case_sem_INSN_L_MSBU }, |
| 130 | { OR1K32BF_INSN_L_CUST1, && case_sem_INSN_L_CUST1 }, |
| 131 | { OR1K32BF_INSN_L_CUST2, && case_sem_INSN_L_CUST2 }, |
| 132 | { OR1K32BF_INSN_L_CUST3, && case_sem_INSN_L_CUST3 }, |
| 133 | { OR1K32BF_INSN_L_CUST4, && case_sem_INSN_L_CUST4 }, |
| 134 | { OR1K32BF_INSN_L_CUST5, && case_sem_INSN_L_CUST5 }, |
| 135 | { OR1K32BF_INSN_L_CUST6, && case_sem_INSN_L_CUST6 }, |
| 136 | { OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 }, |
| 137 | { OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 }, |
| 138 | { OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S }, |
| 139 | { OR1K32BF_INSN_LF_ADD_D32, && case_sem_INSN_LF_ADD_D32 }, |
| 140 | { OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S }, |
| 141 | { OR1K32BF_INSN_LF_SUB_D32, && case_sem_INSN_LF_SUB_D32 }, |
| 142 | { OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S }, |
| 143 | { OR1K32BF_INSN_LF_MUL_D32, && case_sem_INSN_LF_MUL_D32 }, |
| 144 | { OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S }, |
| 145 | { OR1K32BF_INSN_LF_DIV_D32, && case_sem_INSN_LF_DIV_D32 }, |
| 146 | { OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S }, |
| 147 | { OR1K32BF_INSN_LF_REM_D32, && case_sem_INSN_LF_REM_D32 }, |
| 148 | { OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S }, |
| 149 | { OR1K32BF_INSN_LF_ITOF_D32, && case_sem_INSN_LF_ITOF_D32 }, |
| 150 | { OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S }, |
| 151 | { OR1K32BF_INSN_LF_FTOI_D32, && case_sem_INSN_LF_FTOI_D32 }, |
| 152 | { OR1K32BF_INSN_LF_SFEQ_S, && case_sem_INSN_LF_SFEQ_S }, |
| 153 | { OR1K32BF_INSN_LF_SFEQ_D32, && case_sem_INSN_LF_SFEQ_D32 }, |
| 154 | { OR1K32BF_INSN_LF_SFNE_S, && case_sem_INSN_LF_SFNE_S }, |
| 155 | { OR1K32BF_INSN_LF_SFNE_D32, && case_sem_INSN_LF_SFNE_D32 }, |
| 156 | { OR1K32BF_INSN_LF_SFGE_S, && case_sem_INSN_LF_SFGE_S }, |
| 157 | { OR1K32BF_INSN_LF_SFGE_D32, && case_sem_INSN_LF_SFGE_D32 }, |
| 158 | { OR1K32BF_INSN_LF_SFGT_S, && case_sem_INSN_LF_SFGT_S }, |
| 159 | { OR1K32BF_INSN_LF_SFGT_D32, && case_sem_INSN_LF_SFGT_D32 }, |
| 160 | { OR1K32BF_INSN_LF_SFLT_S, && case_sem_INSN_LF_SFLT_S }, |
| 161 | { OR1K32BF_INSN_LF_SFLT_D32, && case_sem_INSN_LF_SFLT_D32 }, |
| 162 | { OR1K32BF_INSN_LF_SFLE_S, && case_sem_INSN_LF_SFLE_S }, |
| 163 | { OR1K32BF_INSN_LF_SFLE_D32, && case_sem_INSN_LF_SFLE_D32 }, |
| 164 | { OR1K32BF_INSN_LF_SFUEQ_S, && case_sem_INSN_LF_SFUEQ_S }, |
| 165 | { OR1K32BF_INSN_LF_SFUEQ_D32, && case_sem_INSN_LF_SFUEQ_D32 }, |
| 166 | { OR1K32BF_INSN_LF_SFUNE_S, && case_sem_INSN_LF_SFUNE_S }, |
| 167 | { OR1K32BF_INSN_LF_SFUNE_D32, && case_sem_INSN_LF_SFUNE_D32 }, |
| 168 | { OR1K32BF_INSN_LF_SFUGT_S, && case_sem_INSN_LF_SFUGT_S }, |
| 169 | { OR1K32BF_INSN_LF_SFUGT_D32, && case_sem_INSN_LF_SFUGT_D32 }, |
| 170 | { OR1K32BF_INSN_LF_SFUGE_S, && case_sem_INSN_LF_SFUGE_S }, |
| 171 | { OR1K32BF_INSN_LF_SFUGE_D32, && case_sem_INSN_LF_SFUGE_D32 }, |
| 172 | { OR1K32BF_INSN_LF_SFULT_S, && case_sem_INSN_LF_SFULT_S }, |
| 173 | { OR1K32BF_INSN_LF_SFULT_D32, && case_sem_INSN_LF_SFULT_D32 }, |
| 174 | { OR1K32BF_INSN_LF_SFULE_S, && case_sem_INSN_LF_SFULE_S }, |
| 175 | { OR1K32BF_INSN_LF_SFULE_D32, && case_sem_INSN_LF_SFULE_D32 }, |
| 176 | { OR1K32BF_INSN_LF_SFUN_S, && case_sem_INSN_LF_SFUN_S }, |
| 177 | { OR1K32BF_INSN_LF_SFUN_D32, && case_sem_INSN_LF_SFUN_D32 }, |
| 178 | { OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S }, |
| 179 | { OR1K32BF_INSN_LF_MADD_D32, && case_sem_INSN_LF_MADD_D32 }, |
| 180 | { OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S }, |
| 181 | { OR1K32BF_INSN_LF_CUST1_D32, && case_sem_INSN_LF_CUST1_D32 }, |
| 182 | { 0, 0 } |
| 183 | }; |
| 184 | int i; |
| 185 | |
| 186 | for (i = 0; labels[i].label != 0; ++i) |
| 187 | { |
| 188 | #if FAST_P |
| 189 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; |
| 190 | #else |
| 191 | CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; |
| 192 | #endif |
| 193 | } |
| 194 | |
| 195 | #undef DEFINE_LABELS |
| 196 | #endif /* DEFINE_LABELS */ |
| 197 | |
| 198 | #ifdef DEFINE_SWITCH |
| 199 | |
| 200 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn |
| 201 | off frills like tracing and profiling. */ |
| 202 | /* FIXME: A better way would be to have TRACE_RESULT check for something |
| 203 | that can cause it to be optimized out. Another way would be to emit |
| 204 | special handlers into the instruction "stream". */ |
| 205 | |
| 206 | #if FAST_P |
| 207 | #undef CGEN_TRACE_RESULT |
| 208 | #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) |
| 209 | #endif |
| 210 | |
| 211 | #undef GET_ATTR |
| 212 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) |
| 213 | |
| 214 | { |
| 215 | |
| 216 | #if WITH_SCACHE_PBB |
| 217 | |
| 218 | /* Branch to next handler without going around main loop. */ |
| 219 | #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case |
| 220 | SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) |
| 221 | |
| 222 | #else /* ! WITH_SCACHE_PBB */ |
| 223 | |
| 224 | #define NEXT(vpc) BREAK (sem) |
| 225 | #ifdef __GNUC__ |
| 226 | #if FAST_P |
| 227 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) |
| 228 | #else |
| 229 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) |
| 230 | #endif |
| 231 | #else |
| 232 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) |
| 233 | #endif |
| 234 | |
| 235 | #endif /* ! WITH_SCACHE_PBB */ |
| 236 | |
| 237 | { |
| 238 | |
| 239 | CASE (sem, INSN_X_INVALID) : /* --invalid-- */ |
| 240 | { |
| 241 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 242 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 243 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 244 | int UNUSED written = 0; |
| 245 | IADDR UNUSED pc = abuf->addr; |
| 246 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 247 | |
| 248 | { |
| 249 | /* Update the recorded pc in the cpu state struct. |
| 250 | Only necessary for WITH_SCACHE case, but to avoid the |
| 251 | conditional compilation .... */ |
| 252 | SET_H_PC (pc); |
| 253 | /* Virtual insns have zero size. Overwrite vpc with address of next insn |
| 254 | using the default-insn-bitsize spec. When executing insns in parallel |
| 255 | we may want to queue the fault and continue execution. */ |
| 256 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 257 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); |
| 258 | } |
| 259 | |
| 260 | #undef FLD |
| 261 | } |
| 262 | NEXT (vpc); |
| 263 | |
| 264 | CASE (sem, INSN_X_AFTER) : /* --after-- */ |
| 265 | { |
| 266 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 267 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 268 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 269 | int UNUSED written = 0; |
| 270 | IADDR UNUSED pc = abuf->addr; |
| 271 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 272 | |
| 273 | { |
| 274 | #if WITH_SCACHE_PBB_OR1K32BF |
| 275 | or1k32bf_pbb_after (current_cpu, sem_arg); |
| 276 | #endif |
| 277 | } |
| 278 | |
| 279 | #undef FLD |
| 280 | } |
| 281 | NEXT (vpc); |
| 282 | |
| 283 | CASE (sem, INSN_X_BEFORE) : /* --before-- */ |
| 284 | { |
| 285 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 286 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 287 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 288 | int UNUSED written = 0; |
| 289 | IADDR UNUSED pc = abuf->addr; |
| 290 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 291 | |
| 292 | { |
| 293 | #if WITH_SCACHE_PBB_OR1K32BF |
| 294 | or1k32bf_pbb_before (current_cpu, sem_arg); |
| 295 | #endif |
| 296 | } |
| 297 | |
| 298 | #undef FLD |
| 299 | } |
| 300 | NEXT (vpc); |
| 301 | |
| 302 | CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ |
| 303 | { |
| 304 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 305 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 306 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 307 | int UNUSED written = 0; |
| 308 | IADDR UNUSED pc = abuf->addr; |
| 309 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 310 | |
| 311 | { |
| 312 | #if WITH_SCACHE_PBB_OR1K32BF |
| 313 | #ifdef DEFINE_SWITCH |
| 314 | vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg, |
| 315 | pbb_br_type, pbb_br_npc); |
| 316 | BREAK (sem); |
| 317 | #else |
| 318 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ |
| 319 | vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg, |
| 320 | CPU_PBB_BR_TYPE (current_cpu), |
| 321 | CPU_PBB_BR_NPC (current_cpu)); |
| 322 | #endif |
| 323 | #endif |
| 324 | } |
| 325 | |
| 326 | #undef FLD |
| 327 | } |
| 328 | NEXT (vpc); |
| 329 | |
| 330 | CASE (sem, INSN_X_CHAIN) : /* --chain-- */ |
| 331 | { |
| 332 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 333 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 334 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 335 | int UNUSED written = 0; |
| 336 | IADDR UNUSED pc = abuf->addr; |
| 337 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 338 | |
| 339 | { |
| 340 | #if WITH_SCACHE_PBB_OR1K32BF |
| 341 | vpc = or1k32bf_pbb_chain (current_cpu, sem_arg); |
| 342 | #ifdef DEFINE_SWITCH |
| 343 | BREAK (sem); |
| 344 | #endif |
| 345 | #endif |
| 346 | } |
| 347 | |
| 348 | #undef FLD |
| 349 | } |
| 350 | NEXT (vpc); |
| 351 | |
| 352 | CASE (sem, INSN_X_BEGIN) : /* --begin-- */ |
| 353 | { |
| 354 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 355 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 356 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 357 | int UNUSED written = 0; |
| 358 | IADDR UNUSED pc = abuf->addr; |
| 359 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 360 | |
| 361 | { |
| 362 | #if WITH_SCACHE_PBB_OR1K32BF |
| 363 | #if defined DEFINE_SWITCH || defined FAST_P |
| 364 | /* In the switch case FAST_P is a constant, allowing several optimizations |
| 365 | in any called inline functions. */ |
| 366 | vpc = or1k32bf_pbb_begin (current_cpu, FAST_P); |
| 367 | #else |
| 368 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ |
| 369 | vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); |
| 370 | #else |
| 371 | vpc = or1k32bf_pbb_begin (current_cpu, 0); |
| 372 | #endif |
| 373 | #endif |
| 374 | #endif |
| 375 | } |
| 376 | |
| 377 | #undef FLD |
| 378 | } |
| 379 | NEXT (vpc); |
| 380 | |
| 381 | CASE (sem, INSN_L_J) : /* l.j ${disp26} */ |
| 382 | { |
| 383 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 384 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 385 | #define FLD(f) abuf->fields.sfmt_l_j.f |
| 386 | int UNUSED written = 0; |
| 387 | IADDR UNUSED pc = abuf->addr; |
| 388 | SEM_BRANCH_INIT |
| 389 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 390 | |
| 391 | { |
| 392 | { |
| 393 | { |
| 394 | USI opval = FLD (i_disp26); |
| 395 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 396 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 397 | } |
| 398 | } |
| 399 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 400 | if (1) |
| 401 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | SEM_BRANCH_FINI (vpc); |
| 406 | #undef FLD |
| 407 | } |
| 408 | NEXT (vpc); |
| 409 | |
| 410 | CASE (sem, INSN_L_ADRP) : /* l.adrp $rD,${disp21} */ |
| 411 | { |
| 412 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 413 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 414 | #define FLD(f) abuf->fields.sfmt_l_adrp.f |
| 415 | int UNUSED written = 0; |
| 416 | IADDR UNUSED pc = abuf->addr; |
| 417 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 418 | |
| 419 | { |
| 420 | USI opval = FLD (i_disp21); |
| 421 | SET_H_GPR (FLD (f_r1), opval); |
| 422 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 423 | } |
| 424 | |
| 425 | #undef FLD |
| 426 | } |
| 427 | NEXT (vpc); |
| 428 | |
| 429 | CASE (sem, INSN_L_JAL) : /* l.jal ${disp26} */ |
| 430 | { |
| 431 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 432 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 433 | #define FLD(f) abuf->fields.sfmt_l_j.f |
| 434 | int UNUSED written = 0; |
| 435 | IADDR UNUSED pc = abuf->addr; |
| 436 | SEM_BRANCH_INIT |
| 437 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 438 | |
| 439 | { |
| 440 | { |
| 441 | USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8))); |
| 442 | SET_H_GPR (((UINT) 9), opval); |
| 443 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 444 | } |
| 445 | { |
| 446 | { |
| 447 | { |
| 448 | USI opval = FLD (i_disp26); |
| 449 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 450 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 451 | } |
| 452 | } |
| 453 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 454 | if (1) |
| 455 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); |
| 456 | } |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | SEM_BRANCH_FINI (vpc); |
| 461 | #undef FLD |
| 462 | } |
| 463 | NEXT (vpc); |
| 464 | |
| 465 | CASE (sem, INSN_L_JR) : /* l.jr $rB */ |
| 466 | { |
| 467 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 468 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 469 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 470 | int UNUSED written = 0; |
| 471 | IADDR UNUSED pc = abuf->addr; |
| 472 | SEM_BRANCH_INIT |
| 473 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 474 | |
| 475 | { |
| 476 | { |
| 477 | { |
| 478 | USI opval = GET_H_GPR (FLD (f_r3)); |
| 479 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 480 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 481 | } |
| 482 | } |
| 483 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 484 | if (1) |
| 485 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | SEM_BRANCH_FINI (vpc); |
| 490 | #undef FLD |
| 491 | } |
| 492 | NEXT (vpc); |
| 493 | |
| 494 | CASE (sem, INSN_L_JALR) : /* l.jalr $rB */ |
| 495 | { |
| 496 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 497 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 498 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 499 | int UNUSED written = 0; |
| 500 | IADDR UNUSED pc = abuf->addr; |
| 501 | SEM_BRANCH_INIT |
| 502 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 503 | |
| 504 | { |
| 505 | { |
| 506 | USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8))); |
| 507 | SET_H_GPR (((UINT) 9), opval); |
| 508 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 509 | } |
| 510 | { |
| 511 | { |
| 512 | { |
| 513 | USI opval = GET_H_GPR (FLD (f_r3)); |
| 514 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 515 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 516 | } |
| 517 | } |
| 518 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 519 | if (1) |
| 520 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); |
| 521 | } |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | SEM_BRANCH_FINI (vpc); |
| 526 | #undef FLD |
| 527 | } |
| 528 | NEXT (vpc); |
| 529 | |
| 530 | CASE (sem, INSN_L_BNF) : /* l.bnf ${disp26} */ |
| 531 | { |
| 532 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 533 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 534 | #define FLD(f) abuf->fields.sfmt_l_j.f |
| 535 | int UNUSED written = 0; |
| 536 | IADDR UNUSED pc = abuf->addr; |
| 537 | SEM_BRANCH_INIT |
| 538 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 539 | |
| 540 | { |
| 541 | if (NOTSI (GET_H_SYS_SR_F ())) { |
| 542 | { |
| 543 | { |
| 544 | USI opval = FLD (i_disp26); |
| 545 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 546 | written |= (1 << 4); |
| 547 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 548 | } |
| 549 | } |
| 550 | } else { |
| 551 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 552 | { |
| 553 | { |
| 554 | USI opval = ADDSI (pc, 4); |
| 555 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 556 | written |= (1 << 4); |
| 557 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 558 | } |
| 559 | } |
| 560 | } |
| 561 | } |
| 562 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 563 | if (1) |
| 564 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); |
| 565 | } |
| 566 | } |
| 567 | |
| 568 | abuf->written = written; |
| 569 | SEM_BRANCH_FINI (vpc); |
| 570 | #undef FLD |
| 571 | } |
| 572 | NEXT (vpc); |
| 573 | |
| 574 | CASE (sem, INSN_L_BF) : /* l.bf ${disp26} */ |
| 575 | { |
| 576 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 577 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 578 | #define FLD(f) abuf->fields.sfmt_l_j.f |
| 579 | int UNUSED written = 0; |
| 580 | IADDR UNUSED pc = abuf->addr; |
| 581 | SEM_BRANCH_INIT |
| 582 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 583 | |
| 584 | { |
| 585 | if (GET_H_SYS_SR_F ()) { |
| 586 | { |
| 587 | { |
| 588 | USI opval = FLD (i_disp26); |
| 589 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 590 | written |= (1 << 4); |
| 591 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 592 | } |
| 593 | } |
| 594 | } else { |
| 595 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 596 | { |
| 597 | { |
| 598 | USI opval = ADDSI (pc, 4); |
| 599 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 600 | written |= (1 << 4); |
| 601 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); |
| 602 | } |
| 603 | } |
| 604 | } |
| 605 | } |
| 606 | if (GET_H_SYS_CPUCFGR_ND ()) { |
| 607 | if (1) |
| 608 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); |
| 609 | } |
| 610 | } |
| 611 | |
| 612 | abuf->written = written; |
| 613 | SEM_BRANCH_FINI (vpc); |
| 614 | #undef FLD |
| 615 | } |
| 616 | NEXT (vpc); |
| 617 | |
| 618 | CASE (sem, INSN_L_TRAP) : /* l.trap ${uimm16} */ |
| 619 | { |
| 620 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 621 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 622 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 623 | int UNUSED written = 0; |
| 624 | IADDR UNUSED pc = abuf->addr; |
| 625 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 626 | |
| 627 | or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP); |
| 628 | |
| 629 | #undef FLD |
| 630 | } |
| 631 | NEXT (vpc); |
| 632 | |
| 633 | CASE (sem, INSN_L_SYS) : /* l.sys ${uimm16} */ |
| 634 | { |
| 635 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 636 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 637 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 638 | int UNUSED written = 0; |
| 639 | IADDR UNUSED pc = abuf->addr; |
| 640 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 641 | |
| 642 | or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL); |
| 643 | |
| 644 | #undef FLD |
| 645 | } |
| 646 | NEXT (vpc); |
| 647 | |
| 648 | CASE (sem, INSN_L_MSYNC) : /* l.msync */ |
| 649 | { |
| 650 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 651 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 652 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 653 | int UNUSED written = 0; |
| 654 | IADDR UNUSED pc = abuf->addr; |
| 655 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 656 | |
| 657 | ((void) 0); /*nop*/ |
| 658 | |
| 659 | #undef FLD |
| 660 | } |
| 661 | NEXT (vpc); |
| 662 | |
| 663 | CASE (sem, INSN_L_PSYNC) : /* l.psync */ |
| 664 | { |
| 665 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 666 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 667 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 668 | int UNUSED written = 0; |
| 669 | IADDR UNUSED pc = abuf->addr; |
| 670 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 671 | |
| 672 | ((void) 0); /*nop*/ |
| 673 | |
| 674 | #undef FLD |
| 675 | } |
| 676 | NEXT (vpc); |
| 677 | |
| 678 | CASE (sem, INSN_L_CSYNC) : /* l.csync */ |
| 679 | { |
| 680 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 681 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 682 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 683 | int UNUSED written = 0; |
| 684 | IADDR UNUSED pc = abuf->addr; |
| 685 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 686 | |
| 687 | ((void) 0); /*nop*/ |
| 688 | |
| 689 | #undef FLD |
| 690 | } |
| 691 | NEXT (vpc); |
| 692 | |
| 693 | CASE (sem, INSN_L_RFE) : /* l.rfe */ |
| 694 | { |
| 695 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 696 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 697 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 698 | int UNUSED written = 0; |
| 699 | IADDR UNUSED pc = abuf->addr; |
| 700 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 701 | |
| 702 | or1k32bf_rfe (current_cpu); |
| 703 | |
| 704 | #undef FLD |
| 705 | } |
| 706 | NEXT (vpc); |
| 707 | |
| 708 | CASE (sem, INSN_L_NOP_IMM) : /* l.nop ${uimm16} */ |
| 709 | { |
| 710 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 711 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 712 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f |
| 713 | int UNUSED written = 0; |
| 714 | IADDR UNUSED pc = abuf->addr; |
| 715 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 716 | |
| 717 | or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16))); |
| 718 | |
| 719 | #undef FLD |
| 720 | } |
| 721 | NEXT (vpc); |
| 722 | |
| 723 | CASE (sem, INSN_L_MOVHI) : /* l.movhi $rD,$uimm16 */ |
| 724 | { |
| 725 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 726 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 727 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f |
| 728 | int UNUSED written = 0; |
| 729 | IADDR UNUSED pc = abuf->addr; |
| 730 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 731 | |
| 732 | { |
| 733 | USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16); |
| 734 | SET_H_GPR (FLD (f_r1), opval); |
| 735 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 736 | } |
| 737 | |
| 738 | #undef FLD |
| 739 | } |
| 740 | NEXT (vpc); |
| 741 | |
| 742 | CASE (sem, INSN_L_MACRC) : /* l.macrc $rD */ |
| 743 | { |
| 744 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 745 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 746 | #define FLD(f) abuf->fields.sfmt_l_adrp.f |
| 747 | int UNUSED written = 0; |
| 748 | IADDR UNUSED pc = abuf->addr; |
| 749 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 750 | |
| 751 | { |
| 752 | { |
| 753 | USI opval = GET_H_MAC_MACLO (); |
| 754 | SET_H_GPR (FLD (f_r1), opval); |
| 755 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 756 | } |
| 757 | { |
| 758 | USI opval = 0; |
| 759 | SET_H_MAC_MACLO (opval); |
| 760 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 761 | } |
| 762 | { |
| 763 | USI opval = 0; |
| 764 | SET_H_MAC_MACHI (opval); |
| 765 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 766 | } |
| 767 | } |
| 768 | |
| 769 | #undef FLD |
| 770 | } |
| 771 | NEXT (vpc); |
| 772 | |
| 773 | CASE (sem, INSN_L_MFSPR) : /* l.mfspr $rD,$rA,${uimm16} */ |
| 774 | { |
| 775 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 776 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 777 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f |
| 778 | int UNUSED written = 0; |
| 779 | IADDR UNUSED pc = abuf->addr; |
| 780 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 781 | |
| 782 | { |
| 783 | USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)))); |
| 784 | SET_H_GPR (FLD (f_r1), opval); |
| 785 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 786 | } |
| 787 | |
| 788 | #undef FLD |
| 789 | } |
| 790 | NEXT (vpc); |
| 791 | |
| 792 | CASE (sem, INSN_L_MTSPR) : /* l.mtspr $rA,$rB,${uimm16-split} */ |
| 793 | { |
| 794 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 795 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 796 | #define FLD(f) abuf->fields.sfmt_l_mtspr.f |
| 797 | int UNUSED written = 0; |
| 798 | IADDR UNUSED pc = abuf->addr; |
| 799 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 800 | |
| 801 | or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3))); |
| 802 | |
| 803 | #undef FLD |
| 804 | } |
| 805 | NEXT (vpc); |
| 806 | |
| 807 | CASE (sem, INSN_L_LWZ) : /* l.lwz $rD,${simm16}($rA) */ |
| 808 | { |
| 809 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 810 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 811 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 812 | int UNUSED written = 0; |
| 813 | IADDR UNUSED pc = abuf->addr; |
| 814 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 815 | |
| 816 | { |
| 817 | USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); |
| 818 | SET_H_GPR (FLD (f_r1), opval); |
| 819 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 820 | } |
| 821 | |
| 822 | #undef FLD |
| 823 | } |
| 824 | NEXT (vpc); |
| 825 | |
| 826 | CASE (sem, INSN_L_LWS) : /* l.lws $rD,${simm16}($rA) */ |
| 827 | { |
| 828 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 829 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 830 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 831 | int UNUSED written = 0; |
| 832 | IADDR UNUSED pc = abuf->addr; |
| 833 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 834 | |
| 835 | { |
| 836 | SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); |
| 837 | SET_H_GPR (FLD (f_r1), opval); |
| 838 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 839 | } |
| 840 | |
| 841 | #undef FLD |
| 842 | } |
| 843 | NEXT (vpc); |
| 844 | |
| 845 | CASE (sem, INSN_L_LWA) : /* l.lwa $rD,${simm16}($rA) */ |
| 846 | { |
| 847 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 848 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 849 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 850 | int UNUSED written = 0; |
| 851 | IADDR UNUSED pc = abuf->addr; |
| 852 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 853 | |
| 854 | { |
| 855 | { |
| 856 | USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); |
| 857 | SET_H_GPR (FLD (f_r1), opval); |
| 858 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 859 | } |
| 860 | { |
| 861 | BI opval = 1; |
| 862 | CPU (h_atomic_reserve) = opval; |
| 863 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); |
| 864 | } |
| 865 | { |
| 866 | SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4); |
| 867 | CPU (h_atomic_address) = opval; |
| 868 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval); |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | #undef FLD |
| 873 | } |
| 874 | NEXT (vpc); |
| 875 | |
| 876 | CASE (sem, INSN_L_LBZ) : /* l.lbz $rD,${simm16}($rA) */ |
| 877 | { |
| 878 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 879 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 880 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 881 | int UNUSED written = 0; |
| 882 | IADDR UNUSED pc = abuf->addr; |
| 883 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 884 | |
| 885 | { |
| 886 | USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1))); |
| 887 | SET_H_GPR (FLD (f_r1), opval); |
| 888 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 889 | } |
| 890 | |
| 891 | #undef FLD |
| 892 | } |
| 893 | NEXT (vpc); |
| 894 | |
| 895 | CASE (sem, INSN_L_LBS) : /* l.lbs $rD,${simm16}($rA) */ |
| 896 | { |
| 897 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 898 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 899 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 900 | int UNUSED written = 0; |
| 901 | IADDR UNUSED pc = abuf->addr; |
| 902 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 903 | |
| 904 | { |
| 905 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1))); |
| 906 | SET_H_GPR (FLD (f_r1), opval); |
| 907 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 908 | } |
| 909 | |
| 910 | #undef FLD |
| 911 | } |
| 912 | NEXT (vpc); |
| 913 | |
| 914 | CASE (sem, INSN_L_LHZ) : /* l.lhz $rD,${simm16}($rA) */ |
| 915 | { |
| 916 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 917 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 918 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 919 | int UNUSED written = 0; |
| 920 | IADDR UNUSED pc = abuf->addr; |
| 921 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 922 | |
| 923 | { |
| 924 | USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2))); |
| 925 | SET_H_GPR (FLD (f_r1), opval); |
| 926 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 927 | } |
| 928 | |
| 929 | #undef FLD |
| 930 | } |
| 931 | NEXT (vpc); |
| 932 | |
| 933 | CASE (sem, INSN_L_LHS) : /* l.lhs $rD,${simm16}($rA) */ |
| 934 | { |
| 935 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 936 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 937 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 938 | int UNUSED written = 0; |
| 939 | IADDR UNUSED pc = abuf->addr; |
| 940 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 941 | |
| 942 | { |
| 943 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2))); |
| 944 | SET_H_GPR (FLD (f_r1), opval); |
| 945 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 946 | } |
| 947 | |
| 948 | #undef FLD |
| 949 | } |
| 950 | NEXT (vpc); |
| 951 | |
| 952 | CASE (sem, INSN_L_SW) : /* l.sw ${simm16-split}($rA),$rB */ |
| 953 | { |
| 954 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 955 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 956 | #define FLD(f) abuf->fields.sfmt_l_sw.f |
| 957 | int UNUSED written = 0; |
| 958 | IADDR UNUSED pc = abuf->addr; |
| 959 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 960 | |
| 961 | { |
| 962 | SI tmp_addr; |
| 963 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4); |
| 964 | { |
| 965 | USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3))); |
| 966 | SETMEMUSI (current_cpu, pc, tmp_addr, opval); |
| 967 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 968 | } |
| 969 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { |
| 970 | { |
| 971 | BI opval = 0; |
| 972 | CPU (h_atomic_reserve) = opval; |
| 973 | written |= (1 << 4); |
| 974 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); |
| 975 | } |
| 976 | } |
| 977 | } |
| 978 | |
| 979 | abuf->written = written; |
| 980 | #undef FLD |
| 981 | } |
| 982 | NEXT (vpc); |
| 983 | |
| 984 | CASE (sem, INSN_L_SB) : /* l.sb ${simm16-split}($rA),$rB */ |
| 985 | { |
| 986 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 987 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 988 | #define FLD(f) abuf->fields.sfmt_l_sw.f |
| 989 | int UNUSED written = 0; |
| 990 | IADDR UNUSED pc = abuf->addr; |
| 991 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 992 | |
| 993 | { |
| 994 | SI tmp_addr; |
| 995 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1); |
| 996 | { |
| 997 | UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3))); |
| 998 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); |
| 999 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 1000 | } |
| 1001 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { |
| 1002 | { |
| 1003 | BI opval = 0; |
| 1004 | CPU (h_atomic_reserve) = opval; |
| 1005 | written |= (1 << 4); |
| 1006 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); |
| 1007 | } |
| 1008 | } |
| 1009 | } |
| 1010 | |
| 1011 | abuf->written = written; |
| 1012 | #undef FLD |
| 1013 | } |
| 1014 | NEXT (vpc); |
| 1015 | |
| 1016 | CASE (sem, INSN_L_SH) : /* l.sh ${simm16-split}($rA),$rB */ |
| 1017 | { |
| 1018 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1019 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1020 | #define FLD(f) abuf->fields.sfmt_l_sw.f |
| 1021 | int UNUSED written = 0; |
| 1022 | IADDR UNUSED pc = abuf->addr; |
| 1023 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1024 | |
| 1025 | { |
| 1026 | SI tmp_addr; |
| 1027 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2); |
| 1028 | { |
| 1029 | UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3))); |
| 1030 | SETMEMUHI (current_cpu, pc, tmp_addr, opval); |
| 1031 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 1032 | } |
| 1033 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { |
| 1034 | { |
| 1035 | BI opval = 0; |
| 1036 | CPU (h_atomic_reserve) = opval; |
| 1037 | written |= (1 << 4); |
| 1038 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); |
| 1039 | } |
| 1040 | } |
| 1041 | } |
| 1042 | |
| 1043 | abuf->written = written; |
| 1044 | #undef FLD |
| 1045 | } |
| 1046 | NEXT (vpc); |
| 1047 | |
| 1048 | CASE (sem, INSN_L_SWA) : /* l.swa ${simm16-split}($rA),$rB */ |
| 1049 | { |
| 1050 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1051 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1052 | #define FLD(f) abuf->fields.sfmt_l_sw.f |
| 1053 | int UNUSED written = 0; |
| 1054 | IADDR UNUSED pc = abuf->addr; |
| 1055 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1056 | |
| 1057 | { |
| 1058 | SI tmp_addr; |
| 1059 | BI tmp_flag; |
| 1060 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4); |
| 1061 | { |
| 1062 | USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address))); |
| 1063 | SET_H_SYS_SR_F (opval); |
| 1064 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 1065 | } |
| 1066 | if (GET_H_SYS_SR_F ()) { |
| 1067 | { |
| 1068 | USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3))); |
| 1069 | SETMEMUSI (current_cpu, pc, tmp_addr, opval); |
| 1070 | written |= (1 << 7); |
| 1071 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 1072 | } |
| 1073 | } |
| 1074 | { |
| 1075 | BI opval = 0; |
| 1076 | CPU (h_atomic_reserve) = opval; |
| 1077 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); |
| 1078 | } |
| 1079 | } |
| 1080 | |
| 1081 | abuf->written = written; |
| 1082 | #undef FLD |
| 1083 | } |
| 1084 | NEXT (vpc); |
| 1085 | |
| 1086 | CASE (sem, INSN_L_SLL) : /* l.sll $rD,$rA,$rB */ |
| 1087 | { |
| 1088 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1089 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1090 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1091 | int UNUSED written = 0; |
| 1092 | IADDR UNUSED pc = abuf->addr; |
| 1093 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1094 | |
| 1095 | { |
| 1096 | USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1097 | SET_H_GPR (FLD (f_r1), opval); |
| 1098 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1099 | } |
| 1100 | |
| 1101 | #undef FLD |
| 1102 | } |
| 1103 | NEXT (vpc); |
| 1104 | |
| 1105 | CASE (sem, INSN_L_SLLI) : /* l.slli $rD,$rA,${uimm6} */ |
| 1106 | { |
| 1107 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1108 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1109 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1110 | int UNUSED written = 0; |
| 1111 | IADDR UNUSED pc = abuf->addr; |
| 1112 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1113 | |
| 1114 | { |
| 1115 | USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); |
| 1116 | SET_H_GPR (FLD (f_r1), opval); |
| 1117 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1118 | } |
| 1119 | |
| 1120 | #undef FLD |
| 1121 | } |
| 1122 | NEXT (vpc); |
| 1123 | |
| 1124 | CASE (sem, INSN_L_SRL) : /* l.srl $rD,$rA,$rB */ |
| 1125 | { |
| 1126 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1127 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1128 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1129 | int UNUSED written = 0; |
| 1130 | IADDR UNUSED pc = abuf->addr; |
| 1131 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1132 | |
| 1133 | { |
| 1134 | USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1135 | SET_H_GPR (FLD (f_r1), opval); |
| 1136 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1137 | } |
| 1138 | |
| 1139 | #undef FLD |
| 1140 | } |
| 1141 | NEXT (vpc); |
| 1142 | |
| 1143 | CASE (sem, INSN_L_SRLI) : /* l.srli $rD,$rA,${uimm6} */ |
| 1144 | { |
| 1145 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1146 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1147 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1148 | int UNUSED written = 0; |
| 1149 | IADDR UNUSED pc = abuf->addr; |
| 1150 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1151 | |
| 1152 | { |
| 1153 | USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); |
| 1154 | SET_H_GPR (FLD (f_r1), opval); |
| 1155 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1156 | } |
| 1157 | |
| 1158 | #undef FLD |
| 1159 | } |
| 1160 | NEXT (vpc); |
| 1161 | |
| 1162 | CASE (sem, INSN_L_SRA) : /* l.sra $rD,$rA,$rB */ |
| 1163 | { |
| 1164 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1165 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1166 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1167 | int UNUSED written = 0; |
| 1168 | IADDR UNUSED pc = abuf->addr; |
| 1169 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1170 | |
| 1171 | { |
| 1172 | USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1173 | SET_H_GPR (FLD (f_r1), opval); |
| 1174 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1175 | } |
| 1176 | |
| 1177 | #undef FLD |
| 1178 | } |
| 1179 | NEXT (vpc); |
| 1180 | |
| 1181 | CASE (sem, INSN_L_SRAI) : /* l.srai $rD,$rA,${uimm6} */ |
| 1182 | { |
| 1183 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1184 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1185 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1186 | int UNUSED written = 0; |
| 1187 | IADDR UNUSED pc = abuf->addr; |
| 1188 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1189 | |
| 1190 | { |
| 1191 | USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); |
| 1192 | SET_H_GPR (FLD (f_r1), opval); |
| 1193 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1194 | } |
| 1195 | |
| 1196 | #undef FLD |
| 1197 | } |
| 1198 | NEXT (vpc); |
| 1199 | |
| 1200 | CASE (sem, INSN_L_ROR) : /* l.ror $rD,$rA,$rB */ |
| 1201 | { |
| 1202 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1203 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1204 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1205 | int UNUSED written = 0; |
| 1206 | IADDR UNUSED pc = abuf->addr; |
| 1207 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1208 | |
| 1209 | { |
| 1210 | USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1211 | SET_H_GPR (FLD (f_r1), opval); |
| 1212 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1213 | } |
| 1214 | |
| 1215 | #undef FLD |
| 1216 | } |
| 1217 | NEXT (vpc); |
| 1218 | |
| 1219 | CASE (sem, INSN_L_RORI) : /* l.rori $rD,$rA,${uimm6} */ |
| 1220 | { |
| 1221 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1222 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1223 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1224 | int UNUSED written = 0; |
| 1225 | IADDR UNUSED pc = abuf->addr; |
| 1226 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1227 | |
| 1228 | { |
| 1229 | USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); |
| 1230 | SET_H_GPR (FLD (f_r1), opval); |
| 1231 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1232 | } |
| 1233 | |
| 1234 | #undef FLD |
| 1235 | } |
| 1236 | NEXT (vpc); |
| 1237 | |
| 1238 | CASE (sem, INSN_L_AND) : /* l.and $rD,$rA,$rB */ |
| 1239 | { |
| 1240 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1241 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1242 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1243 | int UNUSED written = 0; |
| 1244 | IADDR UNUSED pc = abuf->addr; |
| 1245 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1246 | |
| 1247 | { |
| 1248 | USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1249 | SET_H_GPR (FLD (f_r1), opval); |
| 1250 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1251 | } |
| 1252 | |
| 1253 | #undef FLD |
| 1254 | } |
| 1255 | NEXT (vpc); |
| 1256 | |
| 1257 | CASE (sem, INSN_L_OR) : /* l.or $rD,$rA,$rB */ |
| 1258 | { |
| 1259 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1260 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1261 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1262 | int UNUSED written = 0; |
| 1263 | IADDR UNUSED pc = abuf->addr; |
| 1264 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1265 | |
| 1266 | { |
| 1267 | USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1268 | SET_H_GPR (FLD (f_r1), opval); |
| 1269 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1270 | } |
| 1271 | |
| 1272 | #undef FLD |
| 1273 | } |
| 1274 | NEXT (vpc); |
| 1275 | |
| 1276 | CASE (sem, INSN_L_XOR) : /* l.xor $rD,$rA,$rB */ |
| 1277 | { |
| 1278 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1279 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1280 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1281 | int UNUSED written = 0; |
| 1282 | IADDR UNUSED pc = abuf->addr; |
| 1283 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1284 | |
| 1285 | { |
| 1286 | USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1287 | SET_H_GPR (FLD (f_r1), opval); |
| 1288 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1289 | } |
| 1290 | |
| 1291 | #undef FLD |
| 1292 | } |
| 1293 | NEXT (vpc); |
| 1294 | |
| 1295 | CASE (sem, INSN_L_ADD) : /* l.add $rD,$rA,$rB */ |
| 1296 | { |
| 1297 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1298 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1299 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1300 | int UNUSED written = 0; |
| 1301 | IADDR UNUSED pc = abuf->addr; |
| 1302 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1303 | |
| 1304 | { |
| 1305 | { |
| 1306 | { |
| 1307 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); |
| 1308 | SET_H_SYS_SR_CY (opval); |
| 1309 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1310 | } |
| 1311 | { |
| 1312 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); |
| 1313 | SET_H_SYS_SR_OV (opval); |
| 1314 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1315 | } |
| 1316 | { |
| 1317 | USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1318 | SET_H_GPR (FLD (f_r1), opval); |
| 1319 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1320 | } |
| 1321 | } |
| 1322 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 1323 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1324 | } |
| 1325 | } |
| 1326 | |
| 1327 | #undef FLD |
| 1328 | } |
| 1329 | NEXT (vpc); |
| 1330 | |
| 1331 | CASE (sem, INSN_L_SUB) : /* l.sub $rD,$rA,$rB */ |
| 1332 | { |
| 1333 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1334 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1335 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1336 | int UNUSED written = 0; |
| 1337 | IADDR UNUSED pc = abuf->addr; |
| 1338 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1339 | |
| 1340 | { |
| 1341 | { |
| 1342 | { |
| 1343 | BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); |
| 1344 | SET_H_SYS_SR_CY (opval); |
| 1345 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1346 | } |
| 1347 | { |
| 1348 | BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); |
| 1349 | SET_H_SYS_SR_OV (opval); |
| 1350 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1351 | } |
| 1352 | { |
| 1353 | USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1354 | SET_H_GPR (FLD (f_r1), opval); |
| 1355 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1356 | } |
| 1357 | } |
| 1358 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 1359 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1360 | } |
| 1361 | } |
| 1362 | |
| 1363 | #undef FLD |
| 1364 | } |
| 1365 | NEXT (vpc); |
| 1366 | |
| 1367 | CASE (sem, INSN_L_ADDC) : /* l.addc $rD,$rA,$rB */ |
| 1368 | { |
| 1369 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1370 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1371 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1372 | int UNUSED written = 0; |
| 1373 | IADDR UNUSED pc = abuf->addr; |
| 1374 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1375 | |
| 1376 | { |
| 1377 | { |
| 1378 | BI tmp_tmp_sys_sr_cy; |
| 1379 | tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY (); |
| 1380 | { |
| 1381 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); |
| 1382 | SET_H_SYS_SR_CY (opval); |
| 1383 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1384 | } |
| 1385 | { |
| 1386 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); |
| 1387 | SET_H_SYS_SR_OV (opval); |
| 1388 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1389 | } |
| 1390 | { |
| 1391 | USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); |
| 1392 | SET_H_GPR (FLD (f_r1), opval); |
| 1393 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1394 | } |
| 1395 | } |
| 1396 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 1397 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1398 | } |
| 1399 | } |
| 1400 | |
| 1401 | #undef FLD |
| 1402 | } |
| 1403 | NEXT (vpc); |
| 1404 | |
| 1405 | CASE (sem, INSN_L_MUL) : /* l.mul $rD,$rA,$rB */ |
| 1406 | { |
| 1407 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1408 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1409 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1410 | int UNUSED written = 0; |
| 1411 | IADDR UNUSED pc = abuf->addr; |
| 1412 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1413 | |
| 1414 | { |
| 1415 | { |
| 1416 | { |
| 1417 | BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1418 | SET_H_SYS_SR_OV (opval); |
| 1419 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1420 | } |
| 1421 | { |
| 1422 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1423 | SET_H_GPR (FLD (f_r1), opval); |
| 1424 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1425 | } |
| 1426 | } |
| 1427 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 1428 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1429 | } |
| 1430 | } |
| 1431 | |
| 1432 | #undef FLD |
| 1433 | } |
| 1434 | NEXT (vpc); |
| 1435 | |
| 1436 | CASE (sem, INSN_L_MULD) : /* l.muld $rA,$rB */ |
| 1437 | { |
| 1438 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1439 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1440 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1441 | int UNUSED written = 0; |
| 1442 | IADDR UNUSED pc = abuf->addr; |
| 1443 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1444 | |
| 1445 | { |
| 1446 | DI tmp_result; |
| 1447 | tmp_result = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); |
| 1448 | { |
| 1449 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 1450 | SET_H_MAC_MACHI (opval); |
| 1451 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 1452 | } |
| 1453 | { |
| 1454 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 1455 | SET_H_MAC_MACLO (opval); |
| 1456 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 1457 | } |
| 1458 | } |
| 1459 | |
| 1460 | #undef FLD |
| 1461 | } |
| 1462 | NEXT (vpc); |
| 1463 | |
| 1464 | CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */ |
| 1465 | { |
| 1466 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1467 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1468 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1469 | int UNUSED written = 0; |
| 1470 | IADDR UNUSED pc = abuf->addr; |
| 1471 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1472 | |
| 1473 | { |
| 1474 | { |
| 1475 | { |
| 1476 | BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1477 | SET_H_SYS_SR_CY (opval); |
| 1478 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1479 | } |
| 1480 | { |
| 1481 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1482 | SET_H_GPR (FLD (f_r1), opval); |
| 1483 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1484 | } |
| 1485 | } |
| 1486 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { |
| 1487 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1488 | } |
| 1489 | } |
| 1490 | |
| 1491 | #undef FLD |
| 1492 | } |
| 1493 | NEXT (vpc); |
| 1494 | |
| 1495 | CASE (sem, INSN_L_MULDU) : /* l.muldu $rA,$rB */ |
| 1496 | { |
| 1497 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1498 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1499 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1500 | int UNUSED written = 0; |
| 1501 | IADDR UNUSED pc = abuf->addr; |
| 1502 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1503 | |
| 1504 | { |
| 1505 | DI tmp_result; |
| 1506 | tmp_result = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); |
| 1507 | { |
| 1508 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 1509 | SET_H_MAC_MACHI (opval); |
| 1510 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 1511 | } |
| 1512 | { |
| 1513 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 1514 | SET_H_MAC_MACLO (opval); |
| 1515 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 1516 | } |
| 1517 | } |
| 1518 | |
| 1519 | #undef FLD |
| 1520 | } |
| 1521 | NEXT (vpc); |
| 1522 | |
| 1523 | CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */ |
| 1524 | { |
| 1525 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1526 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1527 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1528 | int UNUSED written = 0; |
| 1529 | IADDR UNUSED pc = abuf->addr; |
| 1530 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1531 | |
| 1532 | if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { |
| 1533 | { |
| 1534 | { |
| 1535 | BI opval = 0; |
| 1536 | SET_H_SYS_SR_OV (opval); |
| 1537 | written |= (1 << 5); |
| 1538 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1539 | } |
| 1540 | { |
| 1541 | SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1542 | SET_H_GPR (FLD (f_r1), opval); |
| 1543 | written |= (1 << 4); |
| 1544 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1545 | } |
| 1546 | } |
| 1547 | } else { |
| 1548 | { |
| 1549 | { |
| 1550 | BI opval = 1; |
| 1551 | SET_H_SYS_SR_OV (opval); |
| 1552 | written |= (1 << 5); |
| 1553 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1554 | } |
| 1555 | if (GET_H_SYS_SR_OVE ()) { |
| 1556 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1557 | } |
| 1558 | } |
| 1559 | } |
| 1560 | |
| 1561 | abuf->written = written; |
| 1562 | #undef FLD |
| 1563 | } |
| 1564 | NEXT (vpc); |
| 1565 | |
| 1566 | CASE (sem, INSN_L_DIVU) : /* l.divu $rD,$rA,$rB */ |
| 1567 | { |
| 1568 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1569 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1570 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1571 | int UNUSED written = 0; |
| 1572 | IADDR UNUSED pc = abuf->addr; |
| 1573 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1574 | |
| 1575 | if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { |
| 1576 | { |
| 1577 | { |
| 1578 | BI opval = 0; |
| 1579 | SET_H_SYS_SR_CY (opval); |
| 1580 | written |= (1 << 5); |
| 1581 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1582 | } |
| 1583 | { |
| 1584 | USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1585 | SET_H_GPR (FLD (f_r1), opval); |
| 1586 | written |= (1 << 4); |
| 1587 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1588 | } |
| 1589 | } |
| 1590 | } else { |
| 1591 | { |
| 1592 | { |
| 1593 | BI opval = 1; |
| 1594 | SET_H_SYS_SR_CY (opval); |
| 1595 | written |= (1 << 5); |
| 1596 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1597 | } |
| 1598 | if (GET_H_SYS_SR_OVE ()) { |
| 1599 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1600 | } |
| 1601 | } |
| 1602 | } |
| 1603 | |
| 1604 | abuf->written = written; |
| 1605 | #undef FLD |
| 1606 | } |
| 1607 | NEXT (vpc); |
| 1608 | |
| 1609 | CASE (sem, INSN_L_FF1) : /* l.ff1 $rD,$rA */ |
| 1610 | { |
| 1611 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1612 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1613 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1614 | int UNUSED written = 0; |
| 1615 | IADDR UNUSED pc = abuf->addr; |
| 1616 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1617 | |
| 1618 | { |
| 1619 | USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2))); |
| 1620 | SET_H_GPR (FLD (f_r1), opval); |
| 1621 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1622 | } |
| 1623 | |
| 1624 | #undef FLD |
| 1625 | } |
| 1626 | NEXT (vpc); |
| 1627 | |
| 1628 | CASE (sem, INSN_L_FL1) : /* l.fl1 $rD,$rA */ |
| 1629 | { |
| 1630 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1631 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1632 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1633 | int UNUSED written = 0; |
| 1634 | IADDR UNUSED pc = abuf->addr; |
| 1635 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1636 | |
| 1637 | { |
| 1638 | USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2))); |
| 1639 | SET_H_GPR (FLD (f_r1), opval); |
| 1640 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1641 | } |
| 1642 | |
| 1643 | #undef FLD |
| 1644 | } |
| 1645 | NEXT (vpc); |
| 1646 | |
| 1647 | CASE (sem, INSN_L_ANDI) : /* l.andi $rD,$rA,$uimm16 */ |
| 1648 | { |
| 1649 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1650 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1651 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f |
| 1652 | int UNUSED written = 0; |
| 1653 | IADDR UNUSED pc = abuf->addr; |
| 1654 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1655 | |
| 1656 | { |
| 1657 | USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))); |
| 1658 | SET_H_GPR (FLD (f_r1), opval); |
| 1659 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1660 | } |
| 1661 | |
| 1662 | #undef FLD |
| 1663 | } |
| 1664 | NEXT (vpc); |
| 1665 | |
| 1666 | CASE (sem, INSN_L_ORI) : /* l.ori $rD,$rA,$uimm16 */ |
| 1667 | { |
| 1668 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1669 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1670 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f |
| 1671 | int UNUSED written = 0; |
| 1672 | IADDR UNUSED pc = abuf->addr; |
| 1673 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1674 | |
| 1675 | { |
| 1676 | USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))); |
| 1677 | SET_H_GPR (FLD (f_r1), opval); |
| 1678 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1679 | } |
| 1680 | |
| 1681 | #undef FLD |
| 1682 | } |
| 1683 | NEXT (vpc); |
| 1684 | |
| 1685 | CASE (sem, INSN_L_XORI) : /* l.xori $rD,$rA,$simm16 */ |
| 1686 | { |
| 1687 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1688 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1689 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 1690 | int UNUSED written = 0; |
| 1691 | IADDR UNUSED pc = abuf->addr; |
| 1692 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1693 | |
| 1694 | { |
| 1695 | USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 1696 | SET_H_GPR (FLD (f_r1), opval); |
| 1697 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1698 | } |
| 1699 | |
| 1700 | #undef FLD |
| 1701 | } |
| 1702 | NEXT (vpc); |
| 1703 | |
| 1704 | CASE (sem, INSN_L_ADDI) : /* l.addi $rD,$rA,$simm16 */ |
| 1705 | { |
| 1706 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1707 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1708 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 1709 | int UNUSED written = 0; |
| 1710 | IADDR UNUSED pc = abuf->addr; |
| 1711 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1712 | |
| 1713 | { |
| 1714 | { |
| 1715 | { |
| 1716 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0); |
| 1717 | SET_H_SYS_SR_CY (opval); |
| 1718 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1719 | } |
| 1720 | { |
| 1721 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0); |
| 1722 | SET_H_SYS_SR_OV (opval); |
| 1723 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1724 | } |
| 1725 | { |
| 1726 | USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 1727 | SET_H_GPR (FLD (f_r1), opval); |
| 1728 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1729 | } |
| 1730 | } |
| 1731 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 1732 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1733 | } |
| 1734 | } |
| 1735 | |
| 1736 | #undef FLD |
| 1737 | } |
| 1738 | NEXT (vpc); |
| 1739 | |
| 1740 | CASE (sem, INSN_L_ADDIC) : /* l.addic $rD,$rA,$simm16 */ |
| 1741 | { |
| 1742 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1743 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1744 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 1745 | int UNUSED written = 0; |
| 1746 | IADDR UNUSED pc = abuf->addr; |
| 1747 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1748 | |
| 1749 | { |
| 1750 | { |
| 1751 | BI tmp_tmp_sys_sr_cy; |
| 1752 | tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY (); |
| 1753 | { |
| 1754 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); |
| 1755 | SET_H_SYS_SR_CY (opval); |
| 1756 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 1757 | } |
| 1758 | { |
| 1759 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); |
| 1760 | SET_H_SYS_SR_OV (opval); |
| 1761 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1762 | } |
| 1763 | { |
| 1764 | SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); |
| 1765 | SET_H_GPR (FLD (f_r1), opval); |
| 1766 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1767 | } |
| 1768 | } |
| 1769 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 1770 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1771 | } |
| 1772 | } |
| 1773 | |
| 1774 | #undef FLD |
| 1775 | } |
| 1776 | NEXT (vpc); |
| 1777 | |
| 1778 | CASE (sem, INSN_L_MULI) : /* l.muli $rD,$rA,$simm16 */ |
| 1779 | { |
| 1780 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1781 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1782 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 1783 | int UNUSED written = 0; |
| 1784 | IADDR UNUSED pc = abuf->addr; |
| 1785 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1786 | |
| 1787 | { |
| 1788 | { |
| 1789 | { |
| 1790 | USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 1791 | SET_H_SYS_SR_OV (opval); |
| 1792 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 1793 | } |
| 1794 | { |
| 1795 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 1796 | SET_H_GPR (FLD (f_r1), opval); |
| 1797 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1798 | } |
| 1799 | } |
| 1800 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 1801 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 1802 | } |
| 1803 | } |
| 1804 | |
| 1805 | #undef FLD |
| 1806 | } |
| 1807 | NEXT (vpc); |
| 1808 | |
| 1809 | CASE (sem, INSN_L_EXTHS) : /* l.exths $rD,$rA */ |
| 1810 | { |
| 1811 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1812 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1813 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1814 | int UNUSED written = 0; |
| 1815 | IADDR UNUSED pc = abuf->addr; |
| 1816 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1817 | |
| 1818 | { |
| 1819 | USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2)))); |
| 1820 | SET_H_GPR (FLD (f_r1), opval); |
| 1821 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1822 | } |
| 1823 | |
| 1824 | #undef FLD |
| 1825 | } |
| 1826 | NEXT (vpc); |
| 1827 | |
| 1828 | CASE (sem, INSN_L_EXTBS) : /* l.extbs $rD,$rA */ |
| 1829 | { |
| 1830 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1831 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1832 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1833 | int UNUSED written = 0; |
| 1834 | IADDR UNUSED pc = abuf->addr; |
| 1835 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1836 | |
| 1837 | { |
| 1838 | USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2)))); |
| 1839 | SET_H_GPR (FLD (f_r1), opval); |
| 1840 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1841 | } |
| 1842 | |
| 1843 | #undef FLD |
| 1844 | } |
| 1845 | NEXT (vpc); |
| 1846 | |
| 1847 | CASE (sem, INSN_L_EXTHZ) : /* l.exthz $rD,$rA */ |
| 1848 | { |
| 1849 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1850 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1851 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1852 | int UNUSED written = 0; |
| 1853 | IADDR UNUSED pc = abuf->addr; |
| 1854 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1855 | |
| 1856 | { |
| 1857 | USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2)))); |
| 1858 | SET_H_GPR (FLD (f_r1), opval); |
| 1859 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1860 | } |
| 1861 | |
| 1862 | #undef FLD |
| 1863 | } |
| 1864 | NEXT (vpc); |
| 1865 | |
| 1866 | CASE (sem, INSN_L_EXTBZ) : /* l.extbz $rD,$rA */ |
| 1867 | { |
| 1868 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1869 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1870 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1871 | int UNUSED written = 0; |
| 1872 | IADDR UNUSED pc = abuf->addr; |
| 1873 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1874 | |
| 1875 | { |
| 1876 | USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2)))); |
| 1877 | SET_H_GPR (FLD (f_r1), opval); |
| 1878 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1879 | } |
| 1880 | |
| 1881 | #undef FLD |
| 1882 | } |
| 1883 | NEXT (vpc); |
| 1884 | |
| 1885 | CASE (sem, INSN_L_EXTWS) : /* l.extws $rD,$rA */ |
| 1886 | { |
| 1887 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1888 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1889 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1890 | int UNUSED written = 0; |
| 1891 | IADDR UNUSED pc = abuf->addr; |
| 1892 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1893 | |
| 1894 | { |
| 1895 | USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2)))); |
| 1896 | SET_H_GPR (FLD (f_r1), opval); |
| 1897 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1898 | } |
| 1899 | |
| 1900 | #undef FLD |
| 1901 | } |
| 1902 | NEXT (vpc); |
| 1903 | |
| 1904 | CASE (sem, INSN_L_EXTWZ) : /* l.extwz $rD,$rA */ |
| 1905 | { |
| 1906 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1907 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1908 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 1909 | int UNUSED written = 0; |
| 1910 | IADDR UNUSED pc = abuf->addr; |
| 1911 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1912 | |
| 1913 | { |
| 1914 | USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2)))); |
| 1915 | SET_H_GPR (FLD (f_r1), opval); |
| 1916 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1917 | } |
| 1918 | |
| 1919 | #undef FLD |
| 1920 | } |
| 1921 | NEXT (vpc); |
| 1922 | |
| 1923 | CASE (sem, INSN_L_CMOV) : /* l.cmov $rD,$rA,$rB */ |
| 1924 | { |
| 1925 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1926 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1927 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1928 | int UNUSED written = 0; |
| 1929 | IADDR UNUSED pc = abuf->addr; |
| 1930 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1931 | |
| 1932 | if (GET_H_SYS_SR_F ()) { |
| 1933 | { |
| 1934 | USI opval = GET_H_GPR (FLD (f_r2)); |
| 1935 | SET_H_GPR (FLD (f_r1), opval); |
| 1936 | written |= (1 << 3); |
| 1937 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1938 | } |
| 1939 | } else { |
| 1940 | { |
| 1941 | USI opval = GET_H_GPR (FLD (f_r3)); |
| 1942 | SET_H_GPR (FLD (f_r1), opval); |
| 1943 | written |= (1 << 3); |
| 1944 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 1945 | } |
| 1946 | } |
| 1947 | |
| 1948 | abuf->written = written; |
| 1949 | #undef FLD |
| 1950 | } |
| 1951 | NEXT (vpc); |
| 1952 | |
| 1953 | CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */ |
| 1954 | { |
| 1955 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1956 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1957 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1958 | int UNUSED written = 0; |
| 1959 | IADDR UNUSED pc = abuf->addr; |
| 1960 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1961 | |
| 1962 | { |
| 1963 | USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 1964 | SET_H_SYS_SR_F (opval); |
| 1965 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 1966 | } |
| 1967 | |
| 1968 | #undef FLD |
| 1969 | } |
| 1970 | NEXT (vpc); |
| 1971 | |
| 1972 | CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,$simm16 */ |
| 1973 | { |
| 1974 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1975 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1976 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 1977 | int UNUSED written = 0; |
| 1978 | IADDR UNUSED pc = abuf->addr; |
| 1979 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1980 | |
| 1981 | { |
| 1982 | USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 1983 | SET_H_SYS_SR_F (opval); |
| 1984 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 1985 | } |
| 1986 | |
| 1987 | #undef FLD |
| 1988 | } |
| 1989 | NEXT (vpc); |
| 1990 | |
| 1991 | CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */ |
| 1992 | { |
| 1993 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1994 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1995 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 1996 | int UNUSED written = 0; |
| 1997 | IADDR UNUSED pc = abuf->addr; |
| 1998 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 1999 | |
| 2000 | { |
| 2001 | USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2002 | SET_H_SYS_SR_F (opval); |
| 2003 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2004 | } |
| 2005 | |
| 2006 | #undef FLD |
| 2007 | } |
| 2008 | NEXT (vpc); |
| 2009 | |
| 2010 | CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$simm16 */ |
| 2011 | { |
| 2012 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2013 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2014 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2015 | int UNUSED written = 0; |
| 2016 | IADDR UNUSED pc = abuf->addr; |
| 2017 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2018 | |
| 2019 | { |
| 2020 | USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2021 | SET_H_SYS_SR_F (opval); |
| 2022 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2023 | } |
| 2024 | |
| 2025 | #undef FLD |
| 2026 | } |
| 2027 | NEXT (vpc); |
| 2028 | |
| 2029 | CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */ |
| 2030 | { |
| 2031 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2032 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2033 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2034 | int UNUSED written = 0; |
| 2035 | IADDR UNUSED pc = abuf->addr; |
| 2036 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2037 | |
| 2038 | { |
| 2039 | USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2040 | SET_H_SYS_SR_F (opval); |
| 2041 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2042 | } |
| 2043 | |
| 2044 | #undef FLD |
| 2045 | } |
| 2046 | NEXT (vpc); |
| 2047 | |
| 2048 | CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,$simm16 */ |
| 2049 | { |
| 2050 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2051 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2052 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2053 | int UNUSED written = 0; |
| 2054 | IADDR UNUSED pc = abuf->addr; |
| 2055 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2056 | |
| 2057 | { |
| 2058 | USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2059 | SET_H_SYS_SR_F (opval); |
| 2060 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2061 | } |
| 2062 | |
| 2063 | #undef FLD |
| 2064 | } |
| 2065 | NEXT (vpc); |
| 2066 | |
| 2067 | CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */ |
| 2068 | { |
| 2069 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2070 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2071 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2072 | int UNUSED written = 0; |
| 2073 | IADDR UNUSED pc = abuf->addr; |
| 2074 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2075 | |
| 2076 | { |
| 2077 | USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2078 | SET_H_SYS_SR_F (opval); |
| 2079 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2080 | } |
| 2081 | |
| 2082 | #undef FLD |
| 2083 | } |
| 2084 | NEXT (vpc); |
| 2085 | |
| 2086 | CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$simm16 */ |
| 2087 | { |
| 2088 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2089 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2090 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2091 | int UNUSED written = 0; |
| 2092 | IADDR UNUSED pc = abuf->addr; |
| 2093 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2094 | |
| 2095 | { |
| 2096 | USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2097 | SET_H_SYS_SR_F (opval); |
| 2098 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2099 | } |
| 2100 | |
| 2101 | #undef FLD |
| 2102 | } |
| 2103 | NEXT (vpc); |
| 2104 | |
| 2105 | CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */ |
| 2106 | { |
| 2107 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2108 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2109 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2110 | int UNUSED written = 0; |
| 2111 | IADDR UNUSED pc = abuf->addr; |
| 2112 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2113 | |
| 2114 | { |
| 2115 | USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2116 | SET_H_SYS_SR_F (opval); |
| 2117 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2118 | } |
| 2119 | |
| 2120 | #undef FLD |
| 2121 | } |
| 2122 | NEXT (vpc); |
| 2123 | |
| 2124 | CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,$simm16 */ |
| 2125 | { |
| 2126 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2127 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2128 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2129 | int UNUSED written = 0; |
| 2130 | IADDR UNUSED pc = abuf->addr; |
| 2131 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2132 | |
| 2133 | { |
| 2134 | USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2135 | SET_H_SYS_SR_F (opval); |
| 2136 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2137 | } |
| 2138 | |
| 2139 | #undef FLD |
| 2140 | } |
| 2141 | NEXT (vpc); |
| 2142 | |
| 2143 | CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */ |
| 2144 | { |
| 2145 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2146 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2147 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2148 | int UNUSED written = 0; |
| 2149 | IADDR UNUSED pc = abuf->addr; |
| 2150 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2151 | |
| 2152 | { |
| 2153 | USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2154 | SET_H_SYS_SR_F (opval); |
| 2155 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2156 | } |
| 2157 | |
| 2158 | #undef FLD |
| 2159 | } |
| 2160 | NEXT (vpc); |
| 2161 | |
| 2162 | CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$simm16 */ |
| 2163 | { |
| 2164 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2165 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2166 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2167 | int UNUSED written = 0; |
| 2168 | IADDR UNUSED pc = abuf->addr; |
| 2169 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2170 | |
| 2171 | { |
| 2172 | USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2173 | SET_H_SYS_SR_F (opval); |
| 2174 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2175 | } |
| 2176 | |
| 2177 | #undef FLD |
| 2178 | } |
| 2179 | NEXT (vpc); |
| 2180 | |
| 2181 | CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */ |
| 2182 | { |
| 2183 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2184 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2185 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2186 | int UNUSED written = 0; |
| 2187 | IADDR UNUSED pc = abuf->addr; |
| 2188 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2189 | |
| 2190 | { |
| 2191 | USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2192 | SET_H_SYS_SR_F (opval); |
| 2193 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2194 | } |
| 2195 | |
| 2196 | #undef FLD |
| 2197 | } |
| 2198 | NEXT (vpc); |
| 2199 | |
| 2200 | CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,$simm16 */ |
| 2201 | { |
| 2202 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2203 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2204 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2205 | int UNUSED written = 0; |
| 2206 | IADDR UNUSED pc = abuf->addr; |
| 2207 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2208 | |
| 2209 | { |
| 2210 | USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2211 | SET_H_SYS_SR_F (opval); |
| 2212 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2213 | } |
| 2214 | |
| 2215 | #undef FLD |
| 2216 | } |
| 2217 | NEXT (vpc); |
| 2218 | |
| 2219 | CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */ |
| 2220 | { |
| 2221 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2222 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2223 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2224 | int UNUSED written = 0; |
| 2225 | IADDR UNUSED pc = abuf->addr; |
| 2226 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2227 | |
| 2228 | { |
| 2229 | USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2230 | SET_H_SYS_SR_F (opval); |
| 2231 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2232 | } |
| 2233 | |
| 2234 | #undef FLD |
| 2235 | } |
| 2236 | NEXT (vpc); |
| 2237 | |
| 2238 | CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$simm16 */ |
| 2239 | { |
| 2240 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2241 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2242 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2243 | int UNUSED written = 0; |
| 2244 | IADDR UNUSED pc = abuf->addr; |
| 2245 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2246 | |
| 2247 | { |
| 2248 | USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2249 | SET_H_SYS_SR_F (opval); |
| 2250 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2251 | } |
| 2252 | |
| 2253 | #undef FLD |
| 2254 | } |
| 2255 | NEXT (vpc); |
| 2256 | |
| 2257 | CASE (sem, INSN_L_SFEQ) : /* l.sfeq $rA,$rB */ |
| 2258 | { |
| 2259 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2260 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2261 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2262 | int UNUSED written = 0; |
| 2263 | IADDR UNUSED pc = abuf->addr; |
| 2264 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2265 | |
| 2266 | { |
| 2267 | USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2268 | SET_H_SYS_SR_F (opval); |
| 2269 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2270 | } |
| 2271 | |
| 2272 | #undef FLD |
| 2273 | } |
| 2274 | NEXT (vpc); |
| 2275 | |
| 2276 | CASE (sem, INSN_L_SFEQI) : /* l.sfeqi $rA,$simm16 */ |
| 2277 | { |
| 2278 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2279 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2280 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2281 | int UNUSED written = 0; |
| 2282 | IADDR UNUSED pc = abuf->addr; |
| 2283 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2284 | |
| 2285 | { |
| 2286 | USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2287 | SET_H_SYS_SR_F (opval); |
| 2288 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2289 | } |
| 2290 | |
| 2291 | #undef FLD |
| 2292 | } |
| 2293 | NEXT (vpc); |
| 2294 | |
| 2295 | CASE (sem, INSN_L_SFNE) : /* l.sfne $rA,$rB */ |
| 2296 | { |
| 2297 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2298 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2299 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2300 | int UNUSED written = 0; |
| 2301 | IADDR UNUSED pc = abuf->addr; |
| 2302 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2303 | |
| 2304 | { |
| 2305 | USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); |
| 2306 | SET_H_SYS_SR_F (opval); |
| 2307 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2308 | } |
| 2309 | |
| 2310 | #undef FLD |
| 2311 | } |
| 2312 | NEXT (vpc); |
| 2313 | |
| 2314 | CASE (sem, INSN_L_SFNEI) : /* l.sfnei $rA,$simm16 */ |
| 2315 | { |
| 2316 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2317 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2318 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2319 | int UNUSED written = 0; |
| 2320 | IADDR UNUSED pc = abuf->addr; |
| 2321 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2322 | |
| 2323 | { |
| 2324 | USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); |
| 2325 | SET_H_SYS_SR_F (opval); |
| 2326 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2327 | } |
| 2328 | |
| 2329 | #undef FLD |
| 2330 | } |
| 2331 | NEXT (vpc); |
| 2332 | |
| 2333 | CASE (sem, INSN_L_MAC) : /* l.mac $rA,$rB */ |
| 2334 | { |
| 2335 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2336 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2337 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2338 | int UNUSED written = 0; |
| 2339 | IADDR UNUSED pc = abuf->addr; |
| 2340 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2341 | |
| 2342 | { |
| 2343 | { |
| 2344 | DI tmp_prod; |
| 2345 | DI tmp_mac; |
| 2346 | DI tmp_result; |
| 2347 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); |
| 2348 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); |
| 2349 | tmp_result = ADDDI (tmp_prod, tmp_mac); |
| 2350 | { |
| 2351 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 2352 | SET_H_MAC_MACHI (opval); |
| 2353 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 2354 | } |
| 2355 | { |
| 2356 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 2357 | SET_H_MAC_MACLO (opval); |
| 2358 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 2359 | } |
| 2360 | { |
| 2361 | BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); |
| 2362 | SET_H_SYS_SR_OV (opval); |
| 2363 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 2364 | } |
| 2365 | } |
| 2366 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 2367 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 2368 | } |
| 2369 | } |
| 2370 | |
| 2371 | #undef FLD |
| 2372 | } |
| 2373 | NEXT (vpc); |
| 2374 | |
| 2375 | CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */ |
| 2376 | { |
| 2377 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2378 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2379 | #define FLD(f) abuf->fields.sfmt_l_lwz.f |
| 2380 | int UNUSED written = 0; |
| 2381 | IADDR UNUSED pc = abuf->addr; |
| 2382 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2383 | |
| 2384 | { |
| 2385 | { |
| 2386 | DI tmp_prod; |
| 2387 | DI tmp_mac; |
| 2388 | DI tmp_result; |
| 2389 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (FLD (f_simm16))); |
| 2390 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); |
| 2391 | tmp_result = ADDDI (tmp_mac, tmp_prod); |
| 2392 | { |
| 2393 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 2394 | SET_H_MAC_MACHI (opval); |
| 2395 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 2396 | } |
| 2397 | { |
| 2398 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 2399 | SET_H_MAC_MACLO (opval); |
| 2400 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 2401 | } |
| 2402 | { |
| 2403 | BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); |
| 2404 | SET_H_SYS_SR_OV (opval); |
| 2405 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 2406 | } |
| 2407 | } |
| 2408 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 2409 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 2410 | } |
| 2411 | } |
| 2412 | |
| 2413 | #undef FLD |
| 2414 | } |
| 2415 | NEXT (vpc); |
| 2416 | |
| 2417 | CASE (sem, INSN_L_MACU) : /* l.macu $rA,$rB */ |
| 2418 | { |
| 2419 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2420 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2421 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2422 | int UNUSED written = 0; |
| 2423 | IADDR UNUSED pc = abuf->addr; |
| 2424 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2425 | |
| 2426 | { |
| 2427 | { |
| 2428 | DI tmp_prod; |
| 2429 | DI tmp_mac; |
| 2430 | DI tmp_result; |
| 2431 | tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); |
| 2432 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); |
| 2433 | tmp_result = ADDDI (tmp_prod, tmp_mac); |
| 2434 | { |
| 2435 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 2436 | SET_H_MAC_MACHI (opval); |
| 2437 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 2438 | } |
| 2439 | { |
| 2440 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 2441 | SET_H_MAC_MACLO (opval); |
| 2442 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 2443 | } |
| 2444 | { |
| 2445 | BI opval = ADDCFDI (tmp_prod, tmp_mac, 0); |
| 2446 | SET_H_SYS_SR_CY (opval); |
| 2447 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 2448 | } |
| 2449 | } |
| 2450 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { |
| 2451 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 2452 | } |
| 2453 | } |
| 2454 | |
| 2455 | #undef FLD |
| 2456 | } |
| 2457 | NEXT (vpc); |
| 2458 | |
| 2459 | CASE (sem, INSN_L_MSB) : /* l.msb $rA,$rB */ |
| 2460 | { |
| 2461 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2462 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2463 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2464 | int UNUSED written = 0; |
| 2465 | IADDR UNUSED pc = abuf->addr; |
| 2466 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2467 | |
| 2468 | { |
| 2469 | { |
| 2470 | DI tmp_prod; |
| 2471 | DI tmp_mac; |
| 2472 | DI tmp_result; |
| 2473 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); |
| 2474 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); |
| 2475 | tmp_result = SUBDI (tmp_mac, tmp_prod); |
| 2476 | { |
| 2477 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 2478 | SET_H_MAC_MACHI (opval); |
| 2479 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 2480 | } |
| 2481 | { |
| 2482 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 2483 | SET_H_MAC_MACLO (opval); |
| 2484 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 2485 | } |
| 2486 | { |
| 2487 | BI opval = SUBOFDI (tmp_mac, tmp_result, 0); |
| 2488 | SET_H_SYS_SR_OV (opval); |
| 2489 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
| 2490 | } |
| 2491 | } |
| 2492 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { |
| 2493 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 2494 | } |
| 2495 | } |
| 2496 | |
| 2497 | #undef FLD |
| 2498 | } |
| 2499 | NEXT (vpc); |
| 2500 | |
| 2501 | CASE (sem, INSN_L_MSBU) : /* l.msbu $rA,$rB */ |
| 2502 | { |
| 2503 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2504 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2505 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2506 | int UNUSED written = 0; |
| 2507 | IADDR UNUSED pc = abuf->addr; |
| 2508 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2509 | |
| 2510 | { |
| 2511 | { |
| 2512 | DI tmp_prod; |
| 2513 | DI tmp_mac; |
| 2514 | DI tmp_result; |
| 2515 | tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); |
| 2516 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); |
| 2517 | tmp_result = SUBDI (tmp_mac, tmp_prod); |
| 2518 | { |
| 2519 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 2520 | SET_H_MAC_MACHI (opval); |
| 2521 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); |
| 2522 | } |
| 2523 | { |
| 2524 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 2525 | SET_H_MAC_MACLO (opval); |
| 2526 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); |
| 2527 | } |
| 2528 | { |
| 2529 | BI opval = SUBCFDI (tmp_mac, tmp_result, 0); |
| 2530 | SET_H_SYS_SR_CY (opval); |
| 2531 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
| 2532 | } |
| 2533 | } |
| 2534 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { |
| 2535 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
| 2536 | } |
| 2537 | } |
| 2538 | |
| 2539 | #undef FLD |
| 2540 | } |
| 2541 | NEXT (vpc); |
| 2542 | |
| 2543 | CASE (sem, INSN_L_CUST1) : /* l.cust1 */ |
| 2544 | { |
| 2545 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2546 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2547 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2548 | int UNUSED written = 0; |
| 2549 | IADDR UNUSED pc = abuf->addr; |
| 2550 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2551 | |
| 2552 | ((void) 0); /*nop*/ |
| 2553 | |
| 2554 | #undef FLD |
| 2555 | } |
| 2556 | NEXT (vpc); |
| 2557 | |
| 2558 | CASE (sem, INSN_L_CUST2) : /* l.cust2 */ |
| 2559 | { |
| 2560 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2561 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2562 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2563 | int UNUSED written = 0; |
| 2564 | IADDR UNUSED pc = abuf->addr; |
| 2565 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2566 | |
| 2567 | ((void) 0); /*nop*/ |
| 2568 | |
| 2569 | #undef FLD |
| 2570 | } |
| 2571 | NEXT (vpc); |
| 2572 | |
| 2573 | CASE (sem, INSN_L_CUST3) : /* l.cust3 */ |
| 2574 | { |
| 2575 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2576 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2577 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2578 | int UNUSED written = 0; |
| 2579 | IADDR UNUSED pc = abuf->addr; |
| 2580 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2581 | |
| 2582 | ((void) 0); /*nop*/ |
| 2583 | |
| 2584 | #undef FLD |
| 2585 | } |
| 2586 | NEXT (vpc); |
| 2587 | |
| 2588 | CASE (sem, INSN_L_CUST4) : /* l.cust4 */ |
| 2589 | { |
| 2590 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2591 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2592 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2593 | int UNUSED written = 0; |
| 2594 | IADDR UNUSED pc = abuf->addr; |
| 2595 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2596 | |
| 2597 | ((void) 0); /*nop*/ |
| 2598 | |
| 2599 | #undef FLD |
| 2600 | } |
| 2601 | NEXT (vpc); |
| 2602 | |
| 2603 | CASE (sem, INSN_L_CUST5) : /* l.cust5 */ |
| 2604 | { |
| 2605 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2606 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2607 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2608 | int UNUSED written = 0; |
| 2609 | IADDR UNUSED pc = abuf->addr; |
| 2610 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2611 | |
| 2612 | ((void) 0); /*nop*/ |
| 2613 | |
| 2614 | #undef FLD |
| 2615 | } |
| 2616 | NEXT (vpc); |
| 2617 | |
| 2618 | CASE (sem, INSN_L_CUST6) : /* l.cust6 */ |
| 2619 | { |
| 2620 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2621 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2622 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2623 | int UNUSED written = 0; |
| 2624 | IADDR UNUSED pc = abuf->addr; |
| 2625 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2626 | |
| 2627 | ((void) 0); /*nop*/ |
| 2628 | |
| 2629 | #undef FLD |
| 2630 | } |
| 2631 | NEXT (vpc); |
| 2632 | |
| 2633 | CASE (sem, INSN_L_CUST7) : /* l.cust7 */ |
| 2634 | { |
| 2635 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2636 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2637 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2638 | int UNUSED written = 0; |
| 2639 | IADDR UNUSED pc = abuf->addr; |
| 2640 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2641 | |
| 2642 | ((void) 0); /*nop*/ |
| 2643 | |
| 2644 | #undef FLD |
| 2645 | } |
| 2646 | NEXT (vpc); |
| 2647 | |
| 2648 | CASE (sem, INSN_L_CUST8) : /* l.cust8 */ |
| 2649 | { |
| 2650 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2651 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2652 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 2653 | int UNUSED written = 0; |
| 2654 | IADDR UNUSED pc = abuf->addr; |
| 2655 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2656 | |
| 2657 | ((void) 0); /*nop*/ |
| 2658 | |
| 2659 | #undef FLD |
| 2660 | } |
| 2661 | NEXT (vpc); |
| 2662 | |
| 2663 | CASE (sem, INSN_LF_ADD_S) : /* lf.add.s $rDSF,$rASF,$rBSF */ |
| 2664 | { |
| 2665 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2666 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2667 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2668 | int UNUSED written = 0; |
| 2669 | IADDR UNUSED pc = abuf->addr; |
| 2670 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2671 | |
| 2672 | { |
| 2673 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 2674 | SET_H_FSR (FLD (f_r1), opval); |
| 2675 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); |
| 2676 | } |
| 2677 | |
| 2678 | #undef FLD |
| 2679 | } |
| 2680 | NEXT (vpc); |
| 2681 | |
| 2682 | CASE (sem, INSN_LF_ADD_D32) : /* lf.add.d $rDD32F,$rAD32F,$rBD32F */ |
| 2683 | { |
| 2684 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2685 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2686 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2687 | int UNUSED written = 0; |
| 2688 | IADDR UNUSED pc = abuf->addr; |
| 2689 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2690 | |
| 2691 | { |
| 2692 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 2693 | SET_H_FD32R (FLD (f_rdd32), opval); |
| 2694 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); |
| 2695 | } |
| 2696 | |
| 2697 | #undef FLD |
| 2698 | } |
| 2699 | NEXT (vpc); |
| 2700 | |
| 2701 | CASE (sem, INSN_LF_SUB_S) : /* lf.sub.s $rDSF,$rASF,$rBSF */ |
| 2702 | { |
| 2703 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2704 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2705 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2706 | int UNUSED written = 0; |
| 2707 | IADDR UNUSED pc = abuf->addr; |
| 2708 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2709 | |
| 2710 | { |
| 2711 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 2712 | SET_H_FSR (FLD (f_r1), opval); |
| 2713 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); |
| 2714 | } |
| 2715 | |
| 2716 | #undef FLD |
| 2717 | } |
| 2718 | NEXT (vpc); |
| 2719 | |
| 2720 | CASE (sem, INSN_LF_SUB_D32) : /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */ |
| 2721 | { |
| 2722 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2723 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2724 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2725 | int UNUSED written = 0; |
| 2726 | IADDR UNUSED pc = abuf->addr; |
| 2727 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2728 | |
| 2729 | { |
| 2730 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 2731 | SET_H_FD32R (FLD (f_rdd32), opval); |
| 2732 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); |
| 2733 | } |
| 2734 | |
| 2735 | #undef FLD |
| 2736 | } |
| 2737 | NEXT (vpc); |
| 2738 | |
| 2739 | CASE (sem, INSN_LF_MUL_S) : /* lf.mul.s $rDSF,$rASF,$rBSF */ |
| 2740 | { |
| 2741 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2742 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2743 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2744 | int UNUSED written = 0; |
| 2745 | IADDR UNUSED pc = abuf->addr; |
| 2746 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2747 | |
| 2748 | { |
| 2749 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 2750 | SET_H_FSR (FLD (f_r1), opval); |
| 2751 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); |
| 2752 | } |
| 2753 | |
| 2754 | #undef FLD |
| 2755 | } |
| 2756 | NEXT (vpc); |
| 2757 | |
| 2758 | CASE (sem, INSN_LF_MUL_D32) : /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */ |
| 2759 | { |
| 2760 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2761 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2762 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2763 | int UNUSED written = 0; |
| 2764 | IADDR UNUSED pc = abuf->addr; |
| 2765 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2766 | |
| 2767 | { |
| 2768 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 2769 | SET_H_FD32R (FLD (f_rdd32), opval); |
| 2770 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); |
| 2771 | } |
| 2772 | |
| 2773 | #undef FLD |
| 2774 | } |
| 2775 | NEXT (vpc); |
| 2776 | |
| 2777 | CASE (sem, INSN_LF_DIV_S) : /* lf.div.s $rDSF,$rASF,$rBSF */ |
| 2778 | { |
| 2779 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2780 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2781 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2782 | int UNUSED written = 0; |
| 2783 | IADDR UNUSED pc = abuf->addr; |
| 2784 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2785 | |
| 2786 | { |
| 2787 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 2788 | SET_H_FSR (FLD (f_r1), opval); |
| 2789 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); |
| 2790 | } |
| 2791 | |
| 2792 | #undef FLD |
| 2793 | } |
| 2794 | NEXT (vpc); |
| 2795 | |
| 2796 | CASE (sem, INSN_LF_DIV_D32) : /* lf.div.d $rDD32F,$rAD32F,$rBD32F */ |
| 2797 | { |
| 2798 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2799 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2800 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2801 | int UNUSED written = 0; |
| 2802 | IADDR UNUSED pc = abuf->addr; |
| 2803 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2804 | |
| 2805 | { |
| 2806 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 2807 | SET_H_FD32R (FLD (f_rdd32), opval); |
| 2808 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); |
| 2809 | } |
| 2810 | |
| 2811 | #undef FLD |
| 2812 | } |
| 2813 | NEXT (vpc); |
| 2814 | |
| 2815 | CASE (sem, INSN_LF_REM_S) : /* lf.rem.s $rDSF,$rASF,$rBSF */ |
| 2816 | { |
| 2817 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2818 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2819 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2820 | int UNUSED written = 0; |
| 2821 | IADDR UNUSED pc = abuf->addr; |
| 2822 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2823 | |
| 2824 | { |
| 2825 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 2826 | SET_H_FSR (FLD (f_r1), opval); |
| 2827 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); |
| 2828 | } |
| 2829 | |
| 2830 | #undef FLD |
| 2831 | } |
| 2832 | NEXT (vpc); |
| 2833 | |
| 2834 | CASE (sem, INSN_LF_REM_D32) : /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */ |
| 2835 | { |
| 2836 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2837 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2838 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2839 | int UNUSED written = 0; |
| 2840 | IADDR UNUSED pc = abuf->addr; |
| 2841 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2842 | |
| 2843 | { |
| 2844 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 2845 | SET_H_FD32R (FLD (f_rdd32), opval); |
| 2846 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); |
| 2847 | } |
| 2848 | |
| 2849 | #undef FLD |
| 2850 | } |
| 2851 | NEXT (vpc); |
| 2852 | |
| 2853 | CASE (sem, INSN_LF_ITOF_S) : /* lf.itof.s $rDSF,$rA */ |
| 2854 | { |
| 2855 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2856 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2857 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 2858 | int UNUSED written = 0; |
| 2859 | IADDR UNUSED pc = abuf->addr; |
| 2860 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2861 | |
| 2862 | { |
| 2863 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2)))); |
| 2864 | SET_H_FSR (FLD (f_r1), opval); |
| 2865 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); |
| 2866 | } |
| 2867 | |
| 2868 | #undef FLD |
| 2869 | } |
| 2870 | NEXT (vpc); |
| 2871 | |
| 2872 | CASE (sem, INSN_LF_ITOF_D32) : /* lf.itof.d $rDD32F,$rADI */ |
| 2873 | { |
| 2874 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2875 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2876 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2877 | int UNUSED written = 0; |
| 2878 | IADDR UNUSED pc = abuf->addr; |
| 2879 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2880 | |
| 2881 | { |
| 2882 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_rad32))); |
| 2883 | SET_H_FD32R (FLD (f_rdd32), opval); |
| 2884 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); |
| 2885 | } |
| 2886 | |
| 2887 | #undef FLD |
| 2888 | } |
| 2889 | NEXT (vpc); |
| 2890 | |
| 2891 | CASE (sem, INSN_LF_FTOI_S) : /* lf.ftoi.s $rD,$rASF */ |
| 2892 | { |
| 2893 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2894 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2895 | #define FLD(f) abuf->fields.sfmt_l_slli.f |
| 2896 | int UNUSED written = 0; |
| 2897 | IADDR UNUSED pc = abuf->addr; |
| 2898 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2899 | |
| 2900 | { |
| 2901 | SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2)))); |
| 2902 | SET_H_GPR (FLD (f_r1), opval); |
| 2903 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
| 2904 | } |
| 2905 | |
| 2906 | #undef FLD |
| 2907 | } |
| 2908 | NEXT (vpc); |
| 2909 | |
| 2910 | CASE (sem, INSN_LF_FTOI_D32) : /* lf.ftoi.d $rDDI,$rAD32F */ |
| 2911 | { |
| 2912 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2913 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2914 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2915 | int UNUSED written = 0; |
| 2916 | IADDR UNUSED pc = abuf->addr; |
| 2917 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2918 | |
| 2919 | { |
| 2920 | DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_rad32))); |
| 2921 | SET_H_I64R (FLD (f_rdd32), opval); |
| 2922 | CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval); |
| 2923 | } |
| 2924 | |
| 2925 | #undef FLD |
| 2926 | } |
| 2927 | NEXT (vpc); |
| 2928 | |
| 2929 | CASE (sem, INSN_LF_SFEQ_S) : /* lf.sfeq.s $rASF,$rBSF */ |
| 2930 | { |
| 2931 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2932 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2933 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2934 | int UNUSED written = 0; |
| 2935 | IADDR UNUSED pc = abuf->addr; |
| 2936 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2937 | |
| 2938 | { |
| 2939 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 2940 | SET_H_SYS_SR_F (opval); |
| 2941 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2942 | } |
| 2943 | |
| 2944 | #undef FLD |
| 2945 | } |
| 2946 | NEXT (vpc); |
| 2947 | |
| 2948 | CASE (sem, INSN_LF_SFEQ_D32) : /* lf.sfeq.d $rAD32F,$rBD32F */ |
| 2949 | { |
| 2950 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2951 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2952 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2953 | int UNUSED written = 0; |
| 2954 | IADDR UNUSED pc = abuf->addr; |
| 2955 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2956 | |
| 2957 | { |
| 2958 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 2959 | SET_H_SYS_SR_F (opval); |
| 2960 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2961 | } |
| 2962 | |
| 2963 | #undef FLD |
| 2964 | } |
| 2965 | NEXT (vpc); |
| 2966 | |
| 2967 | CASE (sem, INSN_LF_SFNE_S) : /* lf.sfne.s $rASF,$rBSF */ |
| 2968 | { |
| 2969 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2970 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2971 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 2972 | int UNUSED written = 0; |
| 2973 | IADDR UNUSED pc = abuf->addr; |
| 2974 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2975 | |
| 2976 | { |
| 2977 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 2978 | SET_H_SYS_SR_F (opval); |
| 2979 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2980 | } |
| 2981 | |
| 2982 | #undef FLD |
| 2983 | } |
| 2984 | NEXT (vpc); |
| 2985 | |
| 2986 | CASE (sem, INSN_LF_SFNE_D32) : /* lf.sfne.d $rAD32F,$rBD32F */ |
| 2987 | { |
| 2988 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2989 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2990 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 2991 | int UNUSED written = 0; |
| 2992 | IADDR UNUSED pc = abuf->addr; |
| 2993 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2994 | |
| 2995 | { |
| 2996 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 2997 | SET_H_SYS_SR_F (opval); |
| 2998 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 2999 | } |
| 3000 | |
| 3001 | #undef FLD |
| 3002 | } |
| 3003 | NEXT (vpc); |
| 3004 | |
| 3005 | CASE (sem, INSN_LF_SFGE_S) : /* lf.sfge.s $rASF,$rBSF */ |
| 3006 | { |
| 3007 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3008 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3009 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3010 | int UNUSED written = 0; |
| 3011 | IADDR UNUSED pc = abuf->addr; |
| 3012 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3013 | |
| 3014 | { |
| 3015 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 3016 | SET_H_SYS_SR_F (opval); |
| 3017 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3018 | } |
| 3019 | |
| 3020 | #undef FLD |
| 3021 | } |
| 3022 | NEXT (vpc); |
| 3023 | |
| 3024 | CASE (sem, INSN_LF_SFGE_D32) : /* lf.sfge.d $rAD32F,$rBD32F */ |
| 3025 | { |
| 3026 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3027 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3028 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3029 | int UNUSED written = 0; |
| 3030 | IADDR UNUSED pc = abuf->addr; |
| 3031 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3032 | |
| 3033 | { |
| 3034 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 3035 | SET_H_SYS_SR_F (opval); |
| 3036 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3037 | } |
| 3038 | |
| 3039 | #undef FLD |
| 3040 | } |
| 3041 | NEXT (vpc); |
| 3042 | |
| 3043 | CASE (sem, INSN_LF_SFGT_S) : /* lf.sfgt.s $rASF,$rBSF */ |
| 3044 | { |
| 3045 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3046 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3047 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3048 | int UNUSED written = 0; |
| 3049 | IADDR UNUSED pc = abuf->addr; |
| 3050 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3051 | |
| 3052 | { |
| 3053 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 3054 | SET_H_SYS_SR_F (opval); |
| 3055 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3056 | } |
| 3057 | |
| 3058 | #undef FLD |
| 3059 | } |
| 3060 | NEXT (vpc); |
| 3061 | |
| 3062 | CASE (sem, INSN_LF_SFGT_D32) : /* lf.sfgt.d $rAD32F,$rBD32F */ |
| 3063 | { |
| 3064 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3065 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3066 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3067 | int UNUSED written = 0; |
| 3068 | IADDR UNUSED pc = abuf->addr; |
| 3069 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3070 | |
| 3071 | { |
| 3072 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 3073 | SET_H_SYS_SR_F (opval); |
| 3074 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3075 | } |
| 3076 | |
| 3077 | #undef FLD |
| 3078 | } |
| 3079 | NEXT (vpc); |
| 3080 | |
| 3081 | CASE (sem, INSN_LF_SFLT_S) : /* lf.sflt.s $rASF,$rBSF */ |
| 3082 | { |
| 3083 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3084 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3085 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3086 | int UNUSED written = 0; |
| 3087 | IADDR UNUSED pc = abuf->addr; |
| 3088 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3089 | |
| 3090 | { |
| 3091 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 3092 | SET_H_SYS_SR_F (opval); |
| 3093 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3094 | } |
| 3095 | |
| 3096 | #undef FLD |
| 3097 | } |
| 3098 | NEXT (vpc); |
| 3099 | |
| 3100 | CASE (sem, INSN_LF_SFLT_D32) : /* lf.sflt.d $rAD32F,$rBD32F */ |
| 3101 | { |
| 3102 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3103 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3104 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3105 | int UNUSED written = 0; |
| 3106 | IADDR UNUSED pc = abuf->addr; |
| 3107 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3108 | |
| 3109 | { |
| 3110 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 3111 | SET_H_SYS_SR_F (opval); |
| 3112 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3113 | } |
| 3114 | |
| 3115 | #undef FLD |
| 3116 | } |
| 3117 | NEXT (vpc); |
| 3118 | |
| 3119 | CASE (sem, INSN_LF_SFLE_S) : /* lf.sfle.s $rASF,$rBSF */ |
| 3120 | { |
| 3121 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3122 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3123 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3124 | int UNUSED written = 0; |
| 3125 | IADDR UNUSED pc = abuf->addr; |
| 3126 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3127 | |
| 3128 | { |
| 3129 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 3130 | SET_H_SYS_SR_F (opval); |
| 3131 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3132 | } |
| 3133 | |
| 3134 | #undef FLD |
| 3135 | } |
| 3136 | NEXT (vpc); |
| 3137 | |
| 3138 | CASE (sem, INSN_LF_SFLE_D32) : /* lf.sfle.d $rAD32F,$rBD32F */ |
| 3139 | { |
| 3140 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3141 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3142 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3143 | int UNUSED written = 0; |
| 3144 | IADDR UNUSED pc = abuf->addr; |
| 3145 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3146 | |
| 3147 | { |
| 3148 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 3149 | SET_H_SYS_SR_F (opval); |
| 3150 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3151 | } |
| 3152 | |
| 3153 | #undef FLD |
| 3154 | } |
| 3155 | NEXT (vpc); |
| 3156 | |
| 3157 | CASE (sem, INSN_LF_SFUEQ_S) : /* lf.sfueq.s $rASF,$rBSF */ |
| 3158 | { |
| 3159 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3160 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3161 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3162 | int UNUSED written = 0; |
| 3163 | IADDR UNUSED pc = abuf->addr; |
| 3164 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3165 | |
| 3166 | { |
| 3167 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); |
| 3168 | SET_H_SYS_SR_F (opval); |
| 3169 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3170 | } |
| 3171 | |
| 3172 | #undef FLD |
| 3173 | } |
| 3174 | NEXT (vpc); |
| 3175 | |
| 3176 | CASE (sem, INSN_LF_SFUEQ_D32) : /* lf.sfueq.d $rAD32F,$rBD32F */ |
| 3177 | { |
| 3178 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3179 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3180 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3181 | int UNUSED written = 0; |
| 3182 | IADDR UNUSED pc = abuf->addr; |
| 3183 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3184 | |
| 3185 | { |
| 3186 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); |
| 3187 | SET_H_SYS_SR_F (opval); |
| 3188 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3189 | } |
| 3190 | |
| 3191 | #undef FLD |
| 3192 | } |
| 3193 | NEXT (vpc); |
| 3194 | |
| 3195 | CASE (sem, INSN_LF_SFUNE_S) : /* lf.sfune.s $rASF,$rBSF */ |
| 3196 | { |
| 3197 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3198 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3199 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3200 | int UNUSED written = 0; |
| 3201 | IADDR UNUSED pc = abuf->addr; |
| 3202 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3203 | |
| 3204 | { |
| 3205 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); |
| 3206 | SET_H_SYS_SR_F (opval); |
| 3207 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3208 | } |
| 3209 | |
| 3210 | #undef FLD |
| 3211 | } |
| 3212 | NEXT (vpc); |
| 3213 | |
| 3214 | CASE (sem, INSN_LF_SFUNE_D32) : /* lf.sfune.d $rAD32F,$rBD32F */ |
| 3215 | { |
| 3216 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3217 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3218 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3219 | int UNUSED written = 0; |
| 3220 | IADDR UNUSED pc = abuf->addr; |
| 3221 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3222 | |
| 3223 | { |
| 3224 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); |
| 3225 | SET_H_SYS_SR_F (opval); |
| 3226 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3227 | } |
| 3228 | |
| 3229 | #undef FLD |
| 3230 | } |
| 3231 | NEXT (vpc); |
| 3232 | |
| 3233 | CASE (sem, INSN_LF_SFUGT_S) : /* lf.sfugt.s $rASF,$rBSF */ |
| 3234 | { |
| 3235 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3236 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3237 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3238 | int UNUSED written = 0; |
| 3239 | IADDR UNUSED pc = abuf->addr; |
| 3240 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3241 | |
| 3242 | { |
| 3243 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); |
| 3244 | SET_H_SYS_SR_F (opval); |
| 3245 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3246 | } |
| 3247 | |
| 3248 | #undef FLD |
| 3249 | } |
| 3250 | NEXT (vpc); |
| 3251 | |
| 3252 | CASE (sem, INSN_LF_SFUGT_D32) : /* lf.sfugt.d $rAD32F,$rBD32F */ |
| 3253 | { |
| 3254 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3255 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3256 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3257 | int UNUSED written = 0; |
| 3258 | IADDR UNUSED pc = abuf->addr; |
| 3259 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3260 | |
| 3261 | { |
| 3262 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); |
| 3263 | SET_H_SYS_SR_F (opval); |
| 3264 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3265 | } |
| 3266 | |
| 3267 | #undef FLD |
| 3268 | } |
| 3269 | NEXT (vpc); |
| 3270 | |
| 3271 | CASE (sem, INSN_LF_SFUGE_S) : /* lf.sfuge.s $rASF,$rBSF */ |
| 3272 | { |
| 3273 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3274 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3275 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3276 | int UNUSED written = 0; |
| 3277 | IADDR UNUSED pc = abuf->addr; |
| 3278 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3279 | |
| 3280 | { |
| 3281 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); |
| 3282 | SET_H_SYS_SR_F (opval); |
| 3283 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3284 | } |
| 3285 | |
| 3286 | #undef FLD |
| 3287 | } |
| 3288 | NEXT (vpc); |
| 3289 | |
| 3290 | CASE (sem, INSN_LF_SFUGE_D32) : /* lf.sfuge.d $rAD32F,$rBD32F */ |
| 3291 | { |
| 3292 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3293 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3294 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3295 | int UNUSED written = 0; |
| 3296 | IADDR UNUSED pc = abuf->addr; |
| 3297 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3298 | |
| 3299 | { |
| 3300 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); |
| 3301 | SET_H_SYS_SR_F (opval); |
| 3302 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3303 | } |
| 3304 | |
| 3305 | #undef FLD |
| 3306 | } |
| 3307 | NEXT (vpc); |
| 3308 | |
| 3309 | CASE (sem, INSN_LF_SFULT_S) : /* lf.sfult.s $rASF,$rBSF */ |
| 3310 | { |
| 3311 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3312 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3313 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3314 | int UNUSED written = 0; |
| 3315 | IADDR UNUSED pc = abuf->addr; |
| 3316 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3317 | |
| 3318 | { |
| 3319 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); |
| 3320 | SET_H_SYS_SR_F (opval); |
| 3321 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3322 | } |
| 3323 | |
| 3324 | #undef FLD |
| 3325 | } |
| 3326 | NEXT (vpc); |
| 3327 | |
| 3328 | CASE (sem, INSN_LF_SFULT_D32) : /* lf.sfult.d $rAD32F,$rBD32F */ |
| 3329 | { |
| 3330 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3331 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3332 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3333 | int UNUSED written = 0; |
| 3334 | IADDR UNUSED pc = abuf->addr; |
| 3335 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3336 | |
| 3337 | { |
| 3338 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); |
| 3339 | SET_H_SYS_SR_F (opval); |
| 3340 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3341 | } |
| 3342 | |
| 3343 | #undef FLD |
| 3344 | } |
| 3345 | NEXT (vpc); |
| 3346 | |
| 3347 | CASE (sem, INSN_LF_SFULE_S) : /* lf.sfule.s $rASF,$rBSF */ |
| 3348 | { |
| 3349 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3350 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3351 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3352 | int UNUSED written = 0; |
| 3353 | IADDR UNUSED pc = abuf->addr; |
| 3354 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3355 | |
| 3356 | { |
| 3357 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); |
| 3358 | SET_H_SYS_SR_F (opval); |
| 3359 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3360 | } |
| 3361 | |
| 3362 | #undef FLD |
| 3363 | } |
| 3364 | NEXT (vpc); |
| 3365 | |
| 3366 | CASE (sem, INSN_LF_SFULE_D32) : /* lf.sfule.d $rAD32F,$rBD32F */ |
| 3367 | { |
| 3368 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3369 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3370 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3371 | int UNUSED written = 0; |
| 3372 | IADDR UNUSED pc = abuf->addr; |
| 3373 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3374 | |
| 3375 | { |
| 3376 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); |
| 3377 | SET_H_SYS_SR_F (opval); |
| 3378 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3379 | } |
| 3380 | |
| 3381 | #undef FLD |
| 3382 | } |
| 3383 | NEXT (vpc); |
| 3384 | |
| 3385 | CASE (sem, INSN_LF_SFUN_S) : /* lf.sfun.s $rASF,$rBSF */ |
| 3386 | { |
| 3387 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3388 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3389 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3390 | int UNUSED written = 0; |
| 3391 | IADDR UNUSED pc = abuf->addr; |
| 3392 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3393 | |
| 3394 | { |
| 3395 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); |
| 3396 | SET_H_SYS_SR_F (opval); |
| 3397 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3398 | } |
| 3399 | |
| 3400 | #undef FLD |
| 3401 | } |
| 3402 | NEXT (vpc); |
| 3403 | |
| 3404 | CASE (sem, INSN_LF_SFUN_D32) : /* lf.sfun.d $rAD32F,$rBD32F */ |
| 3405 | { |
| 3406 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3407 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3408 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3409 | int UNUSED written = 0; |
| 3410 | IADDR UNUSED pc = abuf->addr; |
| 3411 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3412 | |
| 3413 | { |
| 3414 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); |
| 3415 | SET_H_SYS_SR_F (opval); |
| 3416 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); |
| 3417 | } |
| 3418 | |
| 3419 | #undef FLD |
| 3420 | } |
| 3421 | NEXT (vpc); |
| 3422 | |
| 3423 | CASE (sem, INSN_LF_MADD_S) : /* lf.madd.s $rDSF,$rASF,$rBSF */ |
| 3424 | { |
| 3425 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3426 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3427 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
| 3428 | int UNUSED written = 0; |
| 3429 | IADDR UNUSED pc = abuf->addr; |
| 3430 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3431 | |
| 3432 | { |
| 3433 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1))); |
| 3434 | SET_H_FSR (FLD (f_r1), opval); |
| 3435 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); |
| 3436 | } |
| 3437 | |
| 3438 | #undef FLD |
| 3439 | } |
| 3440 | NEXT (vpc); |
| 3441 | |
| 3442 | CASE (sem, INSN_LF_MADD_D32) : /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */ |
| 3443 | { |
| 3444 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3445 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3446 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f |
| 3447 | int UNUSED written = 0; |
| 3448 | IADDR UNUSED pc = abuf->addr; |
| 3449 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3450 | |
| 3451 | { |
| 3452 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), GET_H_FD32R (FLD (f_rdd32))); |
| 3453 | SET_H_FD32R (FLD (f_rdd32), opval); |
| 3454 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); |
| 3455 | } |
| 3456 | |
| 3457 | #undef FLD |
| 3458 | } |
| 3459 | NEXT (vpc); |
| 3460 | |
| 3461 | CASE (sem, INSN_LF_CUST1_S) : /* lf.cust1.s $rASF,$rBSF */ |
| 3462 | { |
| 3463 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3464 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3465 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 3466 | int UNUSED written = 0; |
| 3467 | IADDR UNUSED pc = abuf->addr; |
| 3468 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3469 | |
| 3470 | ((void) 0); /*nop*/ |
| 3471 | |
| 3472 | #undef FLD |
| 3473 | } |
| 3474 | NEXT (vpc); |
| 3475 | |
| 3476 | CASE (sem, INSN_LF_CUST1_D32) : /* lf.cust1.d */ |
| 3477 | { |
| 3478 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3479 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3480 | #define FLD(f) abuf->fields.sfmt_empty.f |
| 3481 | int UNUSED written = 0; |
| 3482 | IADDR UNUSED pc = abuf->addr; |
| 3483 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3484 | |
| 3485 | ((void) 0); /*nop*/ |
| 3486 | |
| 3487 | #undef FLD |
| 3488 | } |
| 3489 | NEXT (vpc); |
| 3490 | |
| 3491 | |
| 3492 | } |
| 3493 | ENDSWITCH (sem) /* End of semantic switch. */ |
| 3494 | |
| 3495 | /* At this point `vpc' contains the next insn to execute. */ |
| 3496 | } |
| 3497 | |
| 3498 | #undef DEFINE_SWITCH |
| 3499 | #endif /* DEFINE_SWITCH */ |