| 1 | /* This file is part of the program psim. |
| 2 | |
| 3 | Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the Free Software |
| 17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 18 | |
| 19 | */ |
| 20 | |
| 21 | |
| 22 | #ifndef _CPU_H_ |
| 23 | #define _CPU_H_ |
| 24 | |
| 25 | #ifndef INLINE_CPU |
| 26 | #define INLINE_CPU |
| 27 | #endif |
| 28 | |
| 29 | #include "basics.h" |
| 30 | #include "registers.h" |
| 31 | #include "device_tree.h" |
| 32 | #include "corefile.h" |
| 33 | #include "vm.h" |
| 34 | #include "events.h" |
| 35 | #include "interrupts.h" |
| 36 | #include "psim.h" |
| 37 | #include "icache.h" |
| 38 | #include "itable.h" |
| 39 | #include "mon.h" |
| 40 | #include "model.h" |
| 41 | |
| 42 | #ifndef CONST_ATTRIBUTE |
| 43 | #define CONST_ATTRIBUTE __attribute__((__const__)) |
| 44 | #endif |
| 45 | |
| 46 | /* typedef struct _cpu cpu; |
| 47 | |
| 48 | Declared in basics.h because it is used opaquely throughout the |
| 49 | code */ |
| 50 | |
| 51 | |
| 52 | /* Create a cpu object */ |
| 53 | |
| 54 | INLINE_CPU cpu *cpu_create |
| 55 | (psim *system, |
| 56 | core *memory, |
| 57 | event_queue *events, |
| 58 | cpu_mon *monitor, |
| 59 | int cpu_nr); |
| 60 | |
| 61 | INLINE_CPU void cpu_init |
| 62 | (cpu *processor); |
| 63 | |
| 64 | /* Find our way home */ |
| 65 | |
| 66 | INLINE_CPU psim *cpu_system |
| 67 | (cpu *processor) CONST_ATTRIBUTE; |
| 68 | |
| 69 | INLINE_CPU cpu_mon *cpu_monitor |
| 70 | (cpu *processor) CONST_ATTRIBUTE; |
| 71 | |
| 72 | INLINE_CPU int cpu_nr |
| 73 | (cpu *processor) CONST_ATTRIBUTE; |
| 74 | |
| 75 | INLINE_CPU event_queue *cpu_event_queue |
| 76 | (cpu *processor); |
| 77 | |
| 78 | |
| 79 | /* The processors local concept of time */ |
| 80 | |
| 81 | INLINE_CPU signed64 cpu_get_time_base |
| 82 | (cpu *processor); |
| 83 | |
| 84 | INLINE_CPU void cpu_set_time_base |
| 85 | (cpu *processor, |
| 86 | signed64 time_base); |
| 87 | |
| 88 | INLINE_CPU signed32 cpu_get_decrementer |
| 89 | (cpu *processor); |
| 90 | |
| 91 | INLINE_CPU void cpu_set_decrementer |
| 92 | (cpu *processor, |
| 93 | signed32 decrementer); |
| 94 | |
| 95 | |
| 96 | /* manipulate the program counter |
| 97 | |
| 98 | The program counter is not included in the register file. Instead |
| 99 | it is extracted and then later restored (set, reset, halt). This |
| 100 | is to give the user of the cpu (and the compiler) the chance to |
| 101 | minimize the need to load/store the cpu's PC value. (Especially in |
| 102 | the case of a single processor) */ |
| 103 | |
| 104 | INLINE_CPU void cpu_set_program_counter |
| 105 | (cpu *processor, |
| 106 | unsigned_word new_program_counter); |
| 107 | |
| 108 | INLINE_CPU unsigned_word cpu_get_program_counter |
| 109 | (cpu *processor); |
| 110 | |
| 111 | INLINE_CPU void cpu_restart |
| 112 | (cpu *processor, |
| 113 | unsigned_word nia); |
| 114 | |
| 115 | INLINE_CPU void cpu_halt |
| 116 | (cpu *processor, |
| 117 | unsigned_word nia, |
| 118 | stop_reason reason, |
| 119 | int signal); |
| 120 | |
| 121 | |
| 122 | #if WITH_IDECODE_CACHE_SIZE |
| 123 | /* Return the cache entry that matches the given CIA. No guarentee |
| 124 | that the cache entry actually contains the instruction for that |
| 125 | address */ |
| 126 | |
| 127 | INLINE_CPU idecode_cache *cpu_icache_entry |
| 128 | (cpu *processor, |
| 129 | unsigned_word cia); |
| 130 | |
| 131 | INLINE_CPU void cpu_flush_icache |
| 132 | (cpu *processor); |
| 133 | #endif |
| 134 | |
| 135 | |
| 136 | /* reveal the processors VM: |
| 137 | |
| 138 | At first sight it may seem better to, instead of exposing the cpu's |
| 139 | inner vm maps, to have the cpu its self provide memory manipulation |
| 140 | functions. (eg cpu_instruction_fetch() cpu_data_read_4()) |
| 141 | |
| 142 | Unfortunatly in addition to these functions is the need (for the |
| 143 | debugger) to be able to read/write to memory in ways that violate |
| 144 | the vm protection (eg store breakpoint instruction in the |
| 145 | instruction map). */ |
| 146 | |
| 147 | INLINE_CPU vm_data_map *cpu_data_map |
| 148 | (cpu *processor); |
| 149 | |
| 150 | INLINE_CPU vm_instruction_map *cpu_instruction_map |
| 151 | (cpu *processor); |
| 152 | |
| 153 | |
| 154 | /* grant access to the reservation information */ |
| 155 | typedef struct _memory_reservation { |
| 156 | int valid; |
| 157 | unsigned_word addr; |
| 158 | unsigned_word data; |
| 159 | } memory_reservation; |
| 160 | |
| 161 | INLINE_CPU memory_reservation *cpu_reservation |
| 162 | (cpu *processor); |
| 163 | |
| 164 | |
| 165 | INLINE_CPU void cpu_print_info |
| 166 | (cpu *processor, |
| 167 | int verbose); |
| 168 | |
| 169 | |
| 170 | /* Registers: |
| 171 | |
| 172 | This model exploits the PowerPC's requirement for a synchronization |
| 173 | to occure after (or before) the update of any context controlling |
| 174 | register. All context sync points must call the sync function |
| 175 | below to when ever a synchronization point is reached */ |
| 176 | |
| 177 | INLINE_CPU registers *cpu_registers |
| 178 | (cpu *processor) CONST_ATTRIBUTE; |
| 179 | |
| 180 | INLINE_CPU void cpu_synchronize_context |
| 181 | (cpu *processor); |
| 182 | |
| 183 | INLINE_CPU model_data *cpu_model |
| 184 | (cpu *processor) CONST_ATTRIBUTE; |
| 185 | |
| 186 | #define IS_PROBLEM_STATE(PROCESSOR) \ |
| 187 | (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ |
| 188 | ? (cpu_registers(PROCESSOR)->msr & msr_problem_state) \ |
| 189 | : 1) |
| 190 | |
| 191 | #define IS_64BIT_MODE(PROCESSOR) \ |
| 192 | (WITH_TARGET_WORD_BITSIZE == 64 \ |
| 193 | ? (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ |
| 194 | ? (cpu_registers(PROCESSOR)->msr & msr_64bit_mode) \ |
| 195 | : 1) \ |
| 196 | : 0) |
| 197 | |
| 198 | #define IS_FP_AVAILABLE(PROCESSOR) \ |
| 199 | (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ |
| 200 | ? (cpu_registers(PROCESSOR)->msr & msr_floating_point_available) \ |
| 201 | : 1) |
| 202 | |
| 203 | #endif |