| 1 | /* e500 expression macros, for PSIM, the PowerPC simulator. |
| 2 | |
| 3 | Copyright 2003-2013 Free Software Foundation, Inc. |
| 4 | |
| 5 | Contributed by Red Hat Inc; developed under contract from Motorola. |
| 6 | Written by matthew green <mrg@redhat.com>. |
| 7 | |
| 8 | This file is part of GDB. |
| 9 | |
| 10 | This program is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by |
| 12 | the Free Software Foundation; either version 3 of the License, or |
| 13 | (at your option) any later version. |
| 14 | |
| 15 | This program is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | GNU General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU General Public License |
| 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 22 | |
| 23 | /* e500 register dance */ |
| 24 | #define EV_SET_REG4(sh, sl, h0, h1, h2, h3) do { \ |
| 25 | (sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \ |
| 26 | (sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \ |
| 27 | } while (0) |
| 28 | #define EV_SET_REG4_ACC(sh, sl, h0, h1, h2, h3) do { \ |
| 29 | (sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \ |
| 30 | (sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \ |
| 31 | ACC = ((unsigned64)(sh) << 32) | (sl & 0xffffffff); \ |
| 32 | } while (0) |
| 33 | |
| 34 | #define EV_SET_REG2(sh, sl, dh, dl) do { \ |
| 35 | (sh) = (dh) & 0xffffffff; \ |
| 36 | (sl) = (dl) & 0xffffffff; \ |
| 37 | } while (0) |
| 38 | #define EV_SET_REG2_ACC(sh, sl, dh, dl) do { \ |
| 39 | (sh) = (dh) & 0xffffffff; \ |
| 40 | (sl) = (dl) & 0xffffffff; \ |
| 41 | ACC = ((unsigned64)(sh) << 32) | ((sl) & 0xffffffff); \ |
| 42 | } while (0) |
| 43 | |
| 44 | #define EV_SET_REG1(sh, sl, d) do { \ |
| 45 | (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \ |
| 46 | (sl) = (d) & 0xffffffff; \ |
| 47 | } while (0) |
| 48 | #define EV_SET_REG1_ACC(sh, sl, d) do { \ |
| 49 | (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \ |
| 50 | (sl) = (d) & 0xffffffff; \ |
| 51 | ACC = (d); \ |
| 52 | } while (0) |
| 53 | |
| 54 | #define EV_SET_REG(s, d) do { \ |
| 55 | (s) = (d) & 0xffffffff; \ |
| 56 | } while (0) |
| 57 | |
| 58 | /* get the low or high half word of a word */ |
| 59 | #define EV_LOHALF(x) ((unsigned32)(x) & 0xffff) |
| 60 | #define EV_HIHALF(x) (((unsigned32)(x) >> 16) & 0xffff) |
| 61 | |
| 62 | /* partially visible accumulator accessors */ |
| 63 | #define EV_SET_ACC(rh, rl) \ |
| 64 | ACC = ((unsigned64)(rh) << 32) | ((rl) & 0xffffffff) |
| 65 | |
| 66 | #define EV_ACCLOW (ACC & 0xffffffff) |
| 67 | #define EV_ACCHIGH ((ACC >> 32) & 0xffffffff) |
| 68 | |
| 69 | /* bit manipulation macros needed for e500 SPE */ |
| 70 | #define EV_BITREVERSE16(x) \ |
| 71 | (((x) & 0x0001) << 15) \ |
| 72 | | (((x) & 0x0002) << 13) \ |
| 73 | | (((x) & 0x0004) << 11) \ |
| 74 | | (((x) & 0x0008) << 9) \ |
| 75 | | (((x) & 0x0010) << 7) \ |
| 76 | | (((x) & 0x0020) << 5) \ |
| 77 | | (((x) & 0x0040) << 3) \ |
| 78 | | (((x) & 0x0080) << 1) \ |
| 79 | | (((x) & 0x0100) >> 1) \ |
| 80 | | (((x) & 0x0200) >> 3) \ |
| 81 | | (((x) & 0x0400) >> 5) \ |
| 82 | | (((x) & 0x0800) >> 7) \ |
| 83 | | (((x) & 0x1000) >> 9) \ |
| 84 | | (((x) & 0x2000) >> 11) \ |
| 85 | | (((x) & 0x4000) >> 13) \ |
| 86 | | (((x) & 0x8000) >> 15) |
| 87 | |
| 88 | /* saturation helpers */ |
| 89 | #define EV_MUL16_SSF(a,b) ((signed64)((signed32)(signed16)(a) * (signed32)(signed16)(b)) << 1) |
| 90 | /* this one loses the top sign bit; be careful */ |
| 91 | #define EV_MUL32_SSF(a,b) (((signed64)(signed32)(a) * (signed64)(signed32)(b)) << 1) |
| 92 | #define EV_SAT_P_S32(x) ((((signed64)(x)) < -0x80000000LL) || (((signed64)(x)) > 0x7fffffffLL)) |
| 93 | #define EV_SAT_P_U32(x) ((((signed64)(x)) < -0LL) || (((signed64)(x)) > 0xffffffffLL)) |
| 94 | |
| 95 | #define EV_SATURATE(flag, sat_val, val) \ |
| 96 | ((flag) ? (sat_val) : (val)) |
| 97 | |
| 98 | #define EV_SATURATE_ACC(flag, sign, negative_sat_val, positive_sat_val, val) \ |
| 99 | ((flag) ? ((((sign) >> 63) & 1) ? (negative_sat_val) : (positive_sat_val)) : (val)) |
| 100 | |
| 101 | /* SPEFSCR handling. */ |
| 102 | |
| 103 | /* These bits must be clear. */ |
| 104 | #define EV_SPEFSCR_MASK (BIT(40) | BIT(41) | spefscr_mode | BIT(56)) |
| 105 | |
| 106 | /* The Inexact and Divide by zero sticky bits are based on others. */ |
| 107 | #define EV_SET_SPEFSCR(bits) do { \ |
| 108 | int finxs = (bits) & (spefscr_fgh|spefscr_fxh|spefscr_fg|spefscr_fx); \ |
| 109 | int fdbzs = (bits) & (spefscr_fdbzh|spefscr_fdbz); \ |
| 110 | SPREG(spr_spefscr) = ((bits) & ~EV_SPEFSCR_MASK) | \ |
| 111 | (finxs ? spefscr_finxs : 0) | \ |
| 112 | (fdbzs ? spefscr_fdbzs : 0); \ |
| 113 | } while (0) |
| 114 | |
| 115 | #define EV_SET_SPEFSCR_BITS(s) \ |
| 116 | EV_SET_SPEFSCR(SPREG(spr_spefscr) | (s)) |
| 117 | |
| 118 | #define EV_SET_SPEFSCR_OV(l,h) do { \ |
| 119 | unsigned32 _sPefScR = SPREG(spr_spefscr); \ |
| 120 | if (l) \ |
| 121 | _sPefScR |= spefscr_ov | spefscr_sov; \ |
| 122 | else \ |
| 123 | _sPefScR &= ~spefscr_ov; \ |
| 124 | if (h) \ |
| 125 | _sPefScR |= spefscr_ovh | spefscr_sovh; \ |
| 126 | else \ |
| 127 | _sPefScR &= ~spefscr_ovh; \ |
| 128 | EV_SET_SPEFSCR(_sPefScR); \ |
| 129 | } while (0) |
| 130 | |
| 131 | /* SPE floating point helpers. */ |
| 132 | |
| 133 | #define EV_PMAX 0x7f7fffff |
| 134 | #define EV_NMAX 0xff7fffff |
| 135 | #define EV_PMIN 0x00800001 |
| 136 | #define EV_NMIN 0x80800001 |
| 137 | |
| 138 | #define EV_IS_INFDENORMNAN(x) \ |
| 139 | (sim_fpu_is_infinity(x) || sim_fpu_is_denorm(x) || sim_fpu_is_nan(x)) |
| 140 | |
| 141 | /* These aren't used (yet?) For now, SPU is always enabled. |
| 142 | Would be nice if they were generated by igen for e500. */ |
| 143 | #define SPU_BEGIN \ |
| 144 | { \ |
| 145 | if (MSR & msr_e500_spu_enable) { \ |
| 146 | |
| 147 | #define SPU_END \ |
| 148 | } else { \ |
| 149 | /* FIXME: raise SPU unavailable. */ \ |
| 150 | } \ |
| 151 | } |
| 152 | |
| 153 | /* These are also not yet used. */ |
| 154 | #define SPU_FP_BEGIN \ |
| 155 | { |
| 156 | |
| 157 | #define SPU_FP_END \ |
| 158 | { \ |
| 159 | unsigned s = SPEFSCR; \ |
| 160 | /* Check SPEFSCR; raise exceptions if any required. */ \ |
| 161 | if (((spefscr_finxe || spefscr_finve) \ |
| 162 | && (s & (spefscr_finvh|spefscr_finv))) \ |
| 163 | || ((spefscr_finxe || spefscr_fdbze) \ |
| 164 | && (s & (spefscr_fdbzh|spefscr_fdbz))) \ |
| 165 | || ((spefscr_finxe || spefscr_funfe) \ |
| 166 | && (s & (spefscr_funfh|spefscr_funf))) \ |
| 167 | || ((spefscr_finxe || spefscr_fovfe) \ |
| 168 | && (s & (spefscr_fovfh|spefscr_fovf)))) \ |
| 169 | /* FIXME: raise exceptions. */; \ |
| 170 | } \ |
| 171 | } |