| 1 | /* CPU family header for sh64. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2013 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU simulators. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | |
| 22 | */ |
| 23 | |
| 24 | #ifndef CPU_SH64_H |
| 25 | #define CPU_SH64_H |
| 26 | |
| 27 | /* Maximum number of instructions that are fetched at a time. |
| 28 | This is for LIW type instructions sets (e.g. m32r). */ |
| 29 | #define MAX_LIW_INSNS 1 |
| 30 | |
| 31 | /* Maximum number of instructions that can be executed in parallel. */ |
| 32 | #define MAX_PARALLEL_INSNS 1 |
| 33 | |
| 34 | /* The size of an "int" needed to hold an instruction word. |
| 35 | This is usually 32 bits, but some architectures needs 64 bits. */ |
| 36 | typedef CGEN_INSN_INT CGEN_INSN_WORD; |
| 37 | |
| 38 | #include "cgen-engine.h" |
| 39 | |
| 40 | /* CPU state information. */ |
| 41 | typedef struct { |
| 42 | /* Hardware elements. */ |
| 43 | struct { |
| 44 | /* Program counter */ |
| 45 | UDI h_pc; |
| 46 | #define GET_H_PC() CPU (h_pc) |
| 47 | #define SET_H_PC(x) \ |
| 48 | do { \ |
| 49 | {\ |
| 50 | CPU (h_ism) = ANDDI ((x), 1);\ |
| 51 | CPU (h_pc) = ANDDI ((x), INVDI (1));\ |
| 52 | }\ |
| 53 | ;} while (0) |
| 54 | /* General purpose integer registers */ |
| 55 | DI h_gr[64]; |
| 56 | #define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index]))) |
| 57 | #define SET_H_GR(index, x) \ |
| 58 | do { \ |
| 59 | if ((((index)) != (63))) {\ |
| 60 | CPU (h_gr[(index)]) = (x);\ |
| 61 | } else {\ |
| 62 | ((void) 0); /*nop*/\ |
| 63 | }\ |
| 64 | ;} while (0) |
| 65 | /* Control registers */ |
| 66 | DI h_cr[64]; |
| 67 | #define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index]))) |
| 68 | #define SET_H_CR(index, x) \ |
| 69 | do { \ |
| 70 | if ((((index)) == (0))) {\ |
| 71 | CPU (h_sr) = (x);\ |
| 72 | } else {\ |
| 73 | CPU (h_cr[(index)]) = (x);\ |
| 74 | }\ |
| 75 | ;} while (0) |
| 76 | /* Status register */ |
| 77 | SI h_sr; |
| 78 | #define GET_H_SR() CPU (h_sr) |
| 79 | #define SET_H_SR(x) (CPU (h_sr) = (x)) |
| 80 | /* Floating point status and control register */ |
| 81 | SI h_fpscr; |
| 82 | #define GET_H_FPSCR() CPU (h_fpscr) |
| 83 | #define SET_H_FPSCR(x) (CPU (h_fpscr) = (x)) |
| 84 | /* Single precision floating point registers */ |
| 85 | SF h_fr[64]; |
| 86 | #define GET_H_FR(a1) CPU (h_fr)[a1] |
| 87 | #define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) |
| 88 | /* Single/Double precision floating point registers */ |
| 89 | DF h_fsd[16]; |
| 90 | #define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, CPU (h_fr[index])))) |
| 91 | #define SET_H_FSD(index, x) \ |
| 92 | do { \ |
| 93 | if (GET_H_PRBIT ()) {\ |
| 94 | SET_H_DRC ((index), (x));\ |
| 95 | } else {\ |
| 96 | SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ |
| 97 | }\ |
| 98 | ;} while (0) |
| 99 | /* floating point registers for fmov */ |
| 100 | DF h_fmov[16]; |
| 101 | #define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index))))) |
| 102 | #define SET_H_FMOV(index, x) \ |
| 103 | do { \ |
| 104 | if (NOTBI (GET_H_SZBIT ())) {\ |
| 105 | SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ |
| 106 | } else {\ |
| 107 | if ((((((index)) & (1))) == (1))) {\ |
| 108 | SET_H_XD ((((index)) & ((~ (1)))), (x));\ |
| 109 | } else {\ |
| 110 | SET_H_DR ((index), (x));\ |
| 111 | }\ |
| 112 | }\ |
| 113 | ;} while (0) |
| 114 | /* Branch target registers */ |
| 115 | DI h_tr[8]; |
| 116 | #define GET_H_TR(a1) CPU (h_tr)[a1] |
| 117 | #define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x)) |
| 118 | /* Current instruction set mode */ |
| 119 | BI h_ism; |
| 120 | #define GET_H_ISM() CPU (h_ism) |
| 121 | #define SET_H_ISM(x) \ |
| 122 | do { \ |
| 123 | cgen_rtx_error (current_cpu, "cannot set ism directly");\ |
| 124 | ;} while (0) |
| 125 | } hardware; |
| 126 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) |
| 127 | } SH64_CPU_DATA; |
| 128 | |
| 129 | /* Virtual regs. */ |
| 130 | |
| 131 | #define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff)) |
| 132 | #define SET_H_GRC(index, x) \ |
| 133 | do { \ |
| 134 | CPU (h_gr[(index)]) = EXTSIDI ((x));\ |
| 135 | ;} while (0) |
| 136 | #define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1) |
| 137 | #define SET_H_FRBIT(x) \ |
| 138 | do { \ |
| 139 | CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\ |
| 140 | ;} while (0) |
| 141 | #define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1) |
| 142 | #define SET_H_SZBIT(x) \ |
| 143 | do { \ |
| 144 | CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\ |
| 145 | ;} while (0) |
| 146 | #define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1) |
| 147 | #define SET_H_PRBIT(x) \ |
| 148 | do { \ |
| 149 | CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\ |
| 150 | ;} while (0) |
| 151 | #define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1) |
| 152 | #define SET_H_SBIT(x) \ |
| 153 | do { \ |
| 154 | CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\ |
| 155 | ;} while (0) |
| 156 | #define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1) |
| 157 | #define SET_H_MBIT(x) \ |
| 158 | do { \ |
| 159 | CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\ |
| 160 | ;} while (0) |
| 161 | #define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1) |
| 162 | #define SET_H_QBIT(x) \ |
| 163 | do { \ |
| 164 | CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\ |
| 165 | ;} while (0) |
| 166 | #define GET_H_FP(index) CPU (h_fr[index]) |
| 167 | #define SET_H_FP(index, x) \ |
| 168 | do { \ |
| 169 | CPU (h_fr[(index)]) = (x);\ |
| 170 | ;} while (0) |
| 171 | #define GET_H_FV(index) CPU (h_fr[index]) |
| 172 | #define SET_H_FV(index, x) \ |
| 173 | do { \ |
| 174 | CPU (h_fr[(index)]) = (x);\ |
| 175 | ;} while (0) |
| 176 | #define GET_H_FMTX(index) CPU (h_fr[index]) |
| 177 | #define SET_H_FMTX(index, x) \ |
| 178 | do { \ |
| 179 | CPU (h_fr[(index)]) = (x);\ |
| 180 | ;} while (0) |
| 181 | #define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))]))))) |
| 182 | #define SET_H_DR(index, x) \ |
| 183 | do { \ |
| 184 | {\ |
| 185 | CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\ |
| 186 | CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\ |
| 187 | }\ |
| 188 | ;} while (0) |
| 189 | #define GET_H_ENDIAN() sh64_endian (current_cpu) |
| 190 | #define SET_H_ENDIAN(x) \ |
| 191 | do { \ |
| 192 | cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\ |
| 193 | ;} while (0) |
| 194 | #define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) |
| 195 | #define SET_H_FRC(index, x) \ |
| 196 | do { \ |
| 197 | CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ |
| 198 | ;} while (0) |
| 199 | #define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index))) |
| 200 | #define SET_H_DRC(index, x) \ |
| 201 | do { \ |
| 202 | SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\ |
| 203 | ;} while (0) |
| 204 | #define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))]) |
| 205 | #define SET_H_XF(index, x) \ |
| 206 | do { \ |
| 207 | CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\ |
| 208 | ;} while (0) |
| 209 | #define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))) |
| 210 | #define SET_H_XD(index, x) \ |
| 211 | do { \ |
| 212 | SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\ |
| 213 | ;} while (0) |
| 214 | #define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) |
| 215 | #define SET_H_FVC(index, x) \ |
| 216 | do { \ |
| 217 | CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ |
| 218 | ;} while (0) |
| 219 | #define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) |
| 220 | #define SET_H_GBR(x) \ |
| 221 | do { \ |
| 222 | CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ |
| 223 | ;} while (0) |
| 224 | #define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) |
| 225 | #define SET_H_VBR(x) \ |
| 226 | do { \ |
| 227 | CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ |
| 228 | ;} while (0) |
| 229 | #define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1) |
| 230 | #define SET_H_PR(x) \ |
| 231 | do { \ |
| 232 | CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\ |
| 233 | ;} while (0) |
| 234 | #define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1) |
| 235 | #define SET_H_MACL(x) \ |
| 236 | do { \ |
| 237 | CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\ |
| 238 | ;} while (0) |
| 239 | #define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0) |
| 240 | #define SET_H_MACH(x) \ |
| 241 | do { \ |
| 242 | CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\ |
| 243 | ;} while (0) |
| 244 | #define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1) |
| 245 | #define SET_H_TBIT(x) \ |
| 246 | do { \ |
| 247 | CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\ |
| 248 | ;} while (0) |
| 249 | |
| 250 | /* Cover fns for register access. */ |
| 251 | UDI sh64_h_pc_get (SIM_CPU *); |
| 252 | void sh64_h_pc_set (SIM_CPU *, UDI); |
| 253 | DI sh64_h_gr_get (SIM_CPU *, UINT); |
| 254 | void sh64_h_gr_set (SIM_CPU *, UINT, DI); |
| 255 | SI sh64_h_grc_get (SIM_CPU *, UINT); |
| 256 | void sh64_h_grc_set (SIM_CPU *, UINT, SI); |
| 257 | DI sh64_h_cr_get (SIM_CPU *, UINT); |
| 258 | void sh64_h_cr_set (SIM_CPU *, UINT, DI); |
| 259 | SI sh64_h_sr_get (SIM_CPU *); |
| 260 | void sh64_h_sr_set (SIM_CPU *, SI); |
| 261 | SI sh64_h_fpscr_get (SIM_CPU *); |
| 262 | void sh64_h_fpscr_set (SIM_CPU *, SI); |
| 263 | BI sh64_h_frbit_get (SIM_CPU *); |
| 264 | void sh64_h_frbit_set (SIM_CPU *, BI); |
| 265 | BI sh64_h_szbit_get (SIM_CPU *); |
| 266 | void sh64_h_szbit_set (SIM_CPU *, BI); |
| 267 | BI sh64_h_prbit_get (SIM_CPU *); |
| 268 | void sh64_h_prbit_set (SIM_CPU *, BI); |
| 269 | BI sh64_h_sbit_get (SIM_CPU *); |
| 270 | void sh64_h_sbit_set (SIM_CPU *, BI); |
| 271 | BI sh64_h_mbit_get (SIM_CPU *); |
| 272 | void sh64_h_mbit_set (SIM_CPU *, BI); |
| 273 | BI sh64_h_qbit_get (SIM_CPU *); |
| 274 | void sh64_h_qbit_set (SIM_CPU *, BI); |
| 275 | SF sh64_h_fr_get (SIM_CPU *, UINT); |
| 276 | void sh64_h_fr_set (SIM_CPU *, UINT, SF); |
| 277 | SF sh64_h_fp_get (SIM_CPU *, UINT); |
| 278 | void sh64_h_fp_set (SIM_CPU *, UINT, SF); |
| 279 | SF sh64_h_fv_get (SIM_CPU *, UINT); |
| 280 | void sh64_h_fv_set (SIM_CPU *, UINT, SF); |
| 281 | SF sh64_h_fmtx_get (SIM_CPU *, UINT); |
| 282 | void sh64_h_fmtx_set (SIM_CPU *, UINT, SF); |
| 283 | DF sh64_h_dr_get (SIM_CPU *, UINT); |
| 284 | void sh64_h_dr_set (SIM_CPU *, UINT, DF); |
| 285 | DF sh64_h_fsd_get (SIM_CPU *, UINT); |
| 286 | void sh64_h_fsd_set (SIM_CPU *, UINT, DF); |
| 287 | DF sh64_h_fmov_get (SIM_CPU *, UINT); |
| 288 | void sh64_h_fmov_set (SIM_CPU *, UINT, DF); |
| 289 | DI sh64_h_tr_get (SIM_CPU *, UINT); |
| 290 | void sh64_h_tr_set (SIM_CPU *, UINT, DI); |
| 291 | BI sh64_h_endian_get (SIM_CPU *); |
| 292 | void sh64_h_endian_set (SIM_CPU *, BI); |
| 293 | BI sh64_h_ism_get (SIM_CPU *); |
| 294 | void sh64_h_ism_set (SIM_CPU *, BI); |
| 295 | SF sh64_h_frc_get (SIM_CPU *, UINT); |
| 296 | void sh64_h_frc_set (SIM_CPU *, UINT, SF); |
| 297 | DF sh64_h_drc_get (SIM_CPU *, UINT); |
| 298 | void sh64_h_drc_set (SIM_CPU *, UINT, DF); |
| 299 | SF sh64_h_xf_get (SIM_CPU *, UINT); |
| 300 | void sh64_h_xf_set (SIM_CPU *, UINT, SF); |
| 301 | DF sh64_h_xd_get (SIM_CPU *, UINT); |
| 302 | void sh64_h_xd_set (SIM_CPU *, UINT, DF); |
| 303 | SF sh64_h_fvc_get (SIM_CPU *, UINT); |
| 304 | void sh64_h_fvc_set (SIM_CPU *, UINT, SF); |
| 305 | SI sh64_h_gbr_get (SIM_CPU *); |
| 306 | void sh64_h_gbr_set (SIM_CPU *, SI); |
| 307 | SI sh64_h_vbr_get (SIM_CPU *); |
| 308 | void sh64_h_vbr_set (SIM_CPU *, SI); |
| 309 | SI sh64_h_pr_get (SIM_CPU *); |
| 310 | void sh64_h_pr_set (SIM_CPU *, SI); |
| 311 | SI sh64_h_macl_get (SIM_CPU *); |
| 312 | void sh64_h_macl_set (SIM_CPU *, SI); |
| 313 | SI sh64_h_mach_get (SIM_CPU *); |
| 314 | void sh64_h_mach_set (SIM_CPU *, SI); |
| 315 | BI sh64_h_tbit_get (SIM_CPU *); |
| 316 | void sh64_h_tbit_set (SIM_CPU *, BI); |
| 317 | |
| 318 | /* These must be hand-written. */ |
| 319 | extern CPUREG_FETCH_FN sh64_fetch_register; |
| 320 | extern CPUREG_STORE_FN sh64_store_register; |
| 321 | |
| 322 | typedef struct { |
| 323 | int empty; |
| 324 | } MODEL_SH4_DATA; |
| 325 | |
| 326 | typedef struct { |
| 327 | int empty; |
| 328 | } MODEL_SH5_DATA; |
| 329 | |
| 330 | typedef struct { |
| 331 | int empty; |
| 332 | } MODEL_SH5_MEDIA_DATA; |
| 333 | |
| 334 | /* Collection of various things for the trace handler to use. */ |
| 335 | |
| 336 | typedef struct trace_record { |
| 337 | IADDR pc; |
| 338 | /* FIXME:wip */ |
| 339 | } TRACE_RECORD; |
| 340 | |
| 341 | #endif /* CPU_SH64_H */ |