| 1 | /* Simulator instruction semantics for sh64. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2005 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU simulators. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #ifdef DEFINE_LABELS |
| 26 | |
| 27 | /* The labels have the case they have because the enum of insn types |
| 28 | is all uppercase and in the non-stdc case the insn symbol is built |
| 29 | into the enum name. */ |
| 30 | |
| 31 | static struct { |
| 32 | int index; |
| 33 | void *label; |
| 34 | } labels[] = { |
| 35 | { SH64_COMPACT_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, |
| 36 | { SH64_COMPACT_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, |
| 37 | { SH64_COMPACT_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, |
| 38 | { SH64_COMPACT_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, |
| 39 | { SH64_COMPACT_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, |
| 40 | { SH64_COMPACT_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, |
| 41 | { SH64_COMPACT_INSN_ADD_COMPACT, && case_sem_INSN_ADD_COMPACT }, |
| 42 | { SH64_COMPACT_INSN_ADDI_COMPACT, && case_sem_INSN_ADDI_COMPACT }, |
| 43 | { SH64_COMPACT_INSN_ADDC_COMPACT, && case_sem_INSN_ADDC_COMPACT }, |
| 44 | { SH64_COMPACT_INSN_ADDV_COMPACT, && case_sem_INSN_ADDV_COMPACT }, |
| 45 | { SH64_COMPACT_INSN_AND_COMPACT, && case_sem_INSN_AND_COMPACT }, |
| 46 | { SH64_COMPACT_INSN_ANDI_COMPACT, && case_sem_INSN_ANDI_COMPACT }, |
| 47 | { SH64_COMPACT_INSN_ANDB_COMPACT, && case_sem_INSN_ANDB_COMPACT }, |
| 48 | { SH64_COMPACT_INSN_BF_COMPACT, && case_sem_INSN_BF_COMPACT }, |
| 49 | { SH64_COMPACT_INSN_BFS_COMPACT, && case_sem_INSN_BFS_COMPACT }, |
| 50 | { SH64_COMPACT_INSN_BRA_COMPACT, && case_sem_INSN_BRA_COMPACT }, |
| 51 | { SH64_COMPACT_INSN_BRAF_COMPACT, && case_sem_INSN_BRAF_COMPACT }, |
| 52 | { SH64_COMPACT_INSN_BRK_COMPACT, && case_sem_INSN_BRK_COMPACT }, |
| 53 | { SH64_COMPACT_INSN_BSR_COMPACT, && case_sem_INSN_BSR_COMPACT }, |
| 54 | { SH64_COMPACT_INSN_BSRF_COMPACT, && case_sem_INSN_BSRF_COMPACT }, |
| 55 | { SH64_COMPACT_INSN_BT_COMPACT, && case_sem_INSN_BT_COMPACT }, |
| 56 | { SH64_COMPACT_INSN_BTS_COMPACT, && case_sem_INSN_BTS_COMPACT }, |
| 57 | { SH64_COMPACT_INSN_CLRMAC_COMPACT, && case_sem_INSN_CLRMAC_COMPACT }, |
| 58 | { SH64_COMPACT_INSN_CLRS_COMPACT, && case_sem_INSN_CLRS_COMPACT }, |
| 59 | { SH64_COMPACT_INSN_CLRT_COMPACT, && case_sem_INSN_CLRT_COMPACT }, |
| 60 | { SH64_COMPACT_INSN_CMPEQ_COMPACT, && case_sem_INSN_CMPEQ_COMPACT }, |
| 61 | { SH64_COMPACT_INSN_CMPEQI_COMPACT, && case_sem_INSN_CMPEQI_COMPACT }, |
| 62 | { SH64_COMPACT_INSN_CMPGE_COMPACT, && case_sem_INSN_CMPGE_COMPACT }, |
| 63 | { SH64_COMPACT_INSN_CMPGT_COMPACT, && case_sem_INSN_CMPGT_COMPACT }, |
| 64 | { SH64_COMPACT_INSN_CMPHI_COMPACT, && case_sem_INSN_CMPHI_COMPACT }, |
| 65 | { SH64_COMPACT_INSN_CMPHS_COMPACT, && case_sem_INSN_CMPHS_COMPACT }, |
| 66 | { SH64_COMPACT_INSN_CMPPL_COMPACT, && case_sem_INSN_CMPPL_COMPACT }, |
| 67 | { SH64_COMPACT_INSN_CMPPZ_COMPACT, && case_sem_INSN_CMPPZ_COMPACT }, |
| 68 | { SH64_COMPACT_INSN_CMPSTR_COMPACT, && case_sem_INSN_CMPSTR_COMPACT }, |
| 69 | { SH64_COMPACT_INSN_DIV0S_COMPACT, && case_sem_INSN_DIV0S_COMPACT }, |
| 70 | { SH64_COMPACT_INSN_DIV0U_COMPACT, && case_sem_INSN_DIV0U_COMPACT }, |
| 71 | { SH64_COMPACT_INSN_DIV1_COMPACT, && case_sem_INSN_DIV1_COMPACT }, |
| 72 | { SH64_COMPACT_INSN_DIVU_COMPACT, && case_sem_INSN_DIVU_COMPACT }, |
| 73 | { SH64_COMPACT_INSN_MULR_COMPACT, && case_sem_INSN_MULR_COMPACT }, |
| 74 | { SH64_COMPACT_INSN_DMULSL_COMPACT, && case_sem_INSN_DMULSL_COMPACT }, |
| 75 | { SH64_COMPACT_INSN_DMULUL_COMPACT, && case_sem_INSN_DMULUL_COMPACT }, |
| 76 | { SH64_COMPACT_INSN_DT_COMPACT, && case_sem_INSN_DT_COMPACT }, |
| 77 | { SH64_COMPACT_INSN_EXTSB_COMPACT, && case_sem_INSN_EXTSB_COMPACT }, |
| 78 | { SH64_COMPACT_INSN_EXTSW_COMPACT, && case_sem_INSN_EXTSW_COMPACT }, |
| 79 | { SH64_COMPACT_INSN_EXTUB_COMPACT, && case_sem_INSN_EXTUB_COMPACT }, |
| 80 | { SH64_COMPACT_INSN_EXTUW_COMPACT, && case_sem_INSN_EXTUW_COMPACT }, |
| 81 | { SH64_COMPACT_INSN_FABS_COMPACT, && case_sem_INSN_FABS_COMPACT }, |
| 82 | { SH64_COMPACT_INSN_FADD_COMPACT, && case_sem_INSN_FADD_COMPACT }, |
| 83 | { SH64_COMPACT_INSN_FCMPEQ_COMPACT, && case_sem_INSN_FCMPEQ_COMPACT }, |
| 84 | { SH64_COMPACT_INSN_FCMPGT_COMPACT, && case_sem_INSN_FCMPGT_COMPACT }, |
| 85 | { SH64_COMPACT_INSN_FCNVDS_COMPACT, && case_sem_INSN_FCNVDS_COMPACT }, |
| 86 | { SH64_COMPACT_INSN_FCNVSD_COMPACT, && case_sem_INSN_FCNVSD_COMPACT }, |
| 87 | { SH64_COMPACT_INSN_FDIV_COMPACT, && case_sem_INSN_FDIV_COMPACT }, |
| 88 | { SH64_COMPACT_INSN_FIPR_COMPACT, && case_sem_INSN_FIPR_COMPACT }, |
| 89 | { SH64_COMPACT_INSN_FLDS_COMPACT, && case_sem_INSN_FLDS_COMPACT }, |
| 90 | { SH64_COMPACT_INSN_FLDI0_COMPACT, && case_sem_INSN_FLDI0_COMPACT }, |
| 91 | { SH64_COMPACT_INSN_FLDI1_COMPACT, && case_sem_INSN_FLDI1_COMPACT }, |
| 92 | { SH64_COMPACT_INSN_FLOAT_COMPACT, && case_sem_INSN_FLOAT_COMPACT }, |
| 93 | { SH64_COMPACT_INSN_FMAC_COMPACT, && case_sem_INSN_FMAC_COMPACT }, |
| 94 | { SH64_COMPACT_INSN_FMOV1_COMPACT, && case_sem_INSN_FMOV1_COMPACT }, |
| 95 | { SH64_COMPACT_INSN_FMOV2_COMPACT, && case_sem_INSN_FMOV2_COMPACT }, |
| 96 | { SH64_COMPACT_INSN_FMOV3_COMPACT, && case_sem_INSN_FMOV3_COMPACT }, |
| 97 | { SH64_COMPACT_INSN_FMOV4_COMPACT, && case_sem_INSN_FMOV4_COMPACT }, |
| 98 | { SH64_COMPACT_INSN_FMOV5_COMPACT, && case_sem_INSN_FMOV5_COMPACT }, |
| 99 | { SH64_COMPACT_INSN_FMOV6_COMPACT, && case_sem_INSN_FMOV6_COMPACT }, |
| 100 | { SH64_COMPACT_INSN_FMOV7_COMPACT, && case_sem_INSN_FMOV7_COMPACT }, |
| 101 | { SH64_COMPACT_INSN_FMOV8_COMPACT, && case_sem_INSN_FMOV8_COMPACT }, |
| 102 | { SH64_COMPACT_INSN_FMOV9_COMPACT, && case_sem_INSN_FMOV9_COMPACT }, |
| 103 | { SH64_COMPACT_INSN_FMUL_COMPACT, && case_sem_INSN_FMUL_COMPACT }, |
| 104 | { SH64_COMPACT_INSN_FNEG_COMPACT, && case_sem_INSN_FNEG_COMPACT }, |
| 105 | { SH64_COMPACT_INSN_FRCHG_COMPACT, && case_sem_INSN_FRCHG_COMPACT }, |
| 106 | { SH64_COMPACT_INSN_FSCHG_COMPACT, && case_sem_INSN_FSCHG_COMPACT }, |
| 107 | { SH64_COMPACT_INSN_FSQRT_COMPACT, && case_sem_INSN_FSQRT_COMPACT }, |
| 108 | { SH64_COMPACT_INSN_FSTS_COMPACT, && case_sem_INSN_FSTS_COMPACT }, |
| 109 | { SH64_COMPACT_INSN_FSUB_COMPACT, && case_sem_INSN_FSUB_COMPACT }, |
| 110 | { SH64_COMPACT_INSN_FTRC_COMPACT, && case_sem_INSN_FTRC_COMPACT }, |
| 111 | { SH64_COMPACT_INSN_FTRV_COMPACT, && case_sem_INSN_FTRV_COMPACT }, |
| 112 | { SH64_COMPACT_INSN_JMP_COMPACT, && case_sem_INSN_JMP_COMPACT }, |
| 113 | { SH64_COMPACT_INSN_JSR_COMPACT, && case_sem_INSN_JSR_COMPACT }, |
| 114 | { SH64_COMPACT_INSN_LDC_GBR_COMPACT, && case_sem_INSN_LDC_GBR_COMPACT }, |
| 115 | { SH64_COMPACT_INSN_LDC_VBR_COMPACT, && case_sem_INSN_LDC_VBR_COMPACT }, |
| 116 | { SH64_COMPACT_INSN_LDC_SR_COMPACT, && case_sem_INSN_LDC_SR_COMPACT }, |
| 117 | { SH64_COMPACT_INSN_LDCL_GBR_COMPACT, && case_sem_INSN_LDCL_GBR_COMPACT }, |
| 118 | { SH64_COMPACT_INSN_LDCL_VBR_COMPACT, && case_sem_INSN_LDCL_VBR_COMPACT }, |
| 119 | { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, && case_sem_INSN_LDS_FPSCR_COMPACT }, |
| 120 | { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, && case_sem_INSN_LDSL_FPSCR_COMPACT }, |
| 121 | { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, && case_sem_INSN_LDS_FPUL_COMPACT }, |
| 122 | { SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, && case_sem_INSN_LDSL_FPUL_COMPACT }, |
| 123 | { SH64_COMPACT_INSN_LDS_MACH_COMPACT, && case_sem_INSN_LDS_MACH_COMPACT }, |
| 124 | { SH64_COMPACT_INSN_LDSL_MACH_COMPACT, && case_sem_INSN_LDSL_MACH_COMPACT }, |
| 125 | { SH64_COMPACT_INSN_LDS_MACL_COMPACT, && case_sem_INSN_LDS_MACL_COMPACT }, |
| 126 | { SH64_COMPACT_INSN_LDSL_MACL_COMPACT, && case_sem_INSN_LDSL_MACL_COMPACT }, |
| 127 | { SH64_COMPACT_INSN_LDS_PR_COMPACT, && case_sem_INSN_LDS_PR_COMPACT }, |
| 128 | { SH64_COMPACT_INSN_LDSL_PR_COMPACT, && case_sem_INSN_LDSL_PR_COMPACT }, |
| 129 | { SH64_COMPACT_INSN_MACL_COMPACT, && case_sem_INSN_MACL_COMPACT }, |
| 130 | { SH64_COMPACT_INSN_MACW_COMPACT, && case_sem_INSN_MACW_COMPACT }, |
| 131 | { SH64_COMPACT_INSN_MOV_COMPACT, && case_sem_INSN_MOV_COMPACT }, |
| 132 | { SH64_COMPACT_INSN_MOVI_COMPACT, && case_sem_INSN_MOVI_COMPACT }, |
| 133 | { SH64_COMPACT_INSN_MOVI20_COMPACT, && case_sem_INSN_MOVI20_COMPACT }, |
| 134 | { SH64_COMPACT_INSN_MOVB1_COMPACT, && case_sem_INSN_MOVB1_COMPACT }, |
| 135 | { SH64_COMPACT_INSN_MOVB2_COMPACT, && case_sem_INSN_MOVB2_COMPACT }, |
| 136 | { SH64_COMPACT_INSN_MOVB3_COMPACT, && case_sem_INSN_MOVB3_COMPACT }, |
| 137 | { SH64_COMPACT_INSN_MOVB4_COMPACT, && case_sem_INSN_MOVB4_COMPACT }, |
| 138 | { SH64_COMPACT_INSN_MOVB5_COMPACT, && case_sem_INSN_MOVB5_COMPACT }, |
| 139 | { SH64_COMPACT_INSN_MOVB6_COMPACT, && case_sem_INSN_MOVB6_COMPACT }, |
| 140 | { SH64_COMPACT_INSN_MOVB7_COMPACT, && case_sem_INSN_MOVB7_COMPACT }, |
| 141 | { SH64_COMPACT_INSN_MOVB8_COMPACT, && case_sem_INSN_MOVB8_COMPACT }, |
| 142 | { SH64_COMPACT_INSN_MOVB9_COMPACT, && case_sem_INSN_MOVB9_COMPACT }, |
| 143 | { SH64_COMPACT_INSN_MOVB10_COMPACT, && case_sem_INSN_MOVB10_COMPACT }, |
| 144 | { SH64_COMPACT_INSN_MOVL1_COMPACT, && case_sem_INSN_MOVL1_COMPACT }, |
| 145 | { SH64_COMPACT_INSN_MOVL2_COMPACT, && case_sem_INSN_MOVL2_COMPACT }, |
| 146 | { SH64_COMPACT_INSN_MOVL3_COMPACT, && case_sem_INSN_MOVL3_COMPACT }, |
| 147 | { SH64_COMPACT_INSN_MOVL4_COMPACT, && case_sem_INSN_MOVL4_COMPACT }, |
| 148 | { SH64_COMPACT_INSN_MOVL5_COMPACT, && case_sem_INSN_MOVL5_COMPACT }, |
| 149 | { SH64_COMPACT_INSN_MOVL6_COMPACT, && case_sem_INSN_MOVL6_COMPACT }, |
| 150 | { SH64_COMPACT_INSN_MOVL7_COMPACT, && case_sem_INSN_MOVL7_COMPACT }, |
| 151 | { SH64_COMPACT_INSN_MOVL8_COMPACT, && case_sem_INSN_MOVL8_COMPACT }, |
| 152 | { SH64_COMPACT_INSN_MOVL9_COMPACT, && case_sem_INSN_MOVL9_COMPACT }, |
| 153 | { SH64_COMPACT_INSN_MOVL10_COMPACT, && case_sem_INSN_MOVL10_COMPACT }, |
| 154 | { SH64_COMPACT_INSN_MOVL11_COMPACT, && case_sem_INSN_MOVL11_COMPACT }, |
| 155 | { SH64_COMPACT_INSN_MOVL12_COMPACT, && case_sem_INSN_MOVL12_COMPACT }, |
| 156 | { SH64_COMPACT_INSN_MOVL13_COMPACT, && case_sem_INSN_MOVL13_COMPACT }, |
| 157 | { SH64_COMPACT_INSN_MOVW1_COMPACT, && case_sem_INSN_MOVW1_COMPACT }, |
| 158 | { SH64_COMPACT_INSN_MOVW2_COMPACT, && case_sem_INSN_MOVW2_COMPACT }, |
| 159 | { SH64_COMPACT_INSN_MOVW3_COMPACT, && case_sem_INSN_MOVW3_COMPACT }, |
| 160 | { SH64_COMPACT_INSN_MOVW4_COMPACT, && case_sem_INSN_MOVW4_COMPACT }, |
| 161 | { SH64_COMPACT_INSN_MOVW5_COMPACT, && case_sem_INSN_MOVW5_COMPACT }, |
| 162 | { SH64_COMPACT_INSN_MOVW6_COMPACT, && case_sem_INSN_MOVW6_COMPACT }, |
| 163 | { SH64_COMPACT_INSN_MOVW7_COMPACT, && case_sem_INSN_MOVW7_COMPACT }, |
| 164 | { SH64_COMPACT_INSN_MOVW8_COMPACT, && case_sem_INSN_MOVW8_COMPACT }, |
| 165 | { SH64_COMPACT_INSN_MOVW9_COMPACT, && case_sem_INSN_MOVW9_COMPACT }, |
| 166 | { SH64_COMPACT_INSN_MOVW10_COMPACT, && case_sem_INSN_MOVW10_COMPACT }, |
| 167 | { SH64_COMPACT_INSN_MOVW11_COMPACT, && case_sem_INSN_MOVW11_COMPACT }, |
| 168 | { SH64_COMPACT_INSN_MOVA_COMPACT, && case_sem_INSN_MOVA_COMPACT }, |
| 169 | { SH64_COMPACT_INSN_MOVCAL_COMPACT, && case_sem_INSN_MOVCAL_COMPACT }, |
| 170 | { SH64_COMPACT_INSN_MOVCOL_COMPACT, && case_sem_INSN_MOVCOL_COMPACT }, |
| 171 | { SH64_COMPACT_INSN_MOVT_COMPACT, && case_sem_INSN_MOVT_COMPACT }, |
| 172 | { SH64_COMPACT_INSN_MOVUAL_COMPACT, && case_sem_INSN_MOVUAL_COMPACT }, |
| 173 | { SH64_COMPACT_INSN_MOVUAL2_COMPACT, && case_sem_INSN_MOVUAL2_COMPACT }, |
| 174 | { SH64_COMPACT_INSN_MULL_COMPACT, && case_sem_INSN_MULL_COMPACT }, |
| 175 | { SH64_COMPACT_INSN_MULSW_COMPACT, && case_sem_INSN_MULSW_COMPACT }, |
| 176 | { SH64_COMPACT_INSN_MULUW_COMPACT, && case_sem_INSN_MULUW_COMPACT }, |
| 177 | { SH64_COMPACT_INSN_NEG_COMPACT, && case_sem_INSN_NEG_COMPACT }, |
| 178 | { SH64_COMPACT_INSN_NEGC_COMPACT, && case_sem_INSN_NEGC_COMPACT }, |
| 179 | { SH64_COMPACT_INSN_NOP_COMPACT, && case_sem_INSN_NOP_COMPACT }, |
| 180 | { SH64_COMPACT_INSN_NOT_COMPACT, && case_sem_INSN_NOT_COMPACT }, |
| 181 | { SH64_COMPACT_INSN_OCBI_COMPACT, && case_sem_INSN_OCBI_COMPACT }, |
| 182 | { SH64_COMPACT_INSN_OCBP_COMPACT, && case_sem_INSN_OCBP_COMPACT }, |
| 183 | { SH64_COMPACT_INSN_OCBWB_COMPACT, && case_sem_INSN_OCBWB_COMPACT }, |
| 184 | { SH64_COMPACT_INSN_OR_COMPACT, && case_sem_INSN_OR_COMPACT }, |
| 185 | { SH64_COMPACT_INSN_ORI_COMPACT, && case_sem_INSN_ORI_COMPACT }, |
| 186 | { SH64_COMPACT_INSN_ORB_COMPACT, && case_sem_INSN_ORB_COMPACT }, |
| 187 | { SH64_COMPACT_INSN_PREF_COMPACT, && case_sem_INSN_PREF_COMPACT }, |
| 188 | { SH64_COMPACT_INSN_ROTCL_COMPACT, && case_sem_INSN_ROTCL_COMPACT }, |
| 189 | { SH64_COMPACT_INSN_ROTCR_COMPACT, && case_sem_INSN_ROTCR_COMPACT }, |
| 190 | { SH64_COMPACT_INSN_ROTL_COMPACT, && case_sem_INSN_ROTL_COMPACT }, |
| 191 | { SH64_COMPACT_INSN_ROTR_COMPACT, && case_sem_INSN_ROTR_COMPACT }, |
| 192 | { SH64_COMPACT_INSN_RTS_COMPACT, && case_sem_INSN_RTS_COMPACT }, |
| 193 | { SH64_COMPACT_INSN_SETS_COMPACT, && case_sem_INSN_SETS_COMPACT }, |
| 194 | { SH64_COMPACT_INSN_SETT_COMPACT, && case_sem_INSN_SETT_COMPACT }, |
| 195 | { SH64_COMPACT_INSN_SHAD_COMPACT, && case_sem_INSN_SHAD_COMPACT }, |
| 196 | { SH64_COMPACT_INSN_SHAL_COMPACT, && case_sem_INSN_SHAL_COMPACT }, |
| 197 | { SH64_COMPACT_INSN_SHAR_COMPACT, && case_sem_INSN_SHAR_COMPACT }, |
| 198 | { SH64_COMPACT_INSN_SHLD_COMPACT, && case_sem_INSN_SHLD_COMPACT }, |
| 199 | { SH64_COMPACT_INSN_SHLL_COMPACT, && case_sem_INSN_SHLL_COMPACT }, |
| 200 | { SH64_COMPACT_INSN_SHLL2_COMPACT, && case_sem_INSN_SHLL2_COMPACT }, |
| 201 | { SH64_COMPACT_INSN_SHLL8_COMPACT, && case_sem_INSN_SHLL8_COMPACT }, |
| 202 | { SH64_COMPACT_INSN_SHLL16_COMPACT, && case_sem_INSN_SHLL16_COMPACT }, |
| 203 | { SH64_COMPACT_INSN_SHLR_COMPACT, && case_sem_INSN_SHLR_COMPACT }, |
| 204 | { SH64_COMPACT_INSN_SHLR2_COMPACT, && case_sem_INSN_SHLR2_COMPACT }, |
| 205 | { SH64_COMPACT_INSN_SHLR8_COMPACT, && case_sem_INSN_SHLR8_COMPACT }, |
| 206 | { SH64_COMPACT_INSN_SHLR16_COMPACT, && case_sem_INSN_SHLR16_COMPACT }, |
| 207 | { SH64_COMPACT_INSN_STC_GBR_COMPACT, && case_sem_INSN_STC_GBR_COMPACT }, |
| 208 | { SH64_COMPACT_INSN_STC_VBR_COMPACT, && case_sem_INSN_STC_VBR_COMPACT }, |
| 209 | { SH64_COMPACT_INSN_STCL_GBR_COMPACT, && case_sem_INSN_STCL_GBR_COMPACT }, |
| 210 | { SH64_COMPACT_INSN_STCL_VBR_COMPACT, && case_sem_INSN_STCL_VBR_COMPACT }, |
| 211 | { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, && case_sem_INSN_STS_FPSCR_COMPACT }, |
| 212 | { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, && case_sem_INSN_STSL_FPSCR_COMPACT }, |
| 213 | { SH64_COMPACT_INSN_STS_FPUL_COMPACT, && case_sem_INSN_STS_FPUL_COMPACT }, |
| 214 | { SH64_COMPACT_INSN_STSL_FPUL_COMPACT, && case_sem_INSN_STSL_FPUL_COMPACT }, |
| 215 | { SH64_COMPACT_INSN_STS_MACH_COMPACT, && case_sem_INSN_STS_MACH_COMPACT }, |
| 216 | { SH64_COMPACT_INSN_STSL_MACH_COMPACT, && case_sem_INSN_STSL_MACH_COMPACT }, |
| 217 | { SH64_COMPACT_INSN_STS_MACL_COMPACT, && case_sem_INSN_STS_MACL_COMPACT }, |
| 218 | { SH64_COMPACT_INSN_STSL_MACL_COMPACT, && case_sem_INSN_STSL_MACL_COMPACT }, |
| 219 | { SH64_COMPACT_INSN_STS_PR_COMPACT, && case_sem_INSN_STS_PR_COMPACT }, |
| 220 | { SH64_COMPACT_INSN_STSL_PR_COMPACT, && case_sem_INSN_STSL_PR_COMPACT }, |
| 221 | { SH64_COMPACT_INSN_SUB_COMPACT, && case_sem_INSN_SUB_COMPACT }, |
| 222 | { SH64_COMPACT_INSN_SUBC_COMPACT, && case_sem_INSN_SUBC_COMPACT }, |
| 223 | { SH64_COMPACT_INSN_SUBV_COMPACT, && case_sem_INSN_SUBV_COMPACT }, |
| 224 | { SH64_COMPACT_INSN_SWAPB_COMPACT, && case_sem_INSN_SWAPB_COMPACT }, |
| 225 | { SH64_COMPACT_INSN_SWAPW_COMPACT, && case_sem_INSN_SWAPW_COMPACT }, |
| 226 | { SH64_COMPACT_INSN_TASB_COMPACT, && case_sem_INSN_TASB_COMPACT }, |
| 227 | { SH64_COMPACT_INSN_TRAPA_COMPACT, && case_sem_INSN_TRAPA_COMPACT }, |
| 228 | { SH64_COMPACT_INSN_TST_COMPACT, && case_sem_INSN_TST_COMPACT }, |
| 229 | { SH64_COMPACT_INSN_TSTI_COMPACT, && case_sem_INSN_TSTI_COMPACT }, |
| 230 | { SH64_COMPACT_INSN_TSTB_COMPACT, && case_sem_INSN_TSTB_COMPACT }, |
| 231 | { SH64_COMPACT_INSN_XOR_COMPACT, && case_sem_INSN_XOR_COMPACT }, |
| 232 | { SH64_COMPACT_INSN_XORI_COMPACT, && case_sem_INSN_XORI_COMPACT }, |
| 233 | { SH64_COMPACT_INSN_XORB_COMPACT, && case_sem_INSN_XORB_COMPACT }, |
| 234 | { SH64_COMPACT_INSN_XTRCT_COMPACT, && case_sem_INSN_XTRCT_COMPACT }, |
| 235 | { 0, 0 } |
| 236 | }; |
| 237 | int i; |
| 238 | |
| 239 | for (i = 0; labels[i].label != 0; ++i) |
| 240 | { |
| 241 | #if FAST_P |
| 242 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; |
| 243 | #else |
| 244 | CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; |
| 245 | #endif |
| 246 | } |
| 247 | |
| 248 | #undef DEFINE_LABELS |
| 249 | #endif /* DEFINE_LABELS */ |
| 250 | |
| 251 | #ifdef DEFINE_SWITCH |
| 252 | |
| 253 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn |
| 254 | off frills like tracing and profiling. */ |
| 255 | /* FIXME: A better way would be to have TRACE_RESULT check for something |
| 256 | that can cause it to be optimized out. Another way would be to emit |
| 257 | special handlers into the instruction "stream". */ |
| 258 | |
| 259 | #if FAST_P |
| 260 | #undef TRACE_RESULT |
| 261 | #define TRACE_RESULT(cpu, abuf, name, type, val) |
| 262 | #endif |
| 263 | |
| 264 | #undef GET_ATTR |
| 265 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 266 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) |
| 267 | #else |
| 268 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) |
| 269 | #endif |
| 270 | |
| 271 | { |
| 272 | |
| 273 | #if WITH_SCACHE_PBB |
| 274 | |
| 275 | /* Branch to next handler without going around main loop. */ |
| 276 | #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case |
| 277 | SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) |
| 278 | |
| 279 | #else /* ! WITH_SCACHE_PBB */ |
| 280 | |
| 281 | #define NEXT(vpc) BREAK (sem) |
| 282 | #ifdef __GNUC__ |
| 283 | #if FAST_P |
| 284 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) |
| 285 | #else |
| 286 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) |
| 287 | #endif |
| 288 | #else |
| 289 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) |
| 290 | #endif |
| 291 | |
| 292 | #endif /* ! WITH_SCACHE_PBB */ |
| 293 | |
| 294 | { |
| 295 | |
| 296 | CASE (sem, INSN_X_INVALID) : /* --invalid-- */ |
| 297 | { |
| 298 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 299 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 300 | #define FLD(f) abuf->fields.fmt_empty.f |
| 301 | int UNUSED written = 0; |
| 302 | IADDR UNUSED pc = abuf->addr; |
| 303 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 304 | |
| 305 | { |
| 306 | /* Update the recorded pc in the cpu state struct. |
| 307 | Only necessary for WITH_SCACHE case, but to avoid the |
| 308 | conditional compilation .... */ |
| 309 | SET_H_PC (pc); |
| 310 | /* Virtual insns have zero size. Overwrite vpc with address of next insn |
| 311 | using the default-insn-bitsize spec. When executing insns in parallel |
| 312 | we may want to queue the fault and continue execution. */ |
| 313 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 314 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); |
| 315 | } |
| 316 | |
| 317 | #undef FLD |
| 318 | } |
| 319 | NEXT (vpc); |
| 320 | |
| 321 | CASE (sem, INSN_X_AFTER) : /* --after-- */ |
| 322 | { |
| 323 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 324 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 325 | #define FLD(f) abuf->fields.fmt_empty.f |
| 326 | int UNUSED written = 0; |
| 327 | IADDR UNUSED pc = abuf->addr; |
| 328 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 329 | |
| 330 | { |
| 331 | #if WITH_SCACHE_PBB_SH64_COMPACT |
| 332 | sh64_compact_pbb_after (current_cpu, sem_arg); |
| 333 | #endif |
| 334 | } |
| 335 | |
| 336 | #undef FLD |
| 337 | } |
| 338 | NEXT (vpc); |
| 339 | |
| 340 | CASE (sem, INSN_X_BEFORE) : /* --before-- */ |
| 341 | { |
| 342 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 343 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 344 | #define FLD(f) abuf->fields.fmt_empty.f |
| 345 | int UNUSED written = 0; |
| 346 | IADDR UNUSED pc = abuf->addr; |
| 347 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 348 | |
| 349 | { |
| 350 | #if WITH_SCACHE_PBB_SH64_COMPACT |
| 351 | sh64_compact_pbb_before (current_cpu, sem_arg); |
| 352 | #endif |
| 353 | } |
| 354 | |
| 355 | #undef FLD |
| 356 | } |
| 357 | NEXT (vpc); |
| 358 | |
| 359 | CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ |
| 360 | { |
| 361 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 362 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 363 | #define FLD(f) abuf->fields.fmt_empty.f |
| 364 | int UNUSED written = 0; |
| 365 | IADDR UNUSED pc = abuf->addr; |
| 366 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 367 | |
| 368 | { |
| 369 | #if WITH_SCACHE_PBB_SH64_COMPACT |
| 370 | #ifdef DEFINE_SWITCH |
| 371 | vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg, |
| 372 | pbb_br_type, pbb_br_npc); |
| 373 | BREAK (sem); |
| 374 | #else |
| 375 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ |
| 376 | vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg, |
| 377 | CPU_PBB_BR_TYPE (current_cpu), |
| 378 | CPU_PBB_BR_NPC (current_cpu)); |
| 379 | #endif |
| 380 | #endif |
| 381 | } |
| 382 | |
| 383 | #undef FLD |
| 384 | } |
| 385 | NEXT (vpc); |
| 386 | |
| 387 | CASE (sem, INSN_X_CHAIN) : /* --chain-- */ |
| 388 | { |
| 389 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 390 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 391 | #define FLD(f) abuf->fields.fmt_empty.f |
| 392 | int UNUSED written = 0; |
| 393 | IADDR UNUSED pc = abuf->addr; |
| 394 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 395 | |
| 396 | { |
| 397 | #if WITH_SCACHE_PBB_SH64_COMPACT |
| 398 | vpc = sh64_compact_pbb_chain (current_cpu, sem_arg); |
| 399 | #ifdef DEFINE_SWITCH |
| 400 | BREAK (sem); |
| 401 | #endif |
| 402 | #endif |
| 403 | } |
| 404 | |
| 405 | #undef FLD |
| 406 | } |
| 407 | NEXT (vpc); |
| 408 | |
| 409 | CASE (sem, INSN_X_BEGIN) : /* --begin-- */ |
| 410 | { |
| 411 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 412 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 413 | #define FLD(f) abuf->fields.fmt_empty.f |
| 414 | int UNUSED written = 0; |
| 415 | IADDR UNUSED pc = abuf->addr; |
| 416 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |
| 417 | |
| 418 | { |
| 419 | #if WITH_SCACHE_PBB_SH64_COMPACT |
| 420 | #if defined DEFINE_SWITCH || defined FAST_P |
| 421 | /* In the switch case FAST_P is a constant, allowing several optimizations |
| 422 | in any called inline functions. */ |
| 423 | vpc = sh64_compact_pbb_begin (current_cpu, FAST_P); |
| 424 | #else |
| 425 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ |
| 426 | vpc = sh64_compact_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); |
| 427 | #else |
| 428 | vpc = sh64_compact_pbb_begin (current_cpu, 0); |
| 429 | #endif |
| 430 | #endif |
| 431 | #endif |
| 432 | } |
| 433 | |
| 434 | #undef FLD |
| 435 | } |
| 436 | NEXT (vpc); |
| 437 | |
| 438 | CASE (sem, INSN_ADD_COMPACT) : /* add $rm, $rn */ |
| 439 | { |
| 440 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 441 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 442 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 443 | int UNUSED written = 0; |
| 444 | IADDR UNUSED pc = abuf->addr; |
| 445 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 446 | |
| 447 | { |
| 448 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 449 | SET_H_GRC (FLD (f_rn), opval); |
| 450 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 451 | } |
| 452 | |
| 453 | #undef FLD |
| 454 | } |
| 455 | NEXT (vpc); |
| 456 | |
| 457 | CASE (sem, INSN_ADDI_COMPACT) : /* add #$imm8, $rn */ |
| 458 | { |
| 459 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 460 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 461 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 462 | int UNUSED written = 0; |
| 463 | IADDR UNUSED pc = abuf->addr; |
| 464 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 465 | |
| 466 | { |
| 467 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255))); |
| 468 | SET_H_GRC (FLD (f_rn), opval); |
| 469 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 470 | } |
| 471 | |
| 472 | #undef FLD |
| 473 | } |
| 474 | NEXT (vpc); |
| 475 | |
| 476 | CASE (sem, INSN_ADDC_COMPACT) : /* addc $rm, $rn */ |
| 477 | { |
| 478 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 479 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 480 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 481 | int UNUSED written = 0; |
| 482 | IADDR UNUSED pc = abuf->addr; |
| 483 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 484 | |
| 485 | { |
| 486 | BI tmp_flag; |
| 487 | tmp_flag = ADDCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); |
| 488 | { |
| 489 | SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); |
| 490 | SET_H_GRC (FLD (f_rn), opval); |
| 491 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 492 | } |
| 493 | { |
| 494 | BI opval = tmp_flag; |
| 495 | SET_H_TBIT (opval); |
| 496 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | #undef FLD |
| 501 | } |
| 502 | NEXT (vpc); |
| 503 | |
| 504 | CASE (sem, INSN_ADDV_COMPACT) : /* addv $rm, $rn */ |
| 505 | { |
| 506 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 507 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 508 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 509 | int UNUSED written = 0; |
| 510 | IADDR UNUSED pc = abuf->addr; |
| 511 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 512 | |
| 513 | { |
| 514 | BI tmp_t; |
| 515 | tmp_t = ADDOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0); |
| 516 | { |
| 517 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 518 | SET_H_GRC (FLD (f_rn), opval); |
| 519 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 520 | } |
| 521 | { |
| 522 | BI opval = tmp_t; |
| 523 | SET_H_TBIT (opval); |
| 524 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 525 | } |
| 526 | } |
| 527 | |
| 528 | #undef FLD |
| 529 | } |
| 530 | NEXT (vpc); |
| 531 | |
| 532 | CASE (sem, INSN_AND_COMPACT) : /* and $rm64, $rn64 */ |
| 533 | { |
| 534 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 535 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 536 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 537 | int UNUSED written = 0; |
| 538 | IADDR UNUSED pc = abuf->addr; |
| 539 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 540 | |
| 541 | { |
| 542 | DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); |
| 543 | SET_H_GR (FLD (f_rn), opval); |
| 544 | TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); |
| 545 | } |
| 546 | |
| 547 | #undef FLD |
| 548 | } |
| 549 | NEXT (vpc); |
| 550 | |
| 551 | CASE (sem, INSN_ANDI_COMPACT) : /* and #$uimm8, r0 */ |
| 552 | { |
| 553 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 554 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 555 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 556 | int UNUSED written = 0; |
| 557 | IADDR UNUSED pc = abuf->addr; |
| 558 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 559 | |
| 560 | { |
| 561 | SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); |
| 562 | SET_H_GRC (((UINT) 0), opval); |
| 563 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 564 | } |
| 565 | |
| 566 | #undef FLD |
| 567 | } |
| 568 | NEXT (vpc); |
| 569 | |
| 570 | CASE (sem, INSN_ANDB_COMPACT) : /* and.b #$imm8, @(r0, gbr) */ |
| 571 | { |
| 572 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 573 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 574 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 575 | int UNUSED written = 0; |
| 576 | IADDR UNUSED pc = abuf->addr; |
| 577 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 578 | |
| 579 | { |
| 580 | DI tmp_addr; |
| 581 | UQI tmp_data; |
| 582 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); |
| 583 | tmp_data = ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)); |
| 584 | { |
| 585 | UQI opval = tmp_data; |
| 586 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); |
| 587 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 588 | } |
| 589 | } |
| 590 | |
| 591 | #undef FLD |
| 592 | } |
| 593 | NEXT (vpc); |
| 594 | |
| 595 | CASE (sem, INSN_BF_COMPACT) : /* bf $disp8 */ |
| 596 | { |
| 597 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 598 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 599 | #define FLD(f) abuf->fields.sfmt_bf_compact.f |
| 600 | int UNUSED written = 0; |
| 601 | IADDR UNUSED pc = abuf->addr; |
| 602 | SEM_BRANCH_INIT |
| 603 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 604 | |
| 605 | if (NOTBI (GET_H_TBIT ())) { |
| 606 | { |
| 607 | UDI opval = FLD (i_disp8); |
| 608 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 609 | written |= (1 << 2); |
| 610 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 611 | } |
| 612 | } |
| 613 | |
| 614 | abuf->written = written; |
| 615 | SEM_BRANCH_FINI (vpc); |
| 616 | #undef FLD |
| 617 | } |
| 618 | NEXT (vpc); |
| 619 | |
| 620 | CASE (sem, INSN_BFS_COMPACT) : /* bf/s $disp8 */ |
| 621 | { |
| 622 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 623 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 624 | #define FLD(f) abuf->fields.sfmt_bf_compact.f |
| 625 | int UNUSED written = 0; |
| 626 | IADDR UNUSED pc = abuf->addr; |
| 627 | SEM_BRANCH_INIT |
| 628 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 629 | |
| 630 | if (NOTBI (GET_H_TBIT ())) { |
| 631 | { |
| 632 | { |
| 633 | UDI opval = ADDDI (pc, 2); |
| 634 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 635 | written |= (1 << 3); |
| 636 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 637 | } |
| 638 | ((void) 0); /*nop*/ |
| 639 | { |
| 640 | { |
| 641 | UDI opval = FLD (i_disp8); |
| 642 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 643 | written |= (1 << 3); |
| 644 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 645 | } |
| 646 | } |
| 647 | } |
| 648 | } |
| 649 | |
| 650 | abuf->written = written; |
| 651 | SEM_BRANCH_FINI (vpc); |
| 652 | #undef FLD |
| 653 | } |
| 654 | NEXT (vpc); |
| 655 | |
| 656 | CASE (sem, INSN_BRA_COMPACT) : /* bra $disp12 */ |
| 657 | { |
| 658 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 659 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 660 | #define FLD(f) abuf->fields.sfmt_bra_compact.f |
| 661 | int UNUSED written = 0; |
| 662 | IADDR UNUSED pc = abuf->addr; |
| 663 | SEM_BRANCH_INIT |
| 664 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 665 | |
| 666 | { |
| 667 | { |
| 668 | UDI opval = ADDDI (pc, 2); |
| 669 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 670 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 671 | } |
| 672 | ((void) 0); /*nop*/ |
| 673 | { |
| 674 | { |
| 675 | UDI opval = FLD (i_disp12); |
| 676 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 677 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 678 | } |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | SEM_BRANCH_FINI (vpc); |
| 683 | #undef FLD |
| 684 | } |
| 685 | NEXT (vpc); |
| 686 | |
| 687 | CASE (sem, INSN_BRAF_COMPACT) : /* braf $rn */ |
| 688 | { |
| 689 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 690 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 691 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 692 | int UNUSED written = 0; |
| 693 | IADDR UNUSED pc = abuf->addr; |
| 694 | SEM_BRANCH_INIT |
| 695 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 696 | |
| 697 | { |
| 698 | { |
| 699 | UDI opval = ADDDI (pc, 2); |
| 700 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 701 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 702 | } |
| 703 | ((void) 0); /*nop*/ |
| 704 | { |
| 705 | { |
| 706 | UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); |
| 707 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 708 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 709 | } |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | SEM_BRANCH_FINI (vpc); |
| 714 | #undef FLD |
| 715 | } |
| 716 | NEXT (vpc); |
| 717 | |
| 718 | CASE (sem, INSN_BRK_COMPACT) : /* brk */ |
| 719 | { |
| 720 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 721 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 722 | #define FLD(f) abuf->fields.fmt_empty.f |
| 723 | int UNUSED written = 0; |
| 724 | IADDR UNUSED pc = abuf->addr; |
| 725 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 726 | |
| 727 | sh64_break (current_cpu, pc); |
| 728 | |
| 729 | #undef FLD |
| 730 | } |
| 731 | NEXT (vpc); |
| 732 | |
| 733 | CASE (sem, INSN_BSR_COMPACT) : /* bsr $disp12 */ |
| 734 | { |
| 735 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 736 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 737 | #define FLD(f) abuf->fields.sfmt_bra_compact.f |
| 738 | int UNUSED written = 0; |
| 739 | IADDR UNUSED pc = abuf->addr; |
| 740 | SEM_BRANCH_INIT |
| 741 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 742 | |
| 743 | { |
| 744 | { |
| 745 | { |
| 746 | SI opval = ADDDI (pc, 4); |
| 747 | SET_H_PR (opval); |
| 748 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); |
| 749 | } |
| 750 | } |
| 751 | { |
| 752 | UDI opval = ADDDI (pc, 2); |
| 753 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 754 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 755 | } |
| 756 | ((void) 0); /*nop*/ |
| 757 | { |
| 758 | { |
| 759 | UDI opval = FLD (i_disp12); |
| 760 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 761 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 762 | } |
| 763 | } |
| 764 | } |
| 765 | |
| 766 | SEM_BRANCH_FINI (vpc); |
| 767 | #undef FLD |
| 768 | } |
| 769 | NEXT (vpc); |
| 770 | |
| 771 | CASE (sem, INSN_BSRF_COMPACT) : /* bsrf $rn */ |
| 772 | { |
| 773 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 774 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 775 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 776 | int UNUSED written = 0; |
| 777 | IADDR UNUSED pc = abuf->addr; |
| 778 | SEM_BRANCH_INIT |
| 779 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 780 | |
| 781 | { |
| 782 | { |
| 783 | { |
| 784 | SI opval = ADDDI (pc, 4); |
| 785 | SET_H_PR (opval); |
| 786 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); |
| 787 | } |
| 788 | } |
| 789 | { |
| 790 | UDI opval = ADDDI (pc, 2); |
| 791 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 792 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 793 | } |
| 794 | ((void) 0); /*nop*/ |
| 795 | { |
| 796 | { |
| 797 | UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); |
| 798 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 799 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 800 | } |
| 801 | } |
| 802 | } |
| 803 | |
| 804 | SEM_BRANCH_FINI (vpc); |
| 805 | #undef FLD |
| 806 | } |
| 807 | NEXT (vpc); |
| 808 | |
| 809 | CASE (sem, INSN_BT_COMPACT) : /* bt $disp8 */ |
| 810 | { |
| 811 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 812 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 813 | #define FLD(f) abuf->fields.sfmt_bf_compact.f |
| 814 | int UNUSED written = 0; |
| 815 | IADDR UNUSED pc = abuf->addr; |
| 816 | SEM_BRANCH_INIT |
| 817 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 818 | |
| 819 | if (GET_H_TBIT ()) { |
| 820 | { |
| 821 | UDI opval = FLD (i_disp8); |
| 822 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 823 | written |= (1 << 2); |
| 824 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | abuf->written = written; |
| 829 | SEM_BRANCH_FINI (vpc); |
| 830 | #undef FLD |
| 831 | } |
| 832 | NEXT (vpc); |
| 833 | |
| 834 | CASE (sem, INSN_BTS_COMPACT) : /* bt/s $disp8 */ |
| 835 | { |
| 836 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 837 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 838 | #define FLD(f) abuf->fields.sfmt_bf_compact.f |
| 839 | int UNUSED written = 0; |
| 840 | IADDR UNUSED pc = abuf->addr; |
| 841 | SEM_BRANCH_INIT |
| 842 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 843 | |
| 844 | if (GET_H_TBIT ()) { |
| 845 | { |
| 846 | { |
| 847 | UDI opval = ADDDI (pc, 2); |
| 848 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 849 | written |= (1 << 3); |
| 850 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 851 | } |
| 852 | ((void) 0); /*nop*/ |
| 853 | { |
| 854 | { |
| 855 | UDI opval = FLD (i_disp8); |
| 856 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); |
| 857 | written |= (1 << 3); |
| 858 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 859 | } |
| 860 | } |
| 861 | } |
| 862 | } |
| 863 | |
| 864 | abuf->written = written; |
| 865 | SEM_BRANCH_FINI (vpc); |
| 866 | #undef FLD |
| 867 | } |
| 868 | NEXT (vpc); |
| 869 | |
| 870 | CASE (sem, INSN_CLRMAC_COMPACT) : /* clrmac */ |
| 871 | { |
| 872 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 873 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 874 | #define FLD(f) abuf->fields.fmt_empty.f |
| 875 | int UNUSED written = 0; |
| 876 | IADDR UNUSED pc = abuf->addr; |
| 877 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 878 | |
| 879 | { |
| 880 | { |
| 881 | SI opval = 0; |
| 882 | SET_H_MACL (opval); |
| 883 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 884 | } |
| 885 | { |
| 886 | SI opval = 0; |
| 887 | SET_H_MACH (opval); |
| 888 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 889 | } |
| 890 | } |
| 891 | |
| 892 | #undef FLD |
| 893 | } |
| 894 | NEXT (vpc); |
| 895 | |
| 896 | CASE (sem, INSN_CLRS_COMPACT) : /* clrs */ |
| 897 | { |
| 898 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 899 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 900 | #define FLD(f) abuf->fields.fmt_empty.f |
| 901 | int UNUSED written = 0; |
| 902 | IADDR UNUSED pc = abuf->addr; |
| 903 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 904 | |
| 905 | { |
| 906 | BI opval = 0; |
| 907 | SET_H_SBIT (opval); |
| 908 | TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval); |
| 909 | } |
| 910 | |
| 911 | #undef FLD |
| 912 | } |
| 913 | NEXT (vpc); |
| 914 | |
| 915 | CASE (sem, INSN_CLRT_COMPACT) : /* clrt */ |
| 916 | { |
| 917 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 918 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 919 | #define FLD(f) abuf->fields.fmt_empty.f |
| 920 | int UNUSED written = 0; |
| 921 | IADDR UNUSED pc = abuf->addr; |
| 922 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 923 | |
| 924 | { |
| 925 | BI opval = 0; |
| 926 | SET_H_TBIT (opval); |
| 927 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 928 | } |
| 929 | |
| 930 | #undef FLD |
| 931 | } |
| 932 | NEXT (vpc); |
| 933 | |
| 934 | CASE (sem, INSN_CMPEQ_COMPACT) : /* cmp/eq $rm, $rn */ |
| 935 | { |
| 936 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 937 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 938 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 939 | int UNUSED written = 0; |
| 940 | IADDR UNUSED pc = abuf->addr; |
| 941 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 942 | |
| 943 | { |
| 944 | BI opval = EQSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); |
| 945 | SET_H_TBIT (opval); |
| 946 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 947 | } |
| 948 | |
| 949 | #undef FLD |
| 950 | } |
| 951 | NEXT (vpc); |
| 952 | |
| 953 | CASE (sem, INSN_CMPEQI_COMPACT) : /* cmp/eq #$imm8, r0 */ |
| 954 | { |
| 955 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 956 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 957 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 958 | int UNUSED written = 0; |
| 959 | IADDR UNUSED pc = abuf->addr; |
| 960 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 961 | |
| 962 | { |
| 963 | BI opval = EQSI (GET_H_GRC (((UINT) 0)), EXTQISI (ANDQI (FLD (f_imm8), 255))); |
| 964 | SET_H_TBIT (opval); |
| 965 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 966 | } |
| 967 | |
| 968 | #undef FLD |
| 969 | } |
| 970 | NEXT (vpc); |
| 971 | |
| 972 | CASE (sem, INSN_CMPGE_COMPACT) : /* cmp/ge $rm, $rn */ |
| 973 | { |
| 974 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 975 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 976 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 977 | int UNUSED written = 0; |
| 978 | IADDR UNUSED pc = abuf->addr; |
| 979 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 980 | |
| 981 | { |
| 982 | BI opval = GESI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 983 | SET_H_TBIT (opval); |
| 984 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 985 | } |
| 986 | |
| 987 | #undef FLD |
| 988 | } |
| 989 | NEXT (vpc); |
| 990 | |
| 991 | CASE (sem, INSN_CMPGT_COMPACT) : /* cmp/gt $rm, $rn */ |
| 992 | { |
| 993 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 994 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 995 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 996 | int UNUSED written = 0; |
| 997 | IADDR UNUSED pc = abuf->addr; |
| 998 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 999 | |
| 1000 | { |
| 1001 | BI opval = GTSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 1002 | SET_H_TBIT (opval); |
| 1003 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1004 | } |
| 1005 | |
| 1006 | #undef FLD |
| 1007 | } |
| 1008 | NEXT (vpc); |
| 1009 | |
| 1010 | CASE (sem, INSN_CMPHI_COMPACT) : /* cmp/hi $rm, $rn */ |
| 1011 | { |
| 1012 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1013 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1014 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1015 | int UNUSED written = 0; |
| 1016 | IADDR UNUSED pc = abuf->addr; |
| 1017 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1018 | |
| 1019 | { |
| 1020 | BI opval = GTUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 1021 | SET_H_TBIT (opval); |
| 1022 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1023 | } |
| 1024 | |
| 1025 | #undef FLD |
| 1026 | } |
| 1027 | NEXT (vpc); |
| 1028 | |
| 1029 | CASE (sem, INSN_CMPHS_COMPACT) : /* cmp/hs $rm, $rn */ |
| 1030 | { |
| 1031 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1032 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1033 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1034 | int UNUSED written = 0; |
| 1035 | IADDR UNUSED pc = abuf->addr; |
| 1036 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1037 | |
| 1038 | { |
| 1039 | BI opval = GEUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 1040 | SET_H_TBIT (opval); |
| 1041 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1042 | } |
| 1043 | |
| 1044 | #undef FLD |
| 1045 | } |
| 1046 | NEXT (vpc); |
| 1047 | |
| 1048 | CASE (sem, INSN_CMPPL_COMPACT) : /* cmp/pl $rn */ |
| 1049 | { |
| 1050 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1051 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1052 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1053 | int UNUSED written = 0; |
| 1054 | IADDR UNUSED pc = abuf->addr; |
| 1055 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1056 | |
| 1057 | { |
| 1058 | BI opval = GTSI (GET_H_GRC (FLD (f_rn)), 0); |
| 1059 | SET_H_TBIT (opval); |
| 1060 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1061 | } |
| 1062 | |
| 1063 | #undef FLD |
| 1064 | } |
| 1065 | NEXT (vpc); |
| 1066 | |
| 1067 | CASE (sem, INSN_CMPPZ_COMPACT) : /* cmp/pz $rn */ |
| 1068 | { |
| 1069 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1070 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1071 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1072 | int UNUSED written = 0; |
| 1073 | IADDR UNUSED pc = abuf->addr; |
| 1074 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1075 | |
| 1076 | { |
| 1077 | BI opval = GESI (GET_H_GRC (FLD (f_rn)), 0); |
| 1078 | SET_H_TBIT (opval); |
| 1079 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1080 | } |
| 1081 | |
| 1082 | #undef FLD |
| 1083 | } |
| 1084 | NEXT (vpc); |
| 1085 | |
| 1086 | CASE (sem, INSN_CMPSTR_COMPACT) : /* cmp/str $rm, $rn */ |
| 1087 | { |
| 1088 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1089 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1090 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1091 | int UNUSED written = 0; |
| 1092 | IADDR UNUSED pc = abuf->addr; |
| 1093 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1094 | |
| 1095 | { |
| 1096 | BI tmp_t; |
| 1097 | SI tmp_temp; |
| 1098 | tmp_temp = XORSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); |
| 1099 | tmp_t = EQSI (ANDSI (tmp_temp, 0xff000000), 0); |
| 1100 | tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 16711680), 0), tmp_t); |
| 1101 | tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 65280), 0), tmp_t); |
| 1102 | tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 255), 0), tmp_t); |
| 1103 | { |
| 1104 | BI opval = ((GTUBI (tmp_t, 0)) ? (1) : (0)); |
| 1105 | SET_H_TBIT (opval); |
| 1106 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | #undef FLD |
| 1111 | } |
| 1112 | NEXT (vpc); |
| 1113 | |
| 1114 | CASE (sem, INSN_DIV0S_COMPACT) : /* div0s $rm, $rn */ |
| 1115 | { |
| 1116 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1117 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1118 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1119 | int UNUSED written = 0; |
| 1120 | IADDR UNUSED pc = abuf->addr; |
| 1121 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1122 | |
| 1123 | { |
| 1124 | { |
| 1125 | BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31); |
| 1126 | SET_H_QBIT (opval); |
| 1127 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1128 | } |
| 1129 | { |
| 1130 | BI opval = SRLSI (GET_H_GRC (FLD (f_rm)), 31); |
| 1131 | SET_H_MBIT (opval); |
| 1132 | TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval); |
| 1133 | } |
| 1134 | { |
| 1135 | BI opval = ((EQSI (SRLSI (GET_H_GRC (FLD (f_rm)), 31), SRLSI (GET_H_GRC (FLD (f_rn)), 31))) ? (0) : (1)); |
| 1136 | SET_H_TBIT (opval); |
| 1137 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | #undef FLD |
| 1142 | } |
| 1143 | NEXT (vpc); |
| 1144 | |
| 1145 | CASE (sem, INSN_DIV0U_COMPACT) : /* div0u */ |
| 1146 | { |
| 1147 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1148 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1149 | #define FLD(f) abuf->fields.fmt_empty.f |
| 1150 | int UNUSED written = 0; |
| 1151 | IADDR UNUSED pc = abuf->addr; |
| 1152 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1153 | |
| 1154 | { |
| 1155 | { |
| 1156 | BI opval = 0; |
| 1157 | SET_H_TBIT (opval); |
| 1158 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1159 | } |
| 1160 | { |
| 1161 | BI opval = 0; |
| 1162 | SET_H_QBIT (opval); |
| 1163 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1164 | } |
| 1165 | { |
| 1166 | BI opval = 0; |
| 1167 | SET_H_MBIT (opval); |
| 1168 | TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval); |
| 1169 | } |
| 1170 | } |
| 1171 | |
| 1172 | #undef FLD |
| 1173 | } |
| 1174 | NEXT (vpc); |
| 1175 | |
| 1176 | CASE (sem, INSN_DIV1_COMPACT) : /* div1 $rm, $rn */ |
| 1177 | { |
| 1178 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1179 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1180 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1181 | int UNUSED written = 0; |
| 1182 | IADDR UNUSED pc = abuf->addr; |
| 1183 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1184 | |
| 1185 | { |
| 1186 | BI tmp_oldq; |
| 1187 | SI tmp_tmp0; |
| 1188 | UQI tmp_tmp1; |
| 1189 | tmp_oldq = GET_H_QBIT (); |
| 1190 | { |
| 1191 | BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31); |
| 1192 | SET_H_QBIT (opval); |
| 1193 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1194 | } |
| 1195 | { |
| 1196 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ())); |
| 1197 | SET_H_GRC (FLD (f_rn), opval); |
| 1198 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1199 | } |
| 1200 | if (NOTBI (tmp_oldq)) { |
| 1201 | if (NOTBI (GET_H_MBIT ())) { |
| 1202 | { |
| 1203 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); |
| 1204 | { |
| 1205 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 1206 | SET_H_GRC (FLD (f_rn), opval); |
| 1207 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1208 | } |
| 1209 | tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); |
| 1210 | if (NOTBI (GET_H_QBIT ())) { |
| 1211 | { |
| 1212 | BI opval = ((tmp_tmp1) ? (1) : (0)); |
| 1213 | SET_H_QBIT (opval); |
| 1214 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1215 | } |
| 1216 | } else { |
| 1217 | { |
| 1218 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); |
| 1219 | SET_H_QBIT (opval); |
| 1220 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1221 | } |
| 1222 | } |
| 1223 | } |
| 1224 | } else { |
| 1225 | { |
| 1226 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); |
| 1227 | { |
| 1228 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 1229 | SET_H_GRC (FLD (f_rn), opval); |
| 1230 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1231 | } |
| 1232 | tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); |
| 1233 | if (NOTBI (GET_H_QBIT ())) { |
| 1234 | { |
| 1235 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); |
| 1236 | SET_H_QBIT (opval); |
| 1237 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1238 | } |
| 1239 | } else { |
| 1240 | { |
| 1241 | BI opval = ((tmp_tmp1) ? (1) : (0)); |
| 1242 | SET_H_QBIT (opval); |
| 1243 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1244 | } |
| 1245 | } |
| 1246 | } |
| 1247 | } |
| 1248 | } else { |
| 1249 | if (NOTBI (GET_H_MBIT ())) { |
| 1250 | { |
| 1251 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); |
| 1252 | { |
| 1253 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); |
| 1254 | SET_H_GRC (FLD (f_rn), opval); |
| 1255 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1256 | } |
| 1257 | tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); |
| 1258 | if (NOTBI (GET_H_QBIT ())) { |
| 1259 | { |
| 1260 | BI opval = ((tmp_tmp1) ? (1) : (0)); |
| 1261 | SET_H_QBIT (opval); |
| 1262 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1263 | } |
| 1264 | } else { |
| 1265 | { |
| 1266 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); |
| 1267 | SET_H_QBIT (opval); |
| 1268 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1269 | } |
| 1270 | } |
| 1271 | } |
| 1272 | } else { |
| 1273 | { |
| 1274 | tmp_tmp0 = GET_H_GRC (FLD (f_rn)); |
| 1275 | { |
| 1276 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 1277 | SET_H_GRC (FLD (f_rn), opval); |
| 1278 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1279 | } |
| 1280 | tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); |
| 1281 | if (NOTBI (GET_H_QBIT ())) { |
| 1282 | { |
| 1283 | BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0)); |
| 1284 | SET_H_QBIT (opval); |
| 1285 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1286 | } |
| 1287 | } else { |
| 1288 | { |
| 1289 | BI opval = ((tmp_tmp1) ? (1) : (0)); |
| 1290 | SET_H_QBIT (opval); |
| 1291 | TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval); |
| 1292 | } |
| 1293 | } |
| 1294 | } |
| 1295 | } |
| 1296 | } |
| 1297 | { |
| 1298 | BI opval = ((EQBI (GET_H_QBIT (), GET_H_MBIT ())) ? (1) : (0)); |
| 1299 | SET_H_TBIT (opval); |
| 1300 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1301 | } |
| 1302 | } |
| 1303 | |
| 1304 | #undef FLD |
| 1305 | } |
| 1306 | NEXT (vpc); |
| 1307 | |
| 1308 | CASE (sem, INSN_DIVU_COMPACT) : /* divu r0, $rn */ |
| 1309 | { |
| 1310 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1311 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1312 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1313 | int UNUSED written = 0; |
| 1314 | IADDR UNUSED pc = abuf->addr; |
| 1315 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1316 | |
| 1317 | { |
| 1318 | SI opval = UDIVSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (((UINT) 0))); |
| 1319 | SET_H_GRC (FLD (f_rn), opval); |
| 1320 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1321 | } |
| 1322 | |
| 1323 | #undef FLD |
| 1324 | } |
| 1325 | NEXT (vpc); |
| 1326 | |
| 1327 | CASE (sem, INSN_MULR_COMPACT) : /* mulr r0, $rn */ |
| 1328 | { |
| 1329 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1330 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1331 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1332 | int UNUSED written = 0; |
| 1333 | IADDR UNUSED pc = abuf->addr; |
| 1334 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1335 | |
| 1336 | { |
| 1337 | SI opval = MULSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (((UINT) 0))); |
| 1338 | SET_H_GRC (FLD (f_rn), opval); |
| 1339 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1340 | } |
| 1341 | |
| 1342 | #undef FLD |
| 1343 | } |
| 1344 | NEXT (vpc); |
| 1345 | |
| 1346 | CASE (sem, INSN_DMULSL_COMPACT) : /* dmuls.l $rm, $rn */ |
| 1347 | { |
| 1348 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1349 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1350 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1351 | int UNUSED written = 0; |
| 1352 | IADDR UNUSED pc = abuf->addr; |
| 1353 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1354 | |
| 1355 | { |
| 1356 | DI tmp_result; |
| 1357 | tmp_result = MULDI (EXTSIDI (GET_H_GRC (FLD (f_rm))), EXTSIDI (GET_H_GRC (FLD (f_rn)))); |
| 1358 | { |
| 1359 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 1360 | SET_H_MACH (opval); |
| 1361 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 1362 | } |
| 1363 | { |
| 1364 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 1365 | SET_H_MACL (opval); |
| 1366 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 1367 | } |
| 1368 | } |
| 1369 | |
| 1370 | #undef FLD |
| 1371 | } |
| 1372 | NEXT (vpc); |
| 1373 | |
| 1374 | CASE (sem, INSN_DMULUL_COMPACT) : /* dmulu.l $rm, $rn */ |
| 1375 | { |
| 1376 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1377 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1378 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1379 | int UNUSED written = 0; |
| 1380 | IADDR UNUSED pc = abuf->addr; |
| 1381 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1382 | |
| 1383 | { |
| 1384 | DI tmp_result; |
| 1385 | tmp_result = MULDI (ZEXTSIDI (GET_H_GRC (FLD (f_rm))), ZEXTSIDI (GET_H_GRC (FLD (f_rn)))); |
| 1386 | { |
| 1387 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 1388 | SET_H_MACH (opval); |
| 1389 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 1390 | } |
| 1391 | { |
| 1392 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 1393 | SET_H_MACL (opval); |
| 1394 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 1395 | } |
| 1396 | } |
| 1397 | |
| 1398 | #undef FLD |
| 1399 | } |
| 1400 | NEXT (vpc); |
| 1401 | |
| 1402 | CASE (sem, INSN_DT_COMPACT) : /* dt $rn */ |
| 1403 | { |
| 1404 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1405 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1406 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1407 | int UNUSED written = 0; |
| 1408 | IADDR UNUSED pc = abuf->addr; |
| 1409 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1410 | |
| 1411 | { |
| 1412 | { |
| 1413 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1); |
| 1414 | SET_H_GRC (FLD (f_rn), opval); |
| 1415 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1416 | } |
| 1417 | { |
| 1418 | BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0); |
| 1419 | SET_H_TBIT (opval); |
| 1420 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1421 | } |
| 1422 | } |
| 1423 | |
| 1424 | #undef FLD |
| 1425 | } |
| 1426 | NEXT (vpc); |
| 1427 | |
| 1428 | CASE (sem, INSN_EXTSB_COMPACT) : /* exts.b $rm, $rn */ |
| 1429 | { |
| 1430 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1431 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1432 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1433 | int UNUSED written = 0; |
| 1434 | IADDR UNUSED pc = abuf->addr; |
| 1435 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1436 | |
| 1437 | { |
| 1438 | SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); |
| 1439 | SET_H_GRC (FLD (f_rn), opval); |
| 1440 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1441 | } |
| 1442 | |
| 1443 | #undef FLD |
| 1444 | } |
| 1445 | NEXT (vpc); |
| 1446 | |
| 1447 | CASE (sem, INSN_EXTSW_COMPACT) : /* exts.w $rm, $rn */ |
| 1448 | { |
| 1449 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1450 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1451 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1452 | int UNUSED written = 0; |
| 1453 | IADDR UNUSED pc = abuf->addr; |
| 1454 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1455 | |
| 1456 | { |
| 1457 | SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); |
| 1458 | SET_H_GRC (FLD (f_rn), opval); |
| 1459 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1460 | } |
| 1461 | |
| 1462 | #undef FLD |
| 1463 | } |
| 1464 | NEXT (vpc); |
| 1465 | |
| 1466 | CASE (sem, INSN_EXTUB_COMPACT) : /* extu.b $rm, $rn */ |
| 1467 | { |
| 1468 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1469 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1470 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1471 | int UNUSED written = 0; |
| 1472 | IADDR UNUSED pc = abuf->addr; |
| 1473 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1474 | |
| 1475 | { |
| 1476 | SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); |
| 1477 | SET_H_GRC (FLD (f_rn), opval); |
| 1478 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1479 | } |
| 1480 | |
| 1481 | #undef FLD |
| 1482 | } |
| 1483 | NEXT (vpc); |
| 1484 | |
| 1485 | CASE (sem, INSN_EXTUW_COMPACT) : /* extu.w $rm, $rn */ |
| 1486 | { |
| 1487 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1488 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1489 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1490 | int UNUSED written = 0; |
| 1491 | IADDR UNUSED pc = abuf->addr; |
| 1492 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1493 | |
| 1494 | { |
| 1495 | SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); |
| 1496 | SET_H_GRC (FLD (f_rn), opval); |
| 1497 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1498 | } |
| 1499 | |
| 1500 | #undef FLD |
| 1501 | } |
| 1502 | NEXT (vpc); |
| 1503 | |
| 1504 | CASE (sem, INSN_FABS_COMPACT) : /* fabs $fsdn */ |
| 1505 | { |
| 1506 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1507 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1508 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1509 | int UNUSED written = 0; |
| 1510 | IADDR UNUSED pc = abuf->addr; |
| 1511 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1512 | |
| 1513 | if (GET_H_PRBIT ()) { |
| 1514 | { |
| 1515 | DF opval = sh64_fabsd (current_cpu, GET_H_FSD (FLD (f_rn))); |
| 1516 | SET_H_FSD (FLD (f_rn), opval); |
| 1517 | written |= (1 << 2); |
| 1518 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1519 | } |
| 1520 | } else { |
| 1521 | { |
| 1522 | DF opval = sh64_fabss (current_cpu, GET_H_FSD (FLD (f_rn))); |
| 1523 | SET_H_FSD (FLD (f_rn), opval); |
| 1524 | written |= (1 << 2); |
| 1525 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1526 | } |
| 1527 | } |
| 1528 | |
| 1529 | abuf->written = written; |
| 1530 | #undef FLD |
| 1531 | } |
| 1532 | NEXT (vpc); |
| 1533 | |
| 1534 | CASE (sem, INSN_FADD_COMPACT) : /* fadd $fsdm, $fsdn */ |
| 1535 | { |
| 1536 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1537 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1538 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1539 | int UNUSED written = 0; |
| 1540 | IADDR UNUSED pc = abuf->addr; |
| 1541 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1542 | |
| 1543 | if (GET_H_PRBIT ()) { |
| 1544 | { |
| 1545 | DF opval = sh64_faddd (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); |
| 1546 | SET_H_FSD (FLD (f_rn), opval); |
| 1547 | written |= (1 << 3); |
| 1548 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1549 | } |
| 1550 | } else { |
| 1551 | { |
| 1552 | DF opval = sh64_fadds (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); |
| 1553 | SET_H_FSD (FLD (f_rn), opval); |
| 1554 | written |= (1 << 3); |
| 1555 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1556 | } |
| 1557 | } |
| 1558 | |
| 1559 | abuf->written = written; |
| 1560 | #undef FLD |
| 1561 | } |
| 1562 | NEXT (vpc); |
| 1563 | |
| 1564 | CASE (sem, INSN_FCMPEQ_COMPACT) : /* fcmp/eq $fsdm, $fsdn */ |
| 1565 | { |
| 1566 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1567 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1568 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1569 | int UNUSED written = 0; |
| 1570 | IADDR UNUSED pc = abuf->addr; |
| 1571 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1572 | |
| 1573 | if (GET_H_PRBIT ()) { |
| 1574 | { |
| 1575 | BI opval = sh64_fcmpeqd (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); |
| 1576 | SET_H_TBIT (opval); |
| 1577 | written |= (1 << 3); |
| 1578 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1579 | } |
| 1580 | } else { |
| 1581 | { |
| 1582 | BI opval = sh64_fcmpeqs (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); |
| 1583 | SET_H_TBIT (opval); |
| 1584 | written |= (1 << 3); |
| 1585 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1586 | } |
| 1587 | } |
| 1588 | |
| 1589 | abuf->written = written; |
| 1590 | #undef FLD |
| 1591 | } |
| 1592 | NEXT (vpc); |
| 1593 | |
| 1594 | CASE (sem, INSN_FCMPGT_COMPACT) : /* fcmp/gt $fsdm, $fsdn */ |
| 1595 | { |
| 1596 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1597 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1598 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1599 | int UNUSED written = 0; |
| 1600 | IADDR UNUSED pc = abuf->addr; |
| 1601 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1602 | |
| 1603 | if (GET_H_PRBIT ()) { |
| 1604 | { |
| 1605 | BI opval = sh64_fcmpgtd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); |
| 1606 | SET_H_TBIT (opval); |
| 1607 | written |= (1 << 3); |
| 1608 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1609 | } |
| 1610 | } else { |
| 1611 | { |
| 1612 | BI opval = sh64_fcmpgts (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); |
| 1613 | SET_H_TBIT (opval); |
| 1614 | written |= (1 << 3); |
| 1615 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 1616 | } |
| 1617 | } |
| 1618 | |
| 1619 | abuf->written = written; |
| 1620 | #undef FLD |
| 1621 | } |
| 1622 | NEXT (vpc); |
| 1623 | |
| 1624 | CASE (sem, INSN_FCNVDS_COMPACT) : /* fcnvds $drn, fpul */ |
| 1625 | { |
| 1626 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1627 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1628 | #define FLD(f) abuf->fields.sfmt_fmov8_compact.f |
| 1629 | int UNUSED written = 0; |
| 1630 | IADDR UNUSED pc = abuf->addr; |
| 1631 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1632 | |
| 1633 | { |
| 1634 | SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn))); |
| 1635 | CPU (h_fr[((UINT) 32)]) = opval; |
| 1636 | TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); |
| 1637 | } |
| 1638 | |
| 1639 | #undef FLD |
| 1640 | } |
| 1641 | NEXT (vpc); |
| 1642 | |
| 1643 | CASE (sem, INSN_FCNVSD_COMPACT) : /* fcnvsd fpul, $drn */ |
| 1644 | { |
| 1645 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1646 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1647 | #define FLD(f) abuf->fields.sfmt_fmov8_compact.f |
| 1648 | int UNUSED written = 0; |
| 1649 | IADDR UNUSED pc = abuf->addr; |
| 1650 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1651 | |
| 1652 | { |
| 1653 | DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)])); |
| 1654 | SET_H_DRC (FLD (f_dn), opval); |
| 1655 | TRACE_RESULT (current_cpu, abuf, "drc", 'f', opval); |
| 1656 | } |
| 1657 | |
| 1658 | #undef FLD |
| 1659 | } |
| 1660 | NEXT (vpc); |
| 1661 | |
| 1662 | CASE (sem, INSN_FDIV_COMPACT) : /* fdiv $fsdm, $fsdn */ |
| 1663 | { |
| 1664 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1665 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1666 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1667 | int UNUSED written = 0; |
| 1668 | IADDR UNUSED pc = abuf->addr; |
| 1669 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1670 | |
| 1671 | if (GET_H_PRBIT ()) { |
| 1672 | { |
| 1673 | DF opval = sh64_fdivd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); |
| 1674 | SET_H_FSD (FLD (f_rn), opval); |
| 1675 | written |= (1 << 3); |
| 1676 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1677 | } |
| 1678 | } else { |
| 1679 | { |
| 1680 | DF opval = sh64_fdivs (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); |
| 1681 | SET_H_FSD (FLD (f_rn), opval); |
| 1682 | written |= (1 << 3); |
| 1683 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1684 | } |
| 1685 | } |
| 1686 | |
| 1687 | abuf->written = written; |
| 1688 | #undef FLD |
| 1689 | } |
| 1690 | NEXT (vpc); |
| 1691 | |
| 1692 | CASE (sem, INSN_FIPR_COMPACT) : /* fipr $fvm, $fvn */ |
| 1693 | { |
| 1694 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1695 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1696 | #define FLD(f) abuf->fields.sfmt_fipr_compact.f |
| 1697 | int UNUSED written = 0; |
| 1698 | IADDR UNUSED pc = abuf->addr; |
| 1699 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1700 | |
| 1701 | sh64_fipr (current_cpu, FLD (f_vm), FLD (f_vn)); |
| 1702 | |
| 1703 | #undef FLD |
| 1704 | } |
| 1705 | NEXT (vpc); |
| 1706 | |
| 1707 | CASE (sem, INSN_FLDS_COMPACT) : /* flds $frn, fpul */ |
| 1708 | { |
| 1709 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1710 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1711 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1712 | int UNUSED written = 0; |
| 1713 | IADDR UNUSED pc = abuf->addr; |
| 1714 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1715 | |
| 1716 | { |
| 1717 | SF opval = GET_H_FRC (FLD (f_rn)); |
| 1718 | CPU (h_fr[((UINT) 32)]) = opval; |
| 1719 | TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); |
| 1720 | } |
| 1721 | |
| 1722 | #undef FLD |
| 1723 | } |
| 1724 | NEXT (vpc); |
| 1725 | |
| 1726 | CASE (sem, INSN_FLDI0_COMPACT) : /* fldi0 $frn */ |
| 1727 | { |
| 1728 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1729 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1730 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1731 | int UNUSED written = 0; |
| 1732 | IADDR UNUSED pc = abuf->addr; |
| 1733 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1734 | |
| 1735 | { |
| 1736 | SF opval = sh64_fldi0 (current_cpu); |
| 1737 | SET_H_FRC (FLD (f_rn), opval); |
| 1738 | TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); |
| 1739 | } |
| 1740 | |
| 1741 | #undef FLD |
| 1742 | } |
| 1743 | NEXT (vpc); |
| 1744 | |
| 1745 | CASE (sem, INSN_FLDI1_COMPACT) : /* fldi1 $frn */ |
| 1746 | { |
| 1747 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1748 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1749 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1750 | int UNUSED written = 0; |
| 1751 | IADDR UNUSED pc = abuf->addr; |
| 1752 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1753 | |
| 1754 | { |
| 1755 | SF opval = sh64_fldi1 (current_cpu); |
| 1756 | SET_H_FRC (FLD (f_rn), opval); |
| 1757 | TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); |
| 1758 | } |
| 1759 | |
| 1760 | #undef FLD |
| 1761 | } |
| 1762 | NEXT (vpc); |
| 1763 | |
| 1764 | CASE (sem, INSN_FLOAT_COMPACT) : /* float fpul, $fsdn */ |
| 1765 | { |
| 1766 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1767 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1768 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 1769 | int UNUSED written = 0; |
| 1770 | IADDR UNUSED pc = abuf->addr; |
| 1771 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1772 | |
| 1773 | if (GET_H_PRBIT ()) { |
| 1774 | { |
| 1775 | DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)])); |
| 1776 | SET_H_FSD (FLD (f_rn), opval); |
| 1777 | written |= (1 << 2); |
| 1778 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1779 | } |
| 1780 | } else { |
| 1781 | { |
| 1782 | DF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)])); |
| 1783 | SET_H_FSD (FLD (f_rn), opval); |
| 1784 | written |= (1 << 2); |
| 1785 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 1786 | } |
| 1787 | } |
| 1788 | |
| 1789 | abuf->written = written; |
| 1790 | #undef FLD |
| 1791 | } |
| 1792 | NEXT (vpc); |
| 1793 | |
| 1794 | CASE (sem, INSN_FMAC_COMPACT) : /* fmac fr0, $frm, $frn */ |
| 1795 | { |
| 1796 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1797 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1798 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1799 | int UNUSED written = 0; |
| 1800 | IADDR UNUSED pc = abuf->addr; |
| 1801 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1802 | |
| 1803 | { |
| 1804 | SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); |
| 1805 | SET_H_FRC (FLD (f_rn), opval); |
| 1806 | TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); |
| 1807 | } |
| 1808 | |
| 1809 | #undef FLD |
| 1810 | } |
| 1811 | NEXT (vpc); |
| 1812 | |
| 1813 | CASE (sem, INSN_FMOV1_COMPACT) : /* fmov $fmovm, $fmovn */ |
| 1814 | { |
| 1815 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1816 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1817 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1818 | int UNUSED written = 0; |
| 1819 | IADDR UNUSED pc = abuf->addr; |
| 1820 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1821 | |
| 1822 | { |
| 1823 | DF opval = GET_H_FMOV (FLD (f_rm)); |
| 1824 | SET_H_FMOV (FLD (f_rn), opval); |
| 1825 | TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); |
| 1826 | } |
| 1827 | |
| 1828 | #undef FLD |
| 1829 | } |
| 1830 | NEXT (vpc); |
| 1831 | |
| 1832 | CASE (sem, INSN_FMOV2_COMPACT) : /* fmov @$rm, $fmovn */ |
| 1833 | { |
| 1834 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1835 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1836 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1837 | int UNUSED written = 0; |
| 1838 | IADDR UNUSED pc = abuf->addr; |
| 1839 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1840 | |
| 1841 | if (NOTBI (GET_H_SZBIT ())) { |
| 1842 | { |
| 1843 | DF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 1844 | SET_H_FMOV (FLD (f_rn), opval); |
| 1845 | written |= (1 << 4); |
| 1846 | TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); |
| 1847 | } |
| 1848 | } else { |
| 1849 | { |
| 1850 | DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 1851 | SET_H_FMOV (FLD (f_rn), opval); |
| 1852 | written |= (1 << 4); |
| 1853 | TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); |
| 1854 | } |
| 1855 | } |
| 1856 | |
| 1857 | abuf->written = written; |
| 1858 | #undef FLD |
| 1859 | } |
| 1860 | NEXT (vpc); |
| 1861 | |
| 1862 | CASE (sem, INSN_FMOV3_COMPACT) : /* fmov @${rm}+, fmovn */ |
| 1863 | { |
| 1864 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1865 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1866 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1867 | int UNUSED written = 0; |
| 1868 | IADDR UNUSED pc = abuf->addr; |
| 1869 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1870 | |
| 1871 | if (NOTBI (GET_H_SZBIT ())) { |
| 1872 | { |
| 1873 | { |
| 1874 | DF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 1875 | SET_H_FMOV (FLD (f_rn), opval); |
| 1876 | written |= (1 << 4); |
| 1877 | TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); |
| 1878 | } |
| 1879 | { |
| 1880 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); |
| 1881 | SET_H_GRC (FLD (f_rm), opval); |
| 1882 | written |= (1 << 5); |
| 1883 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1884 | } |
| 1885 | } |
| 1886 | } else { |
| 1887 | { |
| 1888 | { |
| 1889 | DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 1890 | SET_H_FMOV (FLD (f_rn), opval); |
| 1891 | written |= (1 << 4); |
| 1892 | TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); |
| 1893 | } |
| 1894 | { |
| 1895 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8); |
| 1896 | SET_H_GRC (FLD (f_rm), opval); |
| 1897 | written |= (1 << 5); |
| 1898 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1899 | } |
| 1900 | } |
| 1901 | } |
| 1902 | |
| 1903 | abuf->written = written; |
| 1904 | #undef FLD |
| 1905 | } |
| 1906 | NEXT (vpc); |
| 1907 | |
| 1908 | CASE (sem, INSN_FMOV4_COMPACT) : /* fmov @(r0, $rm), $fmovn */ |
| 1909 | { |
| 1910 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1911 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1912 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1913 | int UNUSED written = 0; |
| 1914 | IADDR UNUSED pc = abuf->addr; |
| 1915 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1916 | |
| 1917 | if (NOTBI (GET_H_SZBIT ())) { |
| 1918 | { |
| 1919 | DF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); |
| 1920 | SET_H_FMOV (FLD (f_rn), opval); |
| 1921 | written |= (1 << 5); |
| 1922 | TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); |
| 1923 | } |
| 1924 | } else { |
| 1925 | { |
| 1926 | DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); |
| 1927 | SET_H_FMOV (FLD (f_rn), opval); |
| 1928 | written |= (1 << 5); |
| 1929 | TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); |
| 1930 | } |
| 1931 | } |
| 1932 | |
| 1933 | abuf->written = written; |
| 1934 | #undef FLD |
| 1935 | } |
| 1936 | NEXT (vpc); |
| 1937 | |
| 1938 | CASE (sem, INSN_FMOV5_COMPACT) : /* fmov $fmovm, @$rn */ |
| 1939 | { |
| 1940 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1941 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1942 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1943 | int UNUSED written = 0; |
| 1944 | IADDR UNUSED pc = abuf->addr; |
| 1945 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1946 | |
| 1947 | if (NOTBI (GET_H_SZBIT ())) { |
| 1948 | { |
| 1949 | SF opval = GET_H_FMOV (FLD (f_rm)); |
| 1950 | SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 1951 | written |= (1 << 4); |
| 1952 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 1953 | } |
| 1954 | } else { |
| 1955 | { |
| 1956 | DF opval = GET_H_FMOV (FLD (f_rm)); |
| 1957 | SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 1958 | written |= (1 << 3); |
| 1959 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 1960 | } |
| 1961 | } |
| 1962 | |
| 1963 | abuf->written = written; |
| 1964 | #undef FLD |
| 1965 | } |
| 1966 | NEXT (vpc); |
| 1967 | |
| 1968 | CASE (sem, INSN_FMOV6_COMPACT) : /* fmov $fmovm, @-$rn */ |
| 1969 | { |
| 1970 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 1971 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 1972 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 1973 | int UNUSED written = 0; |
| 1974 | IADDR UNUSED pc = abuf->addr; |
| 1975 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 1976 | |
| 1977 | if (NOTBI (GET_H_SZBIT ())) { |
| 1978 | { |
| 1979 | { |
| 1980 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 1981 | SET_H_GRC (FLD (f_rn), opval); |
| 1982 | written |= (1 << 5); |
| 1983 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1984 | } |
| 1985 | { |
| 1986 | SF opval = GET_H_FMOV (FLD (f_rm)); |
| 1987 | SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 1988 | written |= (1 << 4); |
| 1989 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 1990 | } |
| 1991 | } |
| 1992 | } else { |
| 1993 | { |
| 1994 | { |
| 1995 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8); |
| 1996 | SET_H_GRC (FLD (f_rn), opval); |
| 1997 | written |= (1 << 5); |
| 1998 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 1999 | } |
| 2000 | { |
| 2001 | DF opval = GET_H_FMOV (FLD (f_rm)); |
| 2002 | SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 2003 | written |= (1 << 3); |
| 2004 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 2005 | } |
| 2006 | } |
| 2007 | } |
| 2008 | |
| 2009 | abuf->written = written; |
| 2010 | #undef FLD |
| 2011 | } |
| 2012 | NEXT (vpc); |
| 2013 | |
| 2014 | CASE (sem, INSN_FMOV7_COMPACT) : /* fmov $fmovm, @(r0, $rn) */ |
| 2015 | { |
| 2016 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2017 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2018 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2019 | int UNUSED written = 0; |
| 2020 | IADDR UNUSED pc = abuf->addr; |
| 2021 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2022 | |
| 2023 | if (NOTBI (GET_H_SZBIT ())) { |
| 2024 | { |
| 2025 | SF opval = GET_H_FMOV (FLD (f_rm)); |
| 2026 | SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); |
| 2027 | written |= (1 << 5); |
| 2028 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 2029 | } |
| 2030 | } else { |
| 2031 | { |
| 2032 | DF opval = GET_H_FMOV (FLD (f_rm)); |
| 2033 | SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); |
| 2034 | written |= (1 << 4); |
| 2035 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 2036 | } |
| 2037 | } |
| 2038 | |
| 2039 | abuf->written = written; |
| 2040 | #undef FLD |
| 2041 | } |
| 2042 | NEXT (vpc); |
| 2043 | |
| 2044 | CASE (sem, INSN_FMOV8_COMPACT) : /* fmov.d @($imm12x8, $rm), $drn */ |
| 2045 | { |
| 2046 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2047 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2048 | #define FLD(f) abuf->fields.sfmt_fmov8_compact.f |
| 2049 | int UNUSED written = 0; |
| 2050 | IADDR UNUSED pc = abuf->addr; |
| 2051 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2052 | |
| 2053 | { |
| 2054 | DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm12x8))); |
| 2055 | SET_H_DRC (FLD (f_dn), opval); |
| 2056 | TRACE_RESULT (current_cpu, abuf, "drc", 'f', opval); |
| 2057 | } |
| 2058 | |
| 2059 | #undef FLD |
| 2060 | } |
| 2061 | NEXT (vpc); |
| 2062 | |
| 2063 | CASE (sem, INSN_FMOV9_COMPACT) : /* mov.l $drm, @($imm12x8, $rn) */ |
| 2064 | { |
| 2065 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2066 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2067 | #define FLD(f) abuf->fields.sfmt_fmov9_compact.f |
| 2068 | int UNUSED written = 0; |
| 2069 | IADDR UNUSED pc = abuf->addr; |
| 2070 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2071 | |
| 2072 | { |
| 2073 | DF opval = GET_H_DRC (FLD (f_dm)); |
| 2074 | SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm12x8)), opval); |
| 2075 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 2076 | } |
| 2077 | |
| 2078 | #undef FLD |
| 2079 | } |
| 2080 | NEXT (vpc); |
| 2081 | |
| 2082 | CASE (sem, INSN_FMUL_COMPACT) : /* fmul $fsdm, $fsdn */ |
| 2083 | { |
| 2084 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2085 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2086 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2087 | int UNUSED written = 0; |
| 2088 | IADDR UNUSED pc = abuf->addr; |
| 2089 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2090 | |
| 2091 | if (GET_H_PRBIT ()) { |
| 2092 | { |
| 2093 | DF opval = sh64_fmuld (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); |
| 2094 | SET_H_FSD (FLD (f_rn), opval); |
| 2095 | written |= (1 << 3); |
| 2096 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2097 | } |
| 2098 | } else { |
| 2099 | { |
| 2100 | DF opval = sh64_fmuls (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); |
| 2101 | SET_H_FSD (FLD (f_rn), opval); |
| 2102 | written |= (1 << 3); |
| 2103 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2104 | } |
| 2105 | } |
| 2106 | |
| 2107 | abuf->written = written; |
| 2108 | #undef FLD |
| 2109 | } |
| 2110 | NEXT (vpc); |
| 2111 | |
| 2112 | CASE (sem, INSN_FNEG_COMPACT) : /* fneg $fsdn */ |
| 2113 | { |
| 2114 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2115 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2116 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2117 | int UNUSED written = 0; |
| 2118 | IADDR UNUSED pc = abuf->addr; |
| 2119 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2120 | |
| 2121 | if (GET_H_PRBIT ()) { |
| 2122 | { |
| 2123 | DF opval = sh64_fnegd (current_cpu, GET_H_FSD (FLD (f_rn))); |
| 2124 | SET_H_FSD (FLD (f_rn), opval); |
| 2125 | written |= (1 << 2); |
| 2126 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2127 | } |
| 2128 | } else { |
| 2129 | { |
| 2130 | DF opval = sh64_fnegs (current_cpu, GET_H_FSD (FLD (f_rn))); |
| 2131 | SET_H_FSD (FLD (f_rn), opval); |
| 2132 | written |= (1 << 2); |
| 2133 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2134 | } |
| 2135 | } |
| 2136 | |
| 2137 | abuf->written = written; |
| 2138 | #undef FLD |
| 2139 | } |
| 2140 | NEXT (vpc); |
| 2141 | |
| 2142 | CASE (sem, INSN_FRCHG_COMPACT) : /* frchg */ |
| 2143 | { |
| 2144 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2145 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2146 | #define FLD(f) abuf->fields.fmt_empty.f |
| 2147 | int UNUSED written = 0; |
| 2148 | IADDR UNUSED pc = abuf->addr; |
| 2149 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2150 | |
| 2151 | { |
| 2152 | BI opval = NOTBI (GET_H_FRBIT ()); |
| 2153 | SET_H_FRBIT (opval); |
| 2154 | TRACE_RESULT (current_cpu, abuf, "frbit", 'x', opval); |
| 2155 | } |
| 2156 | |
| 2157 | #undef FLD |
| 2158 | } |
| 2159 | NEXT (vpc); |
| 2160 | |
| 2161 | CASE (sem, INSN_FSCHG_COMPACT) : /* fschg */ |
| 2162 | { |
| 2163 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2164 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2165 | #define FLD(f) abuf->fields.fmt_empty.f |
| 2166 | int UNUSED written = 0; |
| 2167 | IADDR UNUSED pc = abuf->addr; |
| 2168 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2169 | |
| 2170 | { |
| 2171 | BI opval = NOTBI (GET_H_SZBIT ()); |
| 2172 | SET_H_SZBIT (opval); |
| 2173 | TRACE_RESULT (current_cpu, abuf, "szbit", 'x', opval); |
| 2174 | } |
| 2175 | |
| 2176 | #undef FLD |
| 2177 | } |
| 2178 | NEXT (vpc); |
| 2179 | |
| 2180 | CASE (sem, INSN_FSQRT_COMPACT) : /* fsqrt $fsdn */ |
| 2181 | { |
| 2182 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2183 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2184 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2185 | int UNUSED written = 0; |
| 2186 | IADDR UNUSED pc = abuf->addr; |
| 2187 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2188 | |
| 2189 | if (GET_H_PRBIT ()) { |
| 2190 | { |
| 2191 | DF opval = sh64_fsqrtd (current_cpu, GET_H_FSD (FLD (f_rn))); |
| 2192 | SET_H_FSD (FLD (f_rn), opval); |
| 2193 | written |= (1 << 2); |
| 2194 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2195 | } |
| 2196 | } else { |
| 2197 | { |
| 2198 | DF opval = sh64_fsqrts (current_cpu, GET_H_FSD (FLD (f_rn))); |
| 2199 | SET_H_FSD (FLD (f_rn), opval); |
| 2200 | written |= (1 << 2); |
| 2201 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2202 | } |
| 2203 | } |
| 2204 | |
| 2205 | abuf->written = written; |
| 2206 | #undef FLD |
| 2207 | } |
| 2208 | NEXT (vpc); |
| 2209 | |
| 2210 | CASE (sem, INSN_FSTS_COMPACT) : /* fsts fpul, $frn */ |
| 2211 | { |
| 2212 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2213 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2214 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2215 | int UNUSED written = 0; |
| 2216 | IADDR UNUSED pc = abuf->addr; |
| 2217 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2218 | |
| 2219 | { |
| 2220 | SF opval = CPU (h_fr[((UINT) 32)]); |
| 2221 | SET_H_FRC (FLD (f_rn), opval); |
| 2222 | TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); |
| 2223 | } |
| 2224 | |
| 2225 | #undef FLD |
| 2226 | } |
| 2227 | NEXT (vpc); |
| 2228 | |
| 2229 | CASE (sem, INSN_FSUB_COMPACT) : /* fsub $fsdm, $fsdn */ |
| 2230 | { |
| 2231 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2232 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2233 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2234 | int UNUSED written = 0; |
| 2235 | IADDR UNUSED pc = abuf->addr; |
| 2236 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2237 | |
| 2238 | if (GET_H_PRBIT ()) { |
| 2239 | { |
| 2240 | DF opval = sh64_fsubd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); |
| 2241 | SET_H_FSD (FLD (f_rn), opval); |
| 2242 | written |= (1 << 3); |
| 2243 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2244 | } |
| 2245 | } else { |
| 2246 | { |
| 2247 | DF opval = sh64_fsubs (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); |
| 2248 | SET_H_FSD (FLD (f_rn), opval); |
| 2249 | written |= (1 << 3); |
| 2250 | TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); |
| 2251 | } |
| 2252 | } |
| 2253 | |
| 2254 | abuf->written = written; |
| 2255 | #undef FLD |
| 2256 | } |
| 2257 | NEXT (vpc); |
| 2258 | |
| 2259 | CASE (sem, INSN_FTRC_COMPACT) : /* ftrc $fsdn, fpul */ |
| 2260 | { |
| 2261 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2262 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2263 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2264 | int UNUSED written = 0; |
| 2265 | IADDR UNUSED pc = abuf->addr; |
| 2266 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2267 | |
| 2268 | { |
| 2269 | SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_FSD (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FSD (FLD (f_rn))))); |
| 2270 | CPU (h_fr[((UINT) 32)]) = opval; |
| 2271 | TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); |
| 2272 | } |
| 2273 | |
| 2274 | #undef FLD |
| 2275 | } |
| 2276 | NEXT (vpc); |
| 2277 | |
| 2278 | CASE (sem, INSN_FTRV_COMPACT) : /* ftrv xmtrx, $fvn */ |
| 2279 | { |
| 2280 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2281 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2282 | #define FLD(f) abuf->fields.sfmt_fipr_compact.f |
| 2283 | int UNUSED written = 0; |
| 2284 | IADDR UNUSED pc = abuf->addr; |
| 2285 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2286 | |
| 2287 | sh64_ftrv (current_cpu, FLD (f_vn)); |
| 2288 | |
| 2289 | #undef FLD |
| 2290 | } |
| 2291 | NEXT (vpc); |
| 2292 | |
| 2293 | CASE (sem, INSN_JMP_COMPACT) : /* jmp @$rn */ |
| 2294 | { |
| 2295 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2296 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2297 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2298 | int UNUSED written = 0; |
| 2299 | IADDR UNUSED pc = abuf->addr; |
| 2300 | SEM_BRANCH_INIT |
| 2301 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2302 | |
| 2303 | { |
| 2304 | { |
| 2305 | UDI opval = ADDDI (pc, 2); |
| 2306 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 2307 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 2308 | } |
| 2309 | ((void) 0); /*nop*/ |
| 2310 | { |
| 2311 | { |
| 2312 | UDI opval = GET_H_GRC (FLD (f_rn)); |
| 2313 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 2314 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 2315 | } |
| 2316 | } |
| 2317 | ((void) 0); /*nop*/ |
| 2318 | } |
| 2319 | |
| 2320 | SEM_BRANCH_FINI (vpc); |
| 2321 | #undef FLD |
| 2322 | } |
| 2323 | NEXT (vpc); |
| 2324 | |
| 2325 | CASE (sem, INSN_JSR_COMPACT) : /* jsr @$rn */ |
| 2326 | { |
| 2327 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2328 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2329 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2330 | int UNUSED written = 0; |
| 2331 | IADDR UNUSED pc = abuf->addr; |
| 2332 | SEM_BRANCH_INIT |
| 2333 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2334 | |
| 2335 | { |
| 2336 | { |
| 2337 | { |
| 2338 | SI opval = ADDDI (pc, 4); |
| 2339 | SET_H_PR (opval); |
| 2340 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); |
| 2341 | } |
| 2342 | } |
| 2343 | { |
| 2344 | UDI opval = ADDDI (pc, 2); |
| 2345 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 2346 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 2347 | } |
| 2348 | ((void) 0); /*nop*/ |
| 2349 | { |
| 2350 | { |
| 2351 | UDI opval = GET_H_GRC (FLD (f_rn)); |
| 2352 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 2353 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 2354 | } |
| 2355 | } |
| 2356 | ((void) 0); /*nop*/ |
| 2357 | } |
| 2358 | |
| 2359 | SEM_BRANCH_FINI (vpc); |
| 2360 | #undef FLD |
| 2361 | } |
| 2362 | NEXT (vpc); |
| 2363 | |
| 2364 | CASE (sem, INSN_LDC_GBR_COMPACT) : /* ldc $rn, gbr */ |
| 2365 | { |
| 2366 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2367 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2368 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2369 | int UNUSED written = 0; |
| 2370 | IADDR UNUSED pc = abuf->addr; |
| 2371 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2372 | |
| 2373 | { |
| 2374 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 2375 | SET_H_GBR (opval); |
| 2376 | TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval); |
| 2377 | } |
| 2378 | |
| 2379 | #undef FLD |
| 2380 | } |
| 2381 | NEXT (vpc); |
| 2382 | |
| 2383 | CASE (sem, INSN_LDC_VBR_COMPACT) : /* ldc $rn, vbr */ |
| 2384 | { |
| 2385 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2386 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2387 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2388 | int UNUSED written = 0; |
| 2389 | IADDR UNUSED pc = abuf->addr; |
| 2390 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2391 | |
| 2392 | { |
| 2393 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 2394 | SET_H_VBR (opval); |
| 2395 | TRACE_RESULT (current_cpu, abuf, "vbr", 'x', opval); |
| 2396 | } |
| 2397 | |
| 2398 | #undef FLD |
| 2399 | } |
| 2400 | NEXT (vpc); |
| 2401 | |
| 2402 | CASE (sem, INSN_LDC_SR_COMPACT) : /* ldc $rn, sr */ |
| 2403 | { |
| 2404 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2405 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2406 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2407 | int UNUSED written = 0; |
| 2408 | IADDR UNUSED pc = abuf->addr; |
| 2409 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2410 | |
| 2411 | { |
| 2412 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 2413 | CPU (h_sr) = opval; |
| 2414 | TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); |
| 2415 | } |
| 2416 | |
| 2417 | #undef FLD |
| 2418 | } |
| 2419 | NEXT (vpc); |
| 2420 | |
| 2421 | CASE (sem, INSN_LDCL_GBR_COMPACT) : /* ldc.l @${rn}+, gbr */ |
| 2422 | { |
| 2423 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2424 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2425 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2426 | int UNUSED written = 0; |
| 2427 | IADDR UNUSED pc = abuf->addr; |
| 2428 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2429 | |
| 2430 | { |
| 2431 | { |
| 2432 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2433 | SET_H_GBR (opval); |
| 2434 | TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval); |
| 2435 | } |
| 2436 | { |
| 2437 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2438 | SET_H_GRC (FLD (f_rn), opval); |
| 2439 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2440 | } |
| 2441 | } |
| 2442 | |
| 2443 | #undef FLD |
| 2444 | } |
| 2445 | NEXT (vpc); |
| 2446 | |
| 2447 | CASE (sem, INSN_LDCL_VBR_COMPACT) : /* ldc.l @${rn}+, vbr */ |
| 2448 | { |
| 2449 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2450 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2451 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2452 | int UNUSED written = 0; |
| 2453 | IADDR UNUSED pc = abuf->addr; |
| 2454 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2455 | |
| 2456 | { |
| 2457 | { |
| 2458 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2459 | SET_H_VBR (opval); |
| 2460 | TRACE_RESULT (current_cpu, abuf, "vbr", 'x', opval); |
| 2461 | } |
| 2462 | { |
| 2463 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2464 | SET_H_GRC (FLD (f_rn), opval); |
| 2465 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2466 | } |
| 2467 | } |
| 2468 | |
| 2469 | #undef FLD |
| 2470 | } |
| 2471 | NEXT (vpc); |
| 2472 | |
| 2473 | CASE (sem, INSN_LDS_FPSCR_COMPACT) : /* lds $rn, fpscr */ |
| 2474 | { |
| 2475 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2476 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2477 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2478 | int UNUSED written = 0; |
| 2479 | IADDR UNUSED pc = abuf->addr; |
| 2480 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2481 | |
| 2482 | { |
| 2483 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 2484 | CPU (h_fpscr) = opval; |
| 2485 | TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); |
| 2486 | } |
| 2487 | |
| 2488 | #undef FLD |
| 2489 | } |
| 2490 | NEXT (vpc); |
| 2491 | |
| 2492 | CASE (sem, INSN_LDSL_FPSCR_COMPACT) : /* lds.l @${rn}+, fpscr */ |
| 2493 | { |
| 2494 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2495 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2496 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2497 | int UNUSED written = 0; |
| 2498 | IADDR UNUSED pc = abuf->addr; |
| 2499 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2500 | |
| 2501 | { |
| 2502 | { |
| 2503 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2504 | CPU (h_fpscr) = opval; |
| 2505 | TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); |
| 2506 | } |
| 2507 | { |
| 2508 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2509 | SET_H_GRC (FLD (f_rn), opval); |
| 2510 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2511 | } |
| 2512 | } |
| 2513 | |
| 2514 | #undef FLD |
| 2515 | } |
| 2516 | NEXT (vpc); |
| 2517 | |
| 2518 | CASE (sem, INSN_LDS_FPUL_COMPACT) : /* lds $rn, fpul */ |
| 2519 | { |
| 2520 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2521 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2522 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2523 | int UNUSED written = 0; |
| 2524 | IADDR UNUSED pc = abuf->addr; |
| 2525 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2526 | |
| 2527 | { |
| 2528 | SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn))); |
| 2529 | CPU (h_fr[((UINT) 32)]) = opval; |
| 2530 | TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); |
| 2531 | } |
| 2532 | |
| 2533 | #undef FLD |
| 2534 | } |
| 2535 | NEXT (vpc); |
| 2536 | |
| 2537 | CASE (sem, INSN_LDSL_FPUL_COMPACT) : /* lds.l @${rn}+, fpul */ |
| 2538 | { |
| 2539 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2540 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2541 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2542 | int UNUSED written = 0; |
| 2543 | IADDR UNUSED pc = abuf->addr; |
| 2544 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2545 | |
| 2546 | { |
| 2547 | { |
| 2548 | SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2549 | CPU (h_fr[((UINT) 32)]) = opval; |
| 2550 | TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); |
| 2551 | } |
| 2552 | { |
| 2553 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2554 | SET_H_GRC (FLD (f_rn), opval); |
| 2555 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2556 | } |
| 2557 | } |
| 2558 | |
| 2559 | #undef FLD |
| 2560 | } |
| 2561 | NEXT (vpc); |
| 2562 | |
| 2563 | CASE (sem, INSN_LDS_MACH_COMPACT) : /* lds $rn, mach */ |
| 2564 | { |
| 2565 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2566 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2567 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2568 | int UNUSED written = 0; |
| 2569 | IADDR UNUSED pc = abuf->addr; |
| 2570 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2571 | |
| 2572 | { |
| 2573 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 2574 | SET_H_MACH (opval); |
| 2575 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 2576 | } |
| 2577 | |
| 2578 | #undef FLD |
| 2579 | } |
| 2580 | NEXT (vpc); |
| 2581 | |
| 2582 | CASE (sem, INSN_LDSL_MACH_COMPACT) : /* lds.l @${rn}+, mach */ |
| 2583 | { |
| 2584 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2585 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2586 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2587 | int UNUSED written = 0; |
| 2588 | IADDR UNUSED pc = abuf->addr; |
| 2589 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2590 | |
| 2591 | { |
| 2592 | { |
| 2593 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2594 | SET_H_MACH (opval); |
| 2595 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 2596 | } |
| 2597 | { |
| 2598 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2599 | SET_H_GRC (FLD (f_rn), opval); |
| 2600 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2601 | } |
| 2602 | } |
| 2603 | |
| 2604 | #undef FLD |
| 2605 | } |
| 2606 | NEXT (vpc); |
| 2607 | |
| 2608 | CASE (sem, INSN_LDS_MACL_COMPACT) : /* lds $rn, macl */ |
| 2609 | { |
| 2610 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2611 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2612 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2613 | int UNUSED written = 0; |
| 2614 | IADDR UNUSED pc = abuf->addr; |
| 2615 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2616 | |
| 2617 | { |
| 2618 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 2619 | SET_H_MACL (opval); |
| 2620 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 2621 | } |
| 2622 | |
| 2623 | #undef FLD |
| 2624 | } |
| 2625 | NEXT (vpc); |
| 2626 | |
| 2627 | CASE (sem, INSN_LDSL_MACL_COMPACT) : /* lds.l @${rn}+, macl */ |
| 2628 | { |
| 2629 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2630 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2631 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2632 | int UNUSED written = 0; |
| 2633 | IADDR UNUSED pc = abuf->addr; |
| 2634 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2635 | |
| 2636 | { |
| 2637 | { |
| 2638 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2639 | SET_H_MACL (opval); |
| 2640 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 2641 | } |
| 2642 | { |
| 2643 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2644 | SET_H_GRC (FLD (f_rn), opval); |
| 2645 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2646 | } |
| 2647 | } |
| 2648 | |
| 2649 | #undef FLD |
| 2650 | } |
| 2651 | NEXT (vpc); |
| 2652 | |
| 2653 | CASE (sem, INSN_LDS_PR_COMPACT) : /* lds $rn, pr */ |
| 2654 | { |
| 2655 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2656 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2657 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2658 | int UNUSED written = 0; |
| 2659 | IADDR UNUSED pc = abuf->addr; |
| 2660 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2661 | |
| 2662 | { |
| 2663 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 2664 | SET_H_PR (opval); |
| 2665 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); |
| 2666 | } |
| 2667 | |
| 2668 | #undef FLD |
| 2669 | } |
| 2670 | NEXT (vpc); |
| 2671 | |
| 2672 | CASE (sem, INSN_LDSL_PR_COMPACT) : /* lds.l @${rn}+, pr */ |
| 2673 | { |
| 2674 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2675 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2676 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 2677 | int UNUSED written = 0; |
| 2678 | IADDR UNUSED pc = abuf->addr; |
| 2679 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2680 | |
| 2681 | { |
| 2682 | { |
| 2683 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2684 | SET_H_PR (opval); |
| 2685 | TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); |
| 2686 | } |
| 2687 | { |
| 2688 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2689 | SET_H_GRC (FLD (f_rn), opval); |
| 2690 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2691 | } |
| 2692 | } |
| 2693 | |
| 2694 | #undef FLD |
| 2695 | } |
| 2696 | NEXT (vpc); |
| 2697 | |
| 2698 | CASE (sem, INSN_MACL_COMPACT) : /* mac.l @${rm}+, @${rn}+ */ |
| 2699 | { |
| 2700 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2701 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2702 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2703 | int UNUSED written = 0; |
| 2704 | IADDR UNUSED pc = abuf->addr; |
| 2705 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2706 | |
| 2707 | { |
| 2708 | DI tmp_tmpry; |
| 2709 | DI tmp_mac; |
| 2710 | DI tmp_result; |
| 2711 | SI tmp_x; |
| 2712 | SI tmp_y; |
| 2713 | tmp_x = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2714 | { |
| 2715 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2716 | SET_H_GRC (FLD (f_rn), opval); |
| 2717 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2718 | } |
| 2719 | if (EQSI (FLD (f_rn), FLD (f_rm))) { |
| 2720 | { |
| 2721 | { |
| 2722 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 2723 | SET_H_GRC (FLD (f_rn), opval); |
| 2724 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2725 | } |
| 2726 | { |
| 2727 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); |
| 2728 | SET_H_GRC (FLD (f_rm), opval); |
| 2729 | written |= (1 << 11); |
| 2730 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2731 | } |
| 2732 | } |
| 2733 | } |
| 2734 | tmp_y = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 2735 | { |
| 2736 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); |
| 2737 | SET_H_GRC (FLD (f_rm), opval); |
| 2738 | written |= (1 << 11); |
| 2739 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2740 | } |
| 2741 | tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y)); |
| 2742 | tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ())); |
| 2743 | tmp_result = ADDDI (tmp_mac, tmp_tmpry); |
| 2744 | { |
| 2745 | if (GET_H_SBIT ()) { |
| 2746 | { |
| 2747 | SI tmp_min; |
| 2748 | SI tmp_max; |
| 2749 | tmp_max = SRLDI (INVDI (0), 16); |
| 2750 | tmp_min = SRLDI (INVDI (0), 15); |
| 2751 | if (GTDI (tmp_result, tmp_max)) { |
| 2752 | tmp_result = tmp_max; |
| 2753 | } else { |
| 2754 | if (LTDI (tmp_result, tmp_min)) { |
| 2755 | tmp_result = tmp_min; |
| 2756 | } |
| 2757 | } |
| 2758 | } |
| 2759 | } |
| 2760 | { |
| 2761 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 2762 | SET_H_MACH (opval); |
| 2763 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 2764 | } |
| 2765 | { |
| 2766 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 2767 | SET_H_MACL (opval); |
| 2768 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 2769 | } |
| 2770 | } |
| 2771 | } |
| 2772 | |
| 2773 | abuf->written = written; |
| 2774 | #undef FLD |
| 2775 | } |
| 2776 | NEXT (vpc); |
| 2777 | |
| 2778 | CASE (sem, INSN_MACW_COMPACT) : /* mac.w @${rm}+, @${rn}+ */ |
| 2779 | { |
| 2780 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2781 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2782 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2783 | int UNUSED written = 0; |
| 2784 | IADDR UNUSED pc = abuf->addr; |
| 2785 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2786 | |
| 2787 | { |
| 2788 | SI tmp_tmpry; |
| 2789 | DI tmp_mac; |
| 2790 | DI tmp_result; |
| 2791 | HI tmp_x; |
| 2792 | HI tmp_y; |
| 2793 | tmp_x = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 2794 | { |
| 2795 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); |
| 2796 | SET_H_GRC (FLD (f_rn), opval); |
| 2797 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2798 | } |
| 2799 | if (EQSI (FLD (f_rn), FLD (f_rm))) { |
| 2800 | { |
| 2801 | { |
| 2802 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); |
| 2803 | SET_H_GRC (FLD (f_rn), opval); |
| 2804 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2805 | } |
| 2806 | { |
| 2807 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); |
| 2808 | SET_H_GRC (FLD (f_rm), opval); |
| 2809 | written |= (1 << 11); |
| 2810 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2811 | } |
| 2812 | } |
| 2813 | } |
| 2814 | tmp_y = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 2815 | { |
| 2816 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); |
| 2817 | SET_H_GRC (FLD (f_rm), opval); |
| 2818 | written |= (1 << 11); |
| 2819 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2820 | } |
| 2821 | tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y)); |
| 2822 | if (GET_H_SBIT ()) { |
| 2823 | { |
| 2824 | if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { |
| 2825 | { |
| 2826 | SI opval = 1; |
| 2827 | SET_H_MACH (opval); |
| 2828 | written |= (1 << 9); |
| 2829 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 2830 | } |
| 2831 | } |
| 2832 | { |
| 2833 | SI opval = ADDSI (tmp_tmpry, GET_H_MACL ()); |
| 2834 | SET_H_MACL (opval); |
| 2835 | written |= (1 << 10); |
| 2836 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 2837 | } |
| 2838 | } |
| 2839 | } else { |
| 2840 | { |
| 2841 | tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ())); |
| 2842 | tmp_result = ADDDI (tmp_mac, EXTSIDI (tmp_tmpry)); |
| 2843 | { |
| 2844 | SI opval = SUBWORDDISI (tmp_result, 0); |
| 2845 | SET_H_MACH (opval); |
| 2846 | written |= (1 << 9); |
| 2847 | TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval); |
| 2848 | } |
| 2849 | { |
| 2850 | SI opval = SUBWORDDISI (tmp_result, 1); |
| 2851 | SET_H_MACL (opval); |
| 2852 | written |= (1 << 10); |
| 2853 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 2854 | } |
| 2855 | } |
| 2856 | } |
| 2857 | } |
| 2858 | |
| 2859 | abuf->written = written; |
| 2860 | #undef FLD |
| 2861 | } |
| 2862 | NEXT (vpc); |
| 2863 | |
| 2864 | CASE (sem, INSN_MOV_COMPACT) : /* mov $rm64, $rn64 */ |
| 2865 | { |
| 2866 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2867 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2868 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2869 | int UNUSED written = 0; |
| 2870 | IADDR UNUSED pc = abuf->addr; |
| 2871 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2872 | |
| 2873 | { |
| 2874 | DI opval = GET_H_GR (FLD (f_rm)); |
| 2875 | SET_H_GR (FLD (f_rn), opval); |
| 2876 | TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); |
| 2877 | } |
| 2878 | |
| 2879 | #undef FLD |
| 2880 | } |
| 2881 | NEXT (vpc); |
| 2882 | |
| 2883 | CASE (sem, INSN_MOVI_COMPACT) : /* mov #$imm8, $rn */ |
| 2884 | { |
| 2885 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2886 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2887 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 2888 | int UNUSED written = 0; |
| 2889 | IADDR UNUSED pc = abuf->addr; |
| 2890 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2891 | |
| 2892 | { |
| 2893 | SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255)); |
| 2894 | SET_H_GRC (FLD (f_rn), opval); |
| 2895 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2896 | } |
| 2897 | |
| 2898 | #undef FLD |
| 2899 | } |
| 2900 | NEXT (vpc); |
| 2901 | |
| 2902 | CASE (sem, INSN_MOVI20_COMPACT) : /* movi20 #$imm20, $rn */ |
| 2903 | { |
| 2904 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2905 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2906 | #define FLD(f) abuf->fields.sfmt_movi20_compact.f |
| 2907 | int UNUSED written = 0; |
| 2908 | IADDR UNUSED pc = abuf->addr; |
| 2909 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 2910 | |
| 2911 | { |
| 2912 | SI opval = FLD (f_imm20); |
| 2913 | SET_H_GRC (FLD (f_rn), opval); |
| 2914 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2915 | } |
| 2916 | |
| 2917 | #undef FLD |
| 2918 | } |
| 2919 | NEXT (vpc); |
| 2920 | |
| 2921 | CASE (sem, INSN_MOVB1_COMPACT) : /* mov.b $rm, @$rn */ |
| 2922 | { |
| 2923 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2924 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2925 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2926 | int UNUSED written = 0; |
| 2927 | IADDR UNUSED pc = abuf->addr; |
| 2928 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2929 | |
| 2930 | { |
| 2931 | UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3); |
| 2932 | SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 2933 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 2934 | } |
| 2935 | |
| 2936 | #undef FLD |
| 2937 | } |
| 2938 | NEXT (vpc); |
| 2939 | |
| 2940 | CASE (sem, INSN_MOVB2_COMPACT) : /* mov.b $rm, @-$rn */ |
| 2941 | { |
| 2942 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2943 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2944 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2945 | int UNUSED written = 0; |
| 2946 | IADDR UNUSED pc = abuf->addr; |
| 2947 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2948 | |
| 2949 | { |
| 2950 | DI tmp_addr; |
| 2951 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 1); |
| 2952 | { |
| 2953 | UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3); |
| 2954 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); |
| 2955 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 2956 | } |
| 2957 | { |
| 2958 | SI opval = tmp_addr; |
| 2959 | SET_H_GRC (FLD (f_rn), opval); |
| 2960 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 2961 | } |
| 2962 | } |
| 2963 | |
| 2964 | #undef FLD |
| 2965 | } |
| 2966 | NEXT (vpc); |
| 2967 | |
| 2968 | CASE (sem, INSN_MOVB3_COMPACT) : /* mov.b $rm, @(r0,$rn) */ |
| 2969 | { |
| 2970 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2971 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2972 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 2973 | int UNUSED written = 0; |
| 2974 | IADDR UNUSED pc = abuf->addr; |
| 2975 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2976 | |
| 2977 | { |
| 2978 | UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3); |
| 2979 | SETMEMUQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); |
| 2980 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 2981 | } |
| 2982 | |
| 2983 | #undef FLD |
| 2984 | } |
| 2985 | NEXT (vpc); |
| 2986 | |
| 2987 | CASE (sem, INSN_MOVB4_COMPACT) : /* mov.b r0, @($imm8, gbr) */ |
| 2988 | { |
| 2989 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 2990 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 2991 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 2992 | int UNUSED written = 0; |
| 2993 | IADDR UNUSED pc = abuf->addr; |
| 2994 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 2995 | |
| 2996 | { |
| 2997 | DI tmp_addr; |
| 2998 | tmp_addr = ADDSI (GET_H_GBR (), FLD (f_imm8)); |
| 2999 | { |
| 3000 | UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3); |
| 3001 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); |
| 3002 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3003 | } |
| 3004 | } |
| 3005 | |
| 3006 | #undef FLD |
| 3007 | } |
| 3008 | NEXT (vpc); |
| 3009 | |
| 3010 | CASE (sem, INSN_MOVB5_COMPACT) : /* mov.b r0, @($imm4, $rm) */ |
| 3011 | { |
| 3012 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3013 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3014 | #define FLD(f) abuf->fields.sfmt_movb5_compact.f |
| 3015 | int UNUSED written = 0; |
| 3016 | IADDR UNUSED pc = abuf->addr; |
| 3017 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3018 | |
| 3019 | { |
| 3020 | DI tmp_addr; |
| 3021 | tmp_addr = ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4)); |
| 3022 | { |
| 3023 | UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3); |
| 3024 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); |
| 3025 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3026 | } |
| 3027 | } |
| 3028 | |
| 3029 | #undef FLD |
| 3030 | } |
| 3031 | NEXT (vpc); |
| 3032 | |
| 3033 | CASE (sem, INSN_MOVB6_COMPACT) : /* mov.b @$rm, $rn */ |
| 3034 | { |
| 3035 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3036 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3037 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3038 | int UNUSED written = 0; |
| 3039 | IADDR UNUSED pc = abuf->addr; |
| 3040 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3041 | |
| 3042 | { |
| 3043 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); |
| 3044 | SET_H_GRC (FLD (f_rn), opval); |
| 3045 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3046 | } |
| 3047 | |
| 3048 | #undef FLD |
| 3049 | } |
| 3050 | NEXT (vpc); |
| 3051 | |
| 3052 | CASE (sem, INSN_MOVB7_COMPACT) : /* mov.b @${rm}+, $rn */ |
| 3053 | { |
| 3054 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3055 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3056 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3057 | int UNUSED written = 0; |
| 3058 | IADDR UNUSED pc = abuf->addr; |
| 3059 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3060 | |
| 3061 | { |
| 3062 | QI tmp_data; |
| 3063 | tmp_data = GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 3064 | if (EQSI (FLD (f_rm), FLD (f_rn))) { |
| 3065 | { |
| 3066 | SI opval = EXTQISI (tmp_data); |
| 3067 | SET_H_GRC (FLD (f_rm), opval); |
| 3068 | written |= (1 << 4); |
| 3069 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3070 | } |
| 3071 | } else { |
| 3072 | { |
| 3073 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1); |
| 3074 | SET_H_GRC (FLD (f_rm), opval); |
| 3075 | written |= (1 << 4); |
| 3076 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3077 | } |
| 3078 | } |
| 3079 | { |
| 3080 | SI opval = EXTQISI (tmp_data); |
| 3081 | SET_H_GRC (FLD (f_rn), opval); |
| 3082 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3083 | } |
| 3084 | } |
| 3085 | |
| 3086 | abuf->written = written; |
| 3087 | #undef FLD |
| 3088 | } |
| 3089 | NEXT (vpc); |
| 3090 | |
| 3091 | CASE (sem, INSN_MOVB8_COMPACT) : /* mov.b @(r0, $rm), $rn */ |
| 3092 | { |
| 3093 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3094 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3095 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3096 | int UNUSED written = 0; |
| 3097 | IADDR UNUSED pc = abuf->addr; |
| 3098 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3099 | |
| 3100 | { |
| 3101 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); |
| 3102 | SET_H_GRC (FLD (f_rn), opval); |
| 3103 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3104 | } |
| 3105 | |
| 3106 | #undef FLD |
| 3107 | } |
| 3108 | NEXT (vpc); |
| 3109 | |
| 3110 | CASE (sem, INSN_MOVB9_COMPACT) : /* mov.b @($imm8, gbr), r0 */ |
| 3111 | { |
| 3112 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3113 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3114 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 3115 | int UNUSED written = 0; |
| 3116 | IADDR UNUSED pc = abuf->addr; |
| 3117 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3118 | |
| 3119 | { |
| 3120 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8)))); |
| 3121 | SET_H_GRC (((UINT) 0), opval); |
| 3122 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3123 | } |
| 3124 | |
| 3125 | #undef FLD |
| 3126 | } |
| 3127 | NEXT (vpc); |
| 3128 | |
| 3129 | CASE (sem, INSN_MOVB10_COMPACT) : /* mov.b @($imm4, $rm), r0 */ |
| 3130 | { |
| 3131 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3132 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3133 | #define FLD(f) abuf->fields.sfmt_movb5_compact.f |
| 3134 | int UNUSED written = 0; |
| 3135 | IADDR UNUSED pc = abuf->addr; |
| 3136 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3137 | |
| 3138 | { |
| 3139 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4)))); |
| 3140 | SET_H_GRC (((UINT) 0), opval); |
| 3141 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3142 | } |
| 3143 | |
| 3144 | #undef FLD |
| 3145 | } |
| 3146 | NEXT (vpc); |
| 3147 | |
| 3148 | CASE (sem, INSN_MOVL1_COMPACT) : /* mov.l $rm, @$rn */ |
| 3149 | { |
| 3150 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3151 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3152 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3153 | int UNUSED written = 0; |
| 3154 | IADDR UNUSED pc = abuf->addr; |
| 3155 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3156 | |
| 3157 | { |
| 3158 | SI opval = GET_H_GRC (FLD (f_rm)); |
| 3159 | SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 3160 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3161 | } |
| 3162 | |
| 3163 | #undef FLD |
| 3164 | } |
| 3165 | NEXT (vpc); |
| 3166 | |
| 3167 | CASE (sem, INSN_MOVL2_COMPACT) : /* mov.l $rm, @-$rn */ |
| 3168 | { |
| 3169 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3170 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3171 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3172 | int UNUSED written = 0; |
| 3173 | IADDR UNUSED pc = abuf->addr; |
| 3174 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3175 | |
| 3176 | { |
| 3177 | SI tmp_addr; |
| 3178 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 3179 | { |
| 3180 | SI opval = GET_H_GRC (FLD (f_rm)); |
| 3181 | SETMEMSI (current_cpu, pc, tmp_addr, opval); |
| 3182 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3183 | } |
| 3184 | { |
| 3185 | SI opval = tmp_addr; |
| 3186 | SET_H_GRC (FLD (f_rn), opval); |
| 3187 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3188 | } |
| 3189 | } |
| 3190 | |
| 3191 | #undef FLD |
| 3192 | } |
| 3193 | NEXT (vpc); |
| 3194 | |
| 3195 | CASE (sem, INSN_MOVL3_COMPACT) : /* mov.l $rm, @(r0, $rn) */ |
| 3196 | { |
| 3197 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3198 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3199 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3200 | int UNUSED written = 0; |
| 3201 | IADDR UNUSED pc = abuf->addr; |
| 3202 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3203 | |
| 3204 | { |
| 3205 | SI opval = GET_H_GRC (FLD (f_rm)); |
| 3206 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); |
| 3207 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3208 | } |
| 3209 | |
| 3210 | #undef FLD |
| 3211 | } |
| 3212 | NEXT (vpc); |
| 3213 | |
| 3214 | CASE (sem, INSN_MOVL4_COMPACT) : /* mov.l r0, @($imm8x4, gbr) */ |
| 3215 | { |
| 3216 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3217 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3218 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f |
| 3219 | int UNUSED written = 0; |
| 3220 | IADDR UNUSED pc = abuf->addr; |
| 3221 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3222 | |
| 3223 | { |
| 3224 | SI opval = GET_H_GRC (((UINT) 0)); |
| 3225 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)), opval); |
| 3226 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3227 | } |
| 3228 | |
| 3229 | #undef FLD |
| 3230 | } |
| 3231 | NEXT (vpc); |
| 3232 | |
| 3233 | CASE (sem, INSN_MOVL5_COMPACT) : /* mov.l $rm, @($imm4x4, $rn) */ |
| 3234 | { |
| 3235 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3236 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3237 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f |
| 3238 | int UNUSED written = 0; |
| 3239 | IADDR UNUSED pc = abuf->addr; |
| 3240 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3241 | |
| 3242 | { |
| 3243 | SI opval = GET_H_GRC (FLD (f_rm)); |
| 3244 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x4)), opval); |
| 3245 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3246 | } |
| 3247 | |
| 3248 | #undef FLD |
| 3249 | } |
| 3250 | NEXT (vpc); |
| 3251 | |
| 3252 | CASE (sem, INSN_MOVL6_COMPACT) : /* mov.l @$rm, $rn */ |
| 3253 | { |
| 3254 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3255 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3256 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3257 | int UNUSED written = 0; |
| 3258 | IADDR UNUSED pc = abuf->addr; |
| 3259 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3260 | |
| 3261 | { |
| 3262 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 3263 | SET_H_GRC (FLD (f_rn), opval); |
| 3264 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3265 | } |
| 3266 | |
| 3267 | #undef FLD |
| 3268 | } |
| 3269 | NEXT (vpc); |
| 3270 | |
| 3271 | CASE (sem, INSN_MOVL7_COMPACT) : /* mov.l @${rm}+, $rn */ |
| 3272 | { |
| 3273 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3274 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3275 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3276 | int UNUSED written = 0; |
| 3277 | IADDR UNUSED pc = abuf->addr; |
| 3278 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3279 | |
| 3280 | { |
| 3281 | { |
| 3282 | SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 3283 | SET_H_GRC (FLD (f_rn), opval); |
| 3284 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3285 | } |
| 3286 | if (EQSI (FLD (f_rm), FLD (f_rn))) { |
| 3287 | { |
| 3288 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 3289 | SET_H_GRC (FLD (f_rm), opval); |
| 3290 | written |= (1 << 5); |
| 3291 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3292 | } |
| 3293 | } else { |
| 3294 | { |
| 3295 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); |
| 3296 | SET_H_GRC (FLD (f_rm), opval); |
| 3297 | written |= (1 << 5); |
| 3298 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3299 | } |
| 3300 | } |
| 3301 | } |
| 3302 | |
| 3303 | abuf->written = written; |
| 3304 | #undef FLD |
| 3305 | } |
| 3306 | NEXT (vpc); |
| 3307 | |
| 3308 | CASE (sem, INSN_MOVL8_COMPACT) : /* mov.l @(r0, $rm), $rn */ |
| 3309 | { |
| 3310 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3311 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3312 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3313 | int UNUSED written = 0; |
| 3314 | IADDR UNUSED pc = abuf->addr; |
| 3315 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3316 | |
| 3317 | { |
| 3318 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); |
| 3319 | SET_H_GRC (FLD (f_rn), opval); |
| 3320 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3321 | } |
| 3322 | |
| 3323 | #undef FLD |
| 3324 | } |
| 3325 | NEXT (vpc); |
| 3326 | |
| 3327 | CASE (sem, INSN_MOVL9_COMPACT) : /* mov.l @($imm8x4, gbr), r0 */ |
| 3328 | { |
| 3329 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3330 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3331 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f |
| 3332 | int UNUSED written = 0; |
| 3333 | IADDR UNUSED pc = abuf->addr; |
| 3334 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3335 | |
| 3336 | { |
| 3337 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4))); |
| 3338 | SET_H_GRC (((UINT) 0), opval); |
| 3339 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3340 | } |
| 3341 | |
| 3342 | #undef FLD |
| 3343 | } |
| 3344 | NEXT (vpc); |
| 3345 | |
| 3346 | CASE (sem, INSN_MOVL10_COMPACT) : /* mov.l @($imm8x4, pc), $rn */ |
| 3347 | { |
| 3348 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3349 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3350 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f |
| 3351 | int UNUSED written = 0; |
| 3352 | IADDR UNUSED pc = abuf->addr; |
| 3353 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3354 | |
| 3355 | { |
| 3356 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3)))); |
| 3357 | SET_H_GRC (FLD (f_rn), opval); |
| 3358 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3359 | } |
| 3360 | |
| 3361 | #undef FLD |
| 3362 | } |
| 3363 | NEXT (vpc); |
| 3364 | |
| 3365 | CASE (sem, INSN_MOVL11_COMPACT) : /* mov.l @($imm4x4, $rm), $rn */ |
| 3366 | { |
| 3367 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3368 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3369 | #define FLD(f) abuf->fields.sfmt_movl5_compact.f |
| 3370 | int UNUSED written = 0; |
| 3371 | IADDR UNUSED pc = abuf->addr; |
| 3372 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3373 | |
| 3374 | { |
| 3375 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4))); |
| 3376 | SET_H_GRC (FLD (f_rn), opval); |
| 3377 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3378 | } |
| 3379 | |
| 3380 | #undef FLD |
| 3381 | } |
| 3382 | NEXT (vpc); |
| 3383 | |
| 3384 | CASE (sem, INSN_MOVL12_COMPACT) : /* mov.l @($imm12x4, $rm), $rn */ |
| 3385 | { |
| 3386 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3387 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3388 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3389 | int UNUSED written = 0; |
| 3390 | IADDR UNUSED pc = abuf->addr; |
| 3391 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3392 | |
| 3393 | { |
| 3394 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm12x4))); |
| 3395 | SET_H_GRC (FLD (f_rn), opval); |
| 3396 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3397 | } |
| 3398 | |
| 3399 | #undef FLD |
| 3400 | } |
| 3401 | NEXT (vpc); |
| 3402 | |
| 3403 | CASE (sem, INSN_MOVL13_COMPACT) : /* mov.l $rm, @($imm12x4, $rn) */ |
| 3404 | { |
| 3405 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3406 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3407 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3408 | int UNUSED written = 0; |
| 3409 | IADDR UNUSED pc = abuf->addr; |
| 3410 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); |
| 3411 | |
| 3412 | { |
| 3413 | SI opval = GET_H_GRC (FLD (f_rm)); |
| 3414 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm12x4)), opval); |
| 3415 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3416 | } |
| 3417 | |
| 3418 | #undef FLD |
| 3419 | } |
| 3420 | NEXT (vpc); |
| 3421 | |
| 3422 | CASE (sem, INSN_MOVW1_COMPACT) : /* mov.w $rm, @$rn */ |
| 3423 | { |
| 3424 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3425 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3426 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3427 | int UNUSED written = 0; |
| 3428 | IADDR UNUSED pc = abuf->addr; |
| 3429 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3430 | |
| 3431 | { |
| 3432 | HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1); |
| 3433 | SETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 3434 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3435 | } |
| 3436 | |
| 3437 | #undef FLD |
| 3438 | } |
| 3439 | NEXT (vpc); |
| 3440 | |
| 3441 | CASE (sem, INSN_MOVW2_COMPACT) : /* mov.w $rm, @-$rn */ |
| 3442 | { |
| 3443 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3444 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3445 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3446 | int UNUSED written = 0; |
| 3447 | IADDR UNUSED pc = abuf->addr; |
| 3448 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3449 | |
| 3450 | { |
| 3451 | DI tmp_addr; |
| 3452 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 2); |
| 3453 | { |
| 3454 | HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1); |
| 3455 | SETMEMHI (current_cpu, pc, tmp_addr, opval); |
| 3456 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3457 | } |
| 3458 | { |
| 3459 | SI opval = tmp_addr; |
| 3460 | SET_H_GRC (FLD (f_rn), opval); |
| 3461 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3462 | } |
| 3463 | } |
| 3464 | |
| 3465 | #undef FLD |
| 3466 | } |
| 3467 | NEXT (vpc); |
| 3468 | |
| 3469 | CASE (sem, INSN_MOVW3_COMPACT) : /* mov.w $rm, @(r0, $rn) */ |
| 3470 | { |
| 3471 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3472 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3473 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3474 | int UNUSED written = 0; |
| 3475 | IADDR UNUSED pc = abuf->addr; |
| 3476 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3477 | |
| 3478 | { |
| 3479 | HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1); |
| 3480 | SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); |
| 3481 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3482 | } |
| 3483 | |
| 3484 | #undef FLD |
| 3485 | } |
| 3486 | NEXT (vpc); |
| 3487 | |
| 3488 | CASE (sem, INSN_MOVW4_COMPACT) : /* mov.w r0, @($imm8x2, gbr) */ |
| 3489 | { |
| 3490 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3491 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3492 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3493 | int UNUSED written = 0; |
| 3494 | IADDR UNUSED pc = abuf->addr; |
| 3495 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3496 | |
| 3497 | { |
| 3498 | HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1); |
| 3499 | SETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)), opval); |
| 3500 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3501 | } |
| 3502 | |
| 3503 | #undef FLD |
| 3504 | } |
| 3505 | NEXT (vpc); |
| 3506 | |
| 3507 | CASE (sem, INSN_MOVW5_COMPACT) : /* mov.w r0, @($imm4x2, $rm) */ |
| 3508 | { |
| 3509 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3510 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3511 | #define FLD(f) abuf->fields.sfmt_movw5_compact.f |
| 3512 | int UNUSED written = 0; |
| 3513 | IADDR UNUSED pc = abuf->addr; |
| 3514 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3515 | |
| 3516 | { |
| 3517 | HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1); |
| 3518 | SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2)), opval); |
| 3519 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3520 | } |
| 3521 | |
| 3522 | #undef FLD |
| 3523 | } |
| 3524 | NEXT (vpc); |
| 3525 | |
| 3526 | CASE (sem, INSN_MOVW6_COMPACT) : /* mov.w @$rm, $rn */ |
| 3527 | { |
| 3528 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3529 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3530 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3531 | int UNUSED written = 0; |
| 3532 | IADDR UNUSED pc = abuf->addr; |
| 3533 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3534 | |
| 3535 | { |
| 3536 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); |
| 3537 | SET_H_GRC (FLD (f_rn), opval); |
| 3538 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3539 | } |
| 3540 | |
| 3541 | #undef FLD |
| 3542 | } |
| 3543 | NEXT (vpc); |
| 3544 | |
| 3545 | CASE (sem, INSN_MOVW7_COMPACT) : /* mov.w @${rm}+, $rn */ |
| 3546 | { |
| 3547 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3548 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3549 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3550 | int UNUSED written = 0; |
| 3551 | IADDR UNUSED pc = abuf->addr; |
| 3552 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3553 | |
| 3554 | { |
| 3555 | HI tmp_data; |
| 3556 | tmp_data = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); |
| 3557 | if (EQSI (FLD (f_rm), FLD (f_rn))) { |
| 3558 | { |
| 3559 | SI opval = EXTHISI (tmp_data); |
| 3560 | SET_H_GRC (FLD (f_rm), opval); |
| 3561 | written |= (1 << 4); |
| 3562 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3563 | } |
| 3564 | } else { |
| 3565 | { |
| 3566 | SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); |
| 3567 | SET_H_GRC (FLD (f_rm), opval); |
| 3568 | written |= (1 << 4); |
| 3569 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3570 | } |
| 3571 | } |
| 3572 | { |
| 3573 | SI opval = EXTHISI (tmp_data); |
| 3574 | SET_H_GRC (FLD (f_rn), opval); |
| 3575 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3576 | } |
| 3577 | } |
| 3578 | |
| 3579 | abuf->written = written; |
| 3580 | #undef FLD |
| 3581 | } |
| 3582 | NEXT (vpc); |
| 3583 | |
| 3584 | CASE (sem, INSN_MOVW8_COMPACT) : /* mov.w @(r0, $rm), $rn */ |
| 3585 | { |
| 3586 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3587 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3588 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3589 | int UNUSED written = 0; |
| 3590 | IADDR UNUSED pc = abuf->addr; |
| 3591 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3592 | |
| 3593 | { |
| 3594 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); |
| 3595 | SET_H_GRC (FLD (f_rn), opval); |
| 3596 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3597 | } |
| 3598 | |
| 3599 | #undef FLD |
| 3600 | } |
| 3601 | NEXT (vpc); |
| 3602 | |
| 3603 | CASE (sem, INSN_MOVW9_COMPACT) : /* mov.w @($imm8x2, gbr), r0 */ |
| 3604 | { |
| 3605 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3606 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3607 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3608 | int UNUSED written = 0; |
| 3609 | IADDR UNUSED pc = abuf->addr; |
| 3610 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3611 | |
| 3612 | { |
| 3613 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)))); |
| 3614 | SET_H_GRC (((UINT) 0), opval); |
| 3615 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3616 | } |
| 3617 | |
| 3618 | #undef FLD |
| 3619 | } |
| 3620 | NEXT (vpc); |
| 3621 | |
| 3622 | CASE (sem, INSN_MOVW10_COMPACT) : /* mov.w @($imm8x2, pc), $rn */ |
| 3623 | { |
| 3624 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3625 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3626 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3627 | int UNUSED written = 0; |
| 3628 | IADDR UNUSED pc = abuf->addr; |
| 3629 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3630 | |
| 3631 | { |
| 3632 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2)))); |
| 3633 | SET_H_GRC (FLD (f_rn), opval); |
| 3634 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3635 | } |
| 3636 | |
| 3637 | #undef FLD |
| 3638 | } |
| 3639 | NEXT (vpc); |
| 3640 | |
| 3641 | CASE (sem, INSN_MOVW11_COMPACT) : /* mov.w @($imm4x2, $rm), r0 */ |
| 3642 | { |
| 3643 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3644 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3645 | #define FLD(f) abuf->fields.sfmt_movw5_compact.f |
| 3646 | int UNUSED written = 0; |
| 3647 | IADDR UNUSED pc = abuf->addr; |
| 3648 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3649 | |
| 3650 | { |
| 3651 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2)))); |
| 3652 | SET_H_GRC (((UINT) 0), opval); |
| 3653 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3654 | } |
| 3655 | |
| 3656 | #undef FLD |
| 3657 | } |
| 3658 | NEXT (vpc); |
| 3659 | |
| 3660 | CASE (sem, INSN_MOVA_COMPACT) : /* mova @($imm8x4, pc), r0 */ |
| 3661 | { |
| 3662 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3663 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3664 | #define FLD(f) abuf->fields.sfmt_movl10_compact.f |
| 3665 | int UNUSED written = 0; |
| 3666 | IADDR UNUSED pc = abuf->addr; |
| 3667 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3668 | |
| 3669 | { |
| 3670 | SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4)); |
| 3671 | SET_H_GRC (((UINT) 0), opval); |
| 3672 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3673 | } |
| 3674 | |
| 3675 | #undef FLD |
| 3676 | } |
| 3677 | NEXT (vpc); |
| 3678 | |
| 3679 | CASE (sem, INSN_MOVCAL_COMPACT) : /* movca.l r0, @$rn */ |
| 3680 | { |
| 3681 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3682 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3683 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3684 | int UNUSED written = 0; |
| 3685 | IADDR UNUSED pc = abuf->addr; |
| 3686 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3687 | |
| 3688 | { |
| 3689 | SI opval = GET_H_GRC (((UINT) 0)); |
| 3690 | SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 3691 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 3692 | } |
| 3693 | |
| 3694 | #undef FLD |
| 3695 | } |
| 3696 | NEXT (vpc); |
| 3697 | |
| 3698 | CASE (sem, INSN_MOVCOL_COMPACT) : /* movco.l r0, @$rn */ |
| 3699 | { |
| 3700 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3701 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3702 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3703 | int UNUSED written = 0; |
| 3704 | IADDR UNUSED pc = abuf->addr; |
| 3705 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3706 | |
| 3707 | { |
| 3708 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 3709 | SET_H_GRC (FLD (f_rn), opval); |
| 3710 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3711 | } |
| 3712 | |
| 3713 | #undef FLD |
| 3714 | } |
| 3715 | NEXT (vpc); |
| 3716 | |
| 3717 | CASE (sem, INSN_MOVT_COMPACT) : /* movt $rn */ |
| 3718 | { |
| 3719 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3720 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3721 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3722 | int UNUSED written = 0; |
| 3723 | IADDR UNUSED pc = abuf->addr; |
| 3724 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3725 | |
| 3726 | { |
| 3727 | SI opval = ZEXTBISI (GET_H_TBIT ()); |
| 3728 | SET_H_GRC (FLD (f_rn), opval); |
| 3729 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3730 | } |
| 3731 | |
| 3732 | #undef FLD |
| 3733 | } |
| 3734 | NEXT (vpc); |
| 3735 | |
| 3736 | CASE (sem, INSN_MOVUAL_COMPACT) : /* movua.l @$rn, r0 */ |
| 3737 | { |
| 3738 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3739 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3740 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3741 | int UNUSED written = 0; |
| 3742 | IADDR UNUSED pc = abuf->addr; |
| 3743 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3744 | |
| 3745 | { |
| 3746 | SI opval = sh64_movua (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 3747 | SET_H_GRC (((UINT) 0), opval); |
| 3748 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3749 | } |
| 3750 | |
| 3751 | #undef FLD |
| 3752 | } |
| 3753 | NEXT (vpc); |
| 3754 | |
| 3755 | CASE (sem, INSN_MOVUAL2_COMPACT) : /* movua.l @$rn+, r0 */ |
| 3756 | { |
| 3757 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3758 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3759 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3760 | int UNUSED written = 0; |
| 3761 | IADDR UNUSED pc = abuf->addr; |
| 3762 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3763 | |
| 3764 | { |
| 3765 | { |
| 3766 | SI opval = sh64_movua (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 3767 | SET_H_GRC (((UINT) 0), opval); |
| 3768 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3769 | } |
| 3770 | { |
| 3771 | SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); |
| 3772 | SET_H_GRC (FLD (f_rn), opval); |
| 3773 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3774 | } |
| 3775 | } |
| 3776 | |
| 3777 | #undef FLD |
| 3778 | } |
| 3779 | NEXT (vpc); |
| 3780 | |
| 3781 | CASE (sem, INSN_MULL_COMPACT) : /* mul.l $rm, $rn */ |
| 3782 | { |
| 3783 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3784 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3785 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3786 | int UNUSED written = 0; |
| 3787 | IADDR UNUSED pc = abuf->addr; |
| 3788 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3789 | |
| 3790 | { |
| 3791 | SI opval = MULSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); |
| 3792 | SET_H_MACL (opval); |
| 3793 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 3794 | } |
| 3795 | |
| 3796 | #undef FLD |
| 3797 | } |
| 3798 | NEXT (vpc); |
| 3799 | |
| 3800 | CASE (sem, INSN_MULSW_COMPACT) : /* muls.w $rm, $rn */ |
| 3801 | { |
| 3802 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3803 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3804 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3805 | int UNUSED written = 0; |
| 3806 | IADDR UNUSED pc = abuf->addr; |
| 3807 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3808 | |
| 3809 | { |
| 3810 | SI opval = MULSI (EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1))); |
| 3811 | SET_H_MACL (opval); |
| 3812 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 3813 | } |
| 3814 | |
| 3815 | #undef FLD |
| 3816 | } |
| 3817 | NEXT (vpc); |
| 3818 | |
| 3819 | CASE (sem, INSN_MULUW_COMPACT) : /* mulu.w $rm, $rn */ |
| 3820 | { |
| 3821 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3822 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3823 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3824 | int UNUSED written = 0; |
| 3825 | IADDR UNUSED pc = abuf->addr; |
| 3826 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3827 | |
| 3828 | { |
| 3829 | SI opval = MULSI (ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1))); |
| 3830 | SET_H_MACL (opval); |
| 3831 | TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval); |
| 3832 | } |
| 3833 | |
| 3834 | #undef FLD |
| 3835 | } |
| 3836 | NEXT (vpc); |
| 3837 | |
| 3838 | CASE (sem, INSN_NEG_COMPACT) : /* neg $rm, $rn */ |
| 3839 | { |
| 3840 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3841 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3842 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3843 | int UNUSED written = 0; |
| 3844 | IADDR UNUSED pc = abuf->addr; |
| 3845 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3846 | |
| 3847 | { |
| 3848 | SI opval = NEGSI (GET_H_GRC (FLD (f_rm))); |
| 3849 | SET_H_GRC (FLD (f_rn), opval); |
| 3850 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3851 | } |
| 3852 | |
| 3853 | #undef FLD |
| 3854 | } |
| 3855 | NEXT (vpc); |
| 3856 | |
| 3857 | CASE (sem, INSN_NEGC_COMPACT) : /* negc $rm, $rn */ |
| 3858 | { |
| 3859 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3860 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3861 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3862 | int UNUSED written = 0; |
| 3863 | IADDR UNUSED pc = abuf->addr; |
| 3864 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3865 | |
| 3866 | { |
| 3867 | BI tmp_flag; |
| 3868 | tmp_flag = SUBCFSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); |
| 3869 | { |
| 3870 | SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); |
| 3871 | SET_H_GRC (FLD (f_rn), opval); |
| 3872 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3873 | } |
| 3874 | { |
| 3875 | BI opval = tmp_flag; |
| 3876 | SET_H_TBIT (opval); |
| 3877 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 3878 | } |
| 3879 | } |
| 3880 | |
| 3881 | #undef FLD |
| 3882 | } |
| 3883 | NEXT (vpc); |
| 3884 | |
| 3885 | CASE (sem, INSN_NOP_COMPACT) : /* nop */ |
| 3886 | { |
| 3887 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3888 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3889 | #define FLD(f) abuf->fields.fmt_empty.f |
| 3890 | int UNUSED written = 0; |
| 3891 | IADDR UNUSED pc = abuf->addr; |
| 3892 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3893 | |
| 3894 | ((void) 0); /*nop*/ |
| 3895 | |
| 3896 | #undef FLD |
| 3897 | } |
| 3898 | NEXT (vpc); |
| 3899 | |
| 3900 | CASE (sem, INSN_NOT_COMPACT) : /* not $rm64, $rn64 */ |
| 3901 | { |
| 3902 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3903 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3904 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3905 | int UNUSED written = 0; |
| 3906 | IADDR UNUSED pc = abuf->addr; |
| 3907 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3908 | |
| 3909 | { |
| 3910 | DI opval = INVDI (GET_H_GR (FLD (f_rm))); |
| 3911 | SET_H_GR (FLD (f_rn), opval); |
| 3912 | TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); |
| 3913 | } |
| 3914 | |
| 3915 | #undef FLD |
| 3916 | } |
| 3917 | NEXT (vpc); |
| 3918 | |
| 3919 | CASE (sem, INSN_OCBI_COMPACT) : /* ocbi @$rn */ |
| 3920 | { |
| 3921 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3922 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3923 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3924 | int UNUSED written = 0; |
| 3925 | IADDR UNUSED pc = abuf->addr; |
| 3926 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3927 | |
| 3928 | { |
| 3929 | { |
| 3930 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 3931 | SET_H_GRC (FLD (f_rn), opval); |
| 3932 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3933 | } |
| 3934 | ((void) 0); /*nop*/ |
| 3935 | } |
| 3936 | |
| 3937 | #undef FLD |
| 3938 | } |
| 3939 | NEXT (vpc); |
| 3940 | |
| 3941 | CASE (sem, INSN_OCBP_COMPACT) : /* ocbp @$rn */ |
| 3942 | { |
| 3943 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3944 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3945 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3946 | int UNUSED written = 0; |
| 3947 | IADDR UNUSED pc = abuf->addr; |
| 3948 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3949 | |
| 3950 | { |
| 3951 | { |
| 3952 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 3953 | SET_H_GRC (FLD (f_rn), opval); |
| 3954 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3955 | } |
| 3956 | ((void) 0); /*nop*/ |
| 3957 | } |
| 3958 | |
| 3959 | #undef FLD |
| 3960 | } |
| 3961 | NEXT (vpc); |
| 3962 | |
| 3963 | CASE (sem, INSN_OCBWB_COMPACT) : /* ocbwb @$rn */ |
| 3964 | { |
| 3965 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3966 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3967 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 3968 | int UNUSED written = 0; |
| 3969 | IADDR UNUSED pc = abuf->addr; |
| 3970 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3971 | |
| 3972 | { |
| 3973 | { |
| 3974 | SI opval = GET_H_GRC (FLD (f_rn)); |
| 3975 | SET_H_GRC (FLD (f_rn), opval); |
| 3976 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 3977 | } |
| 3978 | ((void) 0); /*nop*/ |
| 3979 | } |
| 3980 | |
| 3981 | #undef FLD |
| 3982 | } |
| 3983 | NEXT (vpc); |
| 3984 | |
| 3985 | CASE (sem, INSN_OR_COMPACT) : /* or $rm64, $rn64 */ |
| 3986 | { |
| 3987 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 3988 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 3989 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 3990 | int UNUSED written = 0; |
| 3991 | IADDR UNUSED pc = abuf->addr; |
| 3992 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 3993 | |
| 3994 | { |
| 3995 | DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); |
| 3996 | SET_H_GR (FLD (f_rn), opval); |
| 3997 | TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); |
| 3998 | } |
| 3999 | |
| 4000 | #undef FLD |
| 4001 | } |
| 4002 | NEXT (vpc); |
| 4003 | |
| 4004 | CASE (sem, INSN_ORI_COMPACT) : /* or #$uimm8, r0 */ |
| 4005 | { |
| 4006 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4007 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4008 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 4009 | int UNUSED written = 0; |
| 4010 | IADDR UNUSED pc = abuf->addr; |
| 4011 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4012 | |
| 4013 | { |
| 4014 | SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); |
| 4015 | SET_H_GRC (((UINT) 0), opval); |
| 4016 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4017 | } |
| 4018 | |
| 4019 | #undef FLD |
| 4020 | } |
| 4021 | NEXT (vpc); |
| 4022 | |
| 4023 | CASE (sem, INSN_ORB_COMPACT) : /* or.b #$imm8, @(r0, gbr) */ |
| 4024 | { |
| 4025 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4026 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4027 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 4028 | int UNUSED written = 0; |
| 4029 | IADDR UNUSED pc = abuf->addr; |
| 4030 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4031 | |
| 4032 | { |
| 4033 | DI tmp_addr; |
| 4034 | UQI tmp_data; |
| 4035 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); |
| 4036 | tmp_data = ORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)); |
| 4037 | { |
| 4038 | UQI opval = tmp_data; |
| 4039 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); |
| 4040 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 4041 | } |
| 4042 | } |
| 4043 | |
| 4044 | #undef FLD |
| 4045 | } |
| 4046 | NEXT (vpc); |
| 4047 | |
| 4048 | CASE (sem, INSN_PREF_COMPACT) : /* pref @$rn */ |
| 4049 | { |
| 4050 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4051 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4052 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4053 | int UNUSED written = 0; |
| 4054 | IADDR UNUSED pc = abuf->addr; |
| 4055 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4056 | |
| 4057 | sh64_pref (current_cpu, GET_H_GRC (FLD (f_rn))); |
| 4058 | |
| 4059 | #undef FLD |
| 4060 | } |
| 4061 | NEXT (vpc); |
| 4062 | |
| 4063 | CASE (sem, INSN_ROTCL_COMPACT) : /* rotcl $rn */ |
| 4064 | { |
| 4065 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4066 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4067 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4068 | int UNUSED written = 0; |
| 4069 | IADDR UNUSED pc = abuf->addr; |
| 4070 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4071 | |
| 4072 | { |
| 4073 | BI tmp_temp; |
| 4074 | tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31); |
| 4075 | { |
| 4076 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ()); |
| 4077 | SET_H_GRC (FLD (f_rn), opval); |
| 4078 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4079 | } |
| 4080 | { |
| 4081 | BI opval = ((tmp_temp) ? (1) : (0)); |
| 4082 | SET_H_TBIT (opval); |
| 4083 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4084 | } |
| 4085 | } |
| 4086 | |
| 4087 | #undef FLD |
| 4088 | } |
| 4089 | NEXT (vpc); |
| 4090 | |
| 4091 | CASE (sem, INSN_ROTCR_COMPACT) : /* rotcr $rn */ |
| 4092 | { |
| 4093 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4094 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4095 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4096 | int UNUSED written = 0; |
| 4097 | IADDR UNUSED pc = abuf->addr; |
| 4098 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4099 | |
| 4100 | { |
| 4101 | BI tmp_lsbit; |
| 4102 | SI tmp_temp; |
| 4103 | tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1)); |
| 4104 | tmp_temp = GET_H_TBIT (); |
| 4105 | { |
| 4106 | SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); |
| 4107 | SET_H_GRC (FLD (f_rn), opval); |
| 4108 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4109 | } |
| 4110 | { |
| 4111 | BI opval = ((tmp_lsbit) ? (1) : (0)); |
| 4112 | SET_H_TBIT (opval); |
| 4113 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4114 | } |
| 4115 | } |
| 4116 | |
| 4117 | #undef FLD |
| 4118 | } |
| 4119 | NEXT (vpc); |
| 4120 | |
| 4121 | CASE (sem, INSN_ROTL_COMPACT) : /* rotl $rn */ |
| 4122 | { |
| 4123 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4124 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4125 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4126 | int UNUSED written = 0; |
| 4127 | IADDR UNUSED pc = abuf->addr; |
| 4128 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4129 | |
| 4130 | { |
| 4131 | BI tmp_temp; |
| 4132 | tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31); |
| 4133 | { |
| 4134 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp); |
| 4135 | SET_H_GRC (FLD (f_rn), opval); |
| 4136 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4137 | } |
| 4138 | { |
| 4139 | BI opval = ((tmp_temp) ? (1) : (0)); |
| 4140 | SET_H_TBIT (opval); |
| 4141 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4142 | } |
| 4143 | } |
| 4144 | |
| 4145 | #undef FLD |
| 4146 | } |
| 4147 | NEXT (vpc); |
| 4148 | |
| 4149 | CASE (sem, INSN_ROTR_COMPACT) : /* rotr $rn */ |
| 4150 | { |
| 4151 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4152 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4153 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4154 | int UNUSED written = 0; |
| 4155 | IADDR UNUSED pc = abuf->addr; |
| 4156 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4157 | |
| 4158 | { |
| 4159 | BI tmp_lsbit; |
| 4160 | SI tmp_temp; |
| 4161 | tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1)); |
| 4162 | tmp_temp = tmp_lsbit; |
| 4163 | { |
| 4164 | SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); |
| 4165 | SET_H_GRC (FLD (f_rn), opval); |
| 4166 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4167 | } |
| 4168 | { |
| 4169 | BI opval = ((tmp_lsbit) ? (1) : (0)); |
| 4170 | SET_H_TBIT (opval); |
| 4171 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4172 | } |
| 4173 | } |
| 4174 | |
| 4175 | #undef FLD |
| 4176 | } |
| 4177 | NEXT (vpc); |
| 4178 | |
| 4179 | CASE (sem, INSN_RTS_COMPACT) : /* rts */ |
| 4180 | { |
| 4181 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4182 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4183 | #define FLD(f) abuf->fields.fmt_empty.f |
| 4184 | int UNUSED written = 0; |
| 4185 | IADDR UNUSED pc = abuf->addr; |
| 4186 | SEM_BRANCH_INIT |
| 4187 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4188 | |
| 4189 | { |
| 4190 | { |
| 4191 | UDI opval = ADDDI (pc, 2); |
| 4192 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 4193 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 4194 | } |
| 4195 | ((void) 0); /*nop*/ |
| 4196 | { |
| 4197 | { |
| 4198 | UDI opval = GET_H_PR (); |
| 4199 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); |
| 4200 | TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); |
| 4201 | } |
| 4202 | } |
| 4203 | ((void) 0); /*nop*/ |
| 4204 | } |
| 4205 | |
| 4206 | SEM_BRANCH_FINI (vpc); |
| 4207 | #undef FLD |
| 4208 | } |
| 4209 | NEXT (vpc); |
| 4210 | |
| 4211 | CASE (sem, INSN_SETS_COMPACT) : /* sets */ |
| 4212 | { |
| 4213 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4214 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4215 | #define FLD(f) abuf->fields.fmt_empty.f |
| 4216 | int UNUSED written = 0; |
| 4217 | IADDR UNUSED pc = abuf->addr; |
| 4218 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4219 | |
| 4220 | { |
| 4221 | BI opval = 1; |
| 4222 | SET_H_SBIT (opval); |
| 4223 | TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval); |
| 4224 | } |
| 4225 | |
| 4226 | #undef FLD |
| 4227 | } |
| 4228 | NEXT (vpc); |
| 4229 | |
| 4230 | CASE (sem, INSN_SETT_COMPACT) : /* sett */ |
| 4231 | { |
| 4232 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4233 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4234 | #define FLD(f) abuf->fields.fmt_empty.f |
| 4235 | int UNUSED written = 0; |
| 4236 | IADDR UNUSED pc = abuf->addr; |
| 4237 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4238 | |
| 4239 | { |
| 4240 | BI opval = 1; |
| 4241 | SET_H_TBIT (opval); |
| 4242 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4243 | } |
| 4244 | |
| 4245 | #undef FLD |
| 4246 | } |
| 4247 | NEXT (vpc); |
| 4248 | |
| 4249 | CASE (sem, INSN_SHAD_COMPACT) : /* shad $rm, $rn */ |
| 4250 | { |
| 4251 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4252 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4253 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 4254 | int UNUSED written = 0; |
| 4255 | IADDR UNUSED pc = abuf->addr; |
| 4256 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4257 | |
| 4258 | { |
| 4259 | SI tmp_shamt; |
| 4260 | tmp_shamt = ANDSI (GET_H_GRC (FLD (f_rm)), 31); |
| 4261 | if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { |
| 4262 | { |
| 4263 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); |
| 4264 | SET_H_GRC (FLD (f_rn), opval); |
| 4265 | written |= (1 << 2); |
| 4266 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4267 | } |
| 4268 | } else { |
| 4269 | if (NESI (tmp_shamt, 0)) { |
| 4270 | { |
| 4271 | SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); |
| 4272 | SET_H_GRC (FLD (f_rn), opval); |
| 4273 | written |= (1 << 2); |
| 4274 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4275 | } |
| 4276 | } else { |
| 4277 | if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) { |
| 4278 | { |
| 4279 | SI opval = NEGSI (1); |
| 4280 | SET_H_GRC (FLD (f_rn), opval); |
| 4281 | written |= (1 << 2); |
| 4282 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4283 | } |
| 4284 | } else { |
| 4285 | { |
| 4286 | SI opval = 0; |
| 4287 | SET_H_GRC (FLD (f_rn), opval); |
| 4288 | written |= (1 << 2); |
| 4289 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4290 | } |
| 4291 | } |
| 4292 | } |
| 4293 | } |
| 4294 | } |
| 4295 | |
| 4296 | abuf->written = written; |
| 4297 | #undef FLD |
| 4298 | } |
| 4299 | NEXT (vpc); |
| 4300 | |
| 4301 | CASE (sem, INSN_SHAL_COMPACT) : /* shal $rn */ |
| 4302 | { |
| 4303 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4304 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4305 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4306 | int UNUSED written = 0; |
| 4307 | IADDR UNUSED pc = abuf->addr; |
| 4308 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4309 | |
| 4310 | { |
| 4311 | BI tmp_t; |
| 4312 | tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31); |
| 4313 | { |
| 4314 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); |
| 4315 | SET_H_GRC (FLD (f_rn), opval); |
| 4316 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4317 | } |
| 4318 | { |
| 4319 | BI opval = ((tmp_t) ? (1) : (0)); |
| 4320 | SET_H_TBIT (opval); |
| 4321 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4322 | } |
| 4323 | } |
| 4324 | |
| 4325 | #undef FLD |
| 4326 | } |
| 4327 | NEXT (vpc); |
| 4328 | |
| 4329 | CASE (sem, INSN_SHAR_COMPACT) : /* shar $rn */ |
| 4330 | { |
| 4331 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4332 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4333 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4334 | int UNUSED written = 0; |
| 4335 | IADDR UNUSED pc = abuf->addr; |
| 4336 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4337 | |
| 4338 | { |
| 4339 | BI tmp_t; |
| 4340 | tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1); |
| 4341 | { |
| 4342 | SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1); |
| 4343 | SET_H_GRC (FLD (f_rn), opval); |
| 4344 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4345 | } |
| 4346 | { |
| 4347 | BI opval = ((tmp_t) ? (1) : (0)); |
| 4348 | SET_H_TBIT (opval); |
| 4349 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4350 | } |
| 4351 | } |
| 4352 | |
| 4353 | #undef FLD |
| 4354 | } |
| 4355 | NEXT (vpc); |
| 4356 | |
| 4357 | CASE (sem, INSN_SHLD_COMPACT) : /* shld $rm, $rn */ |
| 4358 | { |
| 4359 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4360 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4361 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 4362 | int UNUSED written = 0; |
| 4363 | IADDR UNUSED pc = abuf->addr; |
| 4364 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4365 | |
| 4366 | { |
| 4367 | SI tmp_shamt; |
| 4368 | tmp_shamt = ANDSI (GET_H_GRC (FLD (f_rm)), 31); |
| 4369 | if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { |
| 4370 | { |
| 4371 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); |
| 4372 | SET_H_GRC (FLD (f_rn), opval); |
| 4373 | written |= (1 << 2); |
| 4374 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4375 | } |
| 4376 | } else { |
| 4377 | if (NESI (tmp_shamt, 0)) { |
| 4378 | { |
| 4379 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); |
| 4380 | SET_H_GRC (FLD (f_rn), opval); |
| 4381 | written |= (1 << 2); |
| 4382 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4383 | } |
| 4384 | } else { |
| 4385 | { |
| 4386 | SI opval = 0; |
| 4387 | SET_H_GRC (FLD (f_rn), opval); |
| 4388 | written |= (1 << 2); |
| 4389 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4390 | } |
| 4391 | } |
| 4392 | } |
| 4393 | } |
| 4394 | |
| 4395 | abuf->written = written; |
| 4396 | #undef FLD |
| 4397 | } |
| 4398 | NEXT (vpc); |
| 4399 | |
| 4400 | CASE (sem, INSN_SHLL_COMPACT) : /* shll $rn */ |
| 4401 | { |
| 4402 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4403 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4404 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4405 | int UNUSED written = 0; |
| 4406 | IADDR UNUSED pc = abuf->addr; |
| 4407 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4408 | |
| 4409 | { |
| 4410 | BI tmp_t; |
| 4411 | tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31); |
| 4412 | { |
| 4413 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); |
| 4414 | SET_H_GRC (FLD (f_rn), opval); |
| 4415 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4416 | } |
| 4417 | { |
| 4418 | BI opval = ((tmp_t) ? (1) : (0)); |
| 4419 | SET_H_TBIT (opval); |
| 4420 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4421 | } |
| 4422 | } |
| 4423 | |
| 4424 | #undef FLD |
| 4425 | } |
| 4426 | NEXT (vpc); |
| 4427 | |
| 4428 | CASE (sem, INSN_SHLL2_COMPACT) : /* shll2 $rn */ |
| 4429 | { |
| 4430 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4431 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4432 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4433 | int UNUSED written = 0; |
| 4434 | IADDR UNUSED pc = abuf->addr; |
| 4435 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4436 | |
| 4437 | { |
| 4438 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2); |
| 4439 | SET_H_GRC (FLD (f_rn), opval); |
| 4440 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4441 | } |
| 4442 | |
| 4443 | #undef FLD |
| 4444 | } |
| 4445 | NEXT (vpc); |
| 4446 | |
| 4447 | CASE (sem, INSN_SHLL8_COMPACT) : /* shll8 $rn */ |
| 4448 | { |
| 4449 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4450 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4451 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4452 | int UNUSED written = 0; |
| 4453 | IADDR UNUSED pc = abuf->addr; |
| 4454 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4455 | |
| 4456 | { |
| 4457 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8); |
| 4458 | SET_H_GRC (FLD (f_rn), opval); |
| 4459 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4460 | } |
| 4461 | |
| 4462 | #undef FLD |
| 4463 | } |
| 4464 | NEXT (vpc); |
| 4465 | |
| 4466 | CASE (sem, INSN_SHLL16_COMPACT) : /* shll16 $rn */ |
| 4467 | { |
| 4468 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4469 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4470 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4471 | int UNUSED written = 0; |
| 4472 | IADDR UNUSED pc = abuf->addr; |
| 4473 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4474 | |
| 4475 | { |
| 4476 | SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16); |
| 4477 | SET_H_GRC (FLD (f_rn), opval); |
| 4478 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4479 | } |
| 4480 | |
| 4481 | #undef FLD |
| 4482 | } |
| 4483 | NEXT (vpc); |
| 4484 | |
| 4485 | CASE (sem, INSN_SHLR_COMPACT) : /* shlr $rn */ |
| 4486 | { |
| 4487 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4488 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4489 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4490 | int UNUSED written = 0; |
| 4491 | IADDR UNUSED pc = abuf->addr; |
| 4492 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4493 | |
| 4494 | { |
| 4495 | BI tmp_t; |
| 4496 | tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1); |
| 4497 | { |
| 4498 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1); |
| 4499 | SET_H_GRC (FLD (f_rn), opval); |
| 4500 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4501 | } |
| 4502 | { |
| 4503 | BI opval = ((tmp_t) ? (1) : (0)); |
| 4504 | SET_H_TBIT (opval); |
| 4505 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4506 | } |
| 4507 | } |
| 4508 | |
| 4509 | #undef FLD |
| 4510 | } |
| 4511 | NEXT (vpc); |
| 4512 | |
| 4513 | CASE (sem, INSN_SHLR2_COMPACT) : /* shlr2 $rn */ |
| 4514 | { |
| 4515 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4516 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4517 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4518 | int UNUSED written = 0; |
| 4519 | IADDR UNUSED pc = abuf->addr; |
| 4520 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4521 | |
| 4522 | { |
| 4523 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2); |
| 4524 | SET_H_GRC (FLD (f_rn), opval); |
| 4525 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4526 | } |
| 4527 | |
| 4528 | #undef FLD |
| 4529 | } |
| 4530 | NEXT (vpc); |
| 4531 | |
| 4532 | CASE (sem, INSN_SHLR8_COMPACT) : /* shlr8 $rn */ |
| 4533 | { |
| 4534 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4535 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4536 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4537 | int UNUSED written = 0; |
| 4538 | IADDR UNUSED pc = abuf->addr; |
| 4539 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4540 | |
| 4541 | { |
| 4542 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8); |
| 4543 | SET_H_GRC (FLD (f_rn), opval); |
| 4544 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4545 | } |
| 4546 | |
| 4547 | #undef FLD |
| 4548 | } |
| 4549 | NEXT (vpc); |
| 4550 | |
| 4551 | CASE (sem, INSN_SHLR16_COMPACT) : /* shlr16 $rn */ |
| 4552 | { |
| 4553 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4554 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4555 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4556 | int UNUSED written = 0; |
| 4557 | IADDR UNUSED pc = abuf->addr; |
| 4558 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4559 | |
| 4560 | { |
| 4561 | SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16); |
| 4562 | SET_H_GRC (FLD (f_rn), opval); |
| 4563 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4564 | } |
| 4565 | |
| 4566 | #undef FLD |
| 4567 | } |
| 4568 | NEXT (vpc); |
| 4569 | |
| 4570 | CASE (sem, INSN_STC_GBR_COMPACT) : /* stc gbr, $rn */ |
| 4571 | { |
| 4572 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4573 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4574 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4575 | int UNUSED written = 0; |
| 4576 | IADDR UNUSED pc = abuf->addr; |
| 4577 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4578 | |
| 4579 | { |
| 4580 | SI opval = GET_H_GBR (); |
| 4581 | SET_H_GRC (FLD (f_rn), opval); |
| 4582 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4583 | } |
| 4584 | |
| 4585 | #undef FLD |
| 4586 | } |
| 4587 | NEXT (vpc); |
| 4588 | |
| 4589 | CASE (sem, INSN_STC_VBR_COMPACT) : /* stc vbr, $rn */ |
| 4590 | { |
| 4591 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4592 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4593 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4594 | int UNUSED written = 0; |
| 4595 | IADDR UNUSED pc = abuf->addr; |
| 4596 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4597 | |
| 4598 | { |
| 4599 | SI opval = GET_H_VBR (); |
| 4600 | SET_H_GRC (FLD (f_rn), opval); |
| 4601 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4602 | } |
| 4603 | |
| 4604 | #undef FLD |
| 4605 | } |
| 4606 | NEXT (vpc); |
| 4607 | |
| 4608 | CASE (sem, INSN_STCL_GBR_COMPACT) : /* stc.l gbr, @-$rn */ |
| 4609 | { |
| 4610 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4611 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4612 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4613 | int UNUSED written = 0; |
| 4614 | IADDR UNUSED pc = abuf->addr; |
| 4615 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4616 | |
| 4617 | { |
| 4618 | DI tmp_addr; |
| 4619 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 4620 | { |
| 4621 | SI opval = GET_H_GBR (); |
| 4622 | SETMEMSI (current_cpu, pc, tmp_addr, opval); |
| 4623 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 4624 | } |
| 4625 | { |
| 4626 | SI opval = tmp_addr; |
| 4627 | SET_H_GRC (FLD (f_rn), opval); |
| 4628 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4629 | } |
| 4630 | } |
| 4631 | |
| 4632 | #undef FLD |
| 4633 | } |
| 4634 | NEXT (vpc); |
| 4635 | |
| 4636 | CASE (sem, INSN_STCL_VBR_COMPACT) : /* stc.l vbr, @-$rn */ |
| 4637 | { |
| 4638 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4639 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4640 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4641 | int UNUSED written = 0; |
| 4642 | IADDR UNUSED pc = abuf->addr; |
| 4643 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4644 | |
| 4645 | { |
| 4646 | DI tmp_addr; |
| 4647 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 4648 | { |
| 4649 | SI opval = GET_H_VBR (); |
| 4650 | SETMEMSI (current_cpu, pc, tmp_addr, opval); |
| 4651 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 4652 | } |
| 4653 | { |
| 4654 | SI opval = tmp_addr; |
| 4655 | SET_H_GRC (FLD (f_rn), opval); |
| 4656 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4657 | } |
| 4658 | } |
| 4659 | |
| 4660 | #undef FLD |
| 4661 | } |
| 4662 | NEXT (vpc); |
| 4663 | |
| 4664 | CASE (sem, INSN_STS_FPSCR_COMPACT) : /* sts fpscr, $rn */ |
| 4665 | { |
| 4666 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4667 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4668 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4669 | int UNUSED written = 0; |
| 4670 | IADDR UNUSED pc = abuf->addr; |
| 4671 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4672 | |
| 4673 | { |
| 4674 | SI opval = CPU (h_fpscr); |
| 4675 | SET_H_GRC (FLD (f_rn), opval); |
| 4676 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4677 | } |
| 4678 | |
| 4679 | #undef FLD |
| 4680 | } |
| 4681 | NEXT (vpc); |
| 4682 | |
| 4683 | CASE (sem, INSN_STSL_FPSCR_COMPACT) : /* sts.l fpscr, @-$rn */ |
| 4684 | { |
| 4685 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4686 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4687 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4688 | int UNUSED written = 0; |
| 4689 | IADDR UNUSED pc = abuf->addr; |
| 4690 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4691 | |
| 4692 | { |
| 4693 | DI tmp_addr; |
| 4694 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 4695 | { |
| 4696 | SI opval = CPU (h_fpscr); |
| 4697 | SETMEMSI (current_cpu, pc, tmp_addr, opval); |
| 4698 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 4699 | } |
| 4700 | { |
| 4701 | SI opval = tmp_addr; |
| 4702 | SET_H_GRC (FLD (f_rn), opval); |
| 4703 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4704 | } |
| 4705 | } |
| 4706 | |
| 4707 | #undef FLD |
| 4708 | } |
| 4709 | NEXT (vpc); |
| 4710 | |
| 4711 | CASE (sem, INSN_STS_FPUL_COMPACT) : /* sts fpul, $rn */ |
| 4712 | { |
| 4713 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4714 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4715 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4716 | int UNUSED written = 0; |
| 4717 | IADDR UNUSED pc = abuf->addr; |
| 4718 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4719 | |
| 4720 | { |
| 4721 | SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)])); |
| 4722 | SET_H_GRC (FLD (f_rn), opval); |
| 4723 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4724 | } |
| 4725 | |
| 4726 | #undef FLD |
| 4727 | } |
| 4728 | NEXT (vpc); |
| 4729 | |
| 4730 | CASE (sem, INSN_STSL_FPUL_COMPACT) : /* sts.l fpul, @-$rn */ |
| 4731 | { |
| 4732 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4733 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4734 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4735 | int UNUSED written = 0; |
| 4736 | IADDR UNUSED pc = abuf->addr; |
| 4737 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4738 | |
| 4739 | { |
| 4740 | DI tmp_addr; |
| 4741 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 4742 | { |
| 4743 | SF opval = CPU (h_fr[((UINT) 32)]); |
| 4744 | SETMEMSF (current_cpu, pc, tmp_addr, opval); |
| 4745 | TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); |
| 4746 | } |
| 4747 | { |
| 4748 | SI opval = tmp_addr; |
| 4749 | SET_H_GRC (FLD (f_rn), opval); |
| 4750 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4751 | } |
| 4752 | } |
| 4753 | |
| 4754 | #undef FLD |
| 4755 | } |
| 4756 | NEXT (vpc); |
| 4757 | |
| 4758 | CASE (sem, INSN_STS_MACH_COMPACT) : /* sts mach, $rn */ |
| 4759 | { |
| 4760 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4761 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4762 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4763 | int UNUSED written = 0; |
| 4764 | IADDR UNUSED pc = abuf->addr; |
| 4765 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4766 | |
| 4767 | { |
| 4768 | SI opval = GET_H_MACH (); |
| 4769 | SET_H_GRC (FLD (f_rn), opval); |
| 4770 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4771 | } |
| 4772 | |
| 4773 | #undef FLD |
| 4774 | } |
| 4775 | NEXT (vpc); |
| 4776 | |
| 4777 | CASE (sem, INSN_STSL_MACH_COMPACT) : /* sts.l mach, @-$rn */ |
| 4778 | { |
| 4779 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4780 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4781 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4782 | int UNUSED written = 0; |
| 4783 | IADDR UNUSED pc = abuf->addr; |
| 4784 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4785 | |
| 4786 | { |
| 4787 | DI tmp_addr; |
| 4788 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 4789 | { |
| 4790 | SI opval = GET_H_MACH (); |
| 4791 | SETMEMSI (current_cpu, pc, tmp_addr, opval); |
| 4792 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 4793 | } |
| 4794 | { |
| 4795 | SI opval = tmp_addr; |
| 4796 | SET_H_GRC (FLD (f_rn), opval); |
| 4797 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4798 | } |
| 4799 | } |
| 4800 | |
| 4801 | #undef FLD |
| 4802 | } |
| 4803 | NEXT (vpc); |
| 4804 | |
| 4805 | CASE (sem, INSN_STS_MACL_COMPACT) : /* sts macl, $rn */ |
| 4806 | { |
| 4807 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4808 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4809 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4810 | int UNUSED written = 0; |
| 4811 | IADDR UNUSED pc = abuf->addr; |
| 4812 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4813 | |
| 4814 | { |
| 4815 | SI opval = GET_H_MACL (); |
| 4816 | SET_H_GRC (FLD (f_rn), opval); |
| 4817 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4818 | } |
| 4819 | |
| 4820 | #undef FLD |
| 4821 | } |
| 4822 | NEXT (vpc); |
| 4823 | |
| 4824 | CASE (sem, INSN_STSL_MACL_COMPACT) : /* sts.l macl, @-$rn */ |
| 4825 | { |
| 4826 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4827 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4828 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4829 | int UNUSED written = 0; |
| 4830 | IADDR UNUSED pc = abuf->addr; |
| 4831 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4832 | |
| 4833 | { |
| 4834 | DI tmp_addr; |
| 4835 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 4836 | { |
| 4837 | SI opval = GET_H_MACL (); |
| 4838 | SETMEMSI (current_cpu, pc, tmp_addr, opval); |
| 4839 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 4840 | } |
| 4841 | { |
| 4842 | SI opval = tmp_addr; |
| 4843 | SET_H_GRC (FLD (f_rn), opval); |
| 4844 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4845 | } |
| 4846 | } |
| 4847 | |
| 4848 | #undef FLD |
| 4849 | } |
| 4850 | NEXT (vpc); |
| 4851 | |
| 4852 | CASE (sem, INSN_STS_PR_COMPACT) : /* sts pr, $rn */ |
| 4853 | { |
| 4854 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4855 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4856 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4857 | int UNUSED written = 0; |
| 4858 | IADDR UNUSED pc = abuf->addr; |
| 4859 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4860 | |
| 4861 | { |
| 4862 | SI opval = GET_H_PR (); |
| 4863 | SET_H_GRC (FLD (f_rn), opval); |
| 4864 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4865 | } |
| 4866 | |
| 4867 | #undef FLD |
| 4868 | } |
| 4869 | NEXT (vpc); |
| 4870 | |
| 4871 | CASE (sem, INSN_STSL_PR_COMPACT) : /* sts.l pr, @-$rn */ |
| 4872 | { |
| 4873 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4874 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4875 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 4876 | int UNUSED written = 0; |
| 4877 | IADDR UNUSED pc = abuf->addr; |
| 4878 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4879 | |
| 4880 | { |
| 4881 | DI tmp_addr; |
| 4882 | tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); |
| 4883 | { |
| 4884 | SI opval = GET_H_PR (); |
| 4885 | SETMEMSI (current_cpu, pc, tmp_addr, opval); |
| 4886 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 4887 | } |
| 4888 | { |
| 4889 | SI opval = tmp_addr; |
| 4890 | SET_H_GRC (FLD (f_rn), opval); |
| 4891 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4892 | } |
| 4893 | } |
| 4894 | |
| 4895 | #undef FLD |
| 4896 | } |
| 4897 | NEXT (vpc); |
| 4898 | |
| 4899 | CASE (sem, INSN_SUB_COMPACT) : /* sub $rm, $rn */ |
| 4900 | { |
| 4901 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4902 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4903 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 4904 | int UNUSED written = 0; |
| 4905 | IADDR UNUSED pc = abuf->addr; |
| 4906 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4907 | |
| 4908 | { |
| 4909 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 4910 | SET_H_GRC (FLD (f_rn), opval); |
| 4911 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4912 | } |
| 4913 | |
| 4914 | #undef FLD |
| 4915 | } |
| 4916 | NEXT (vpc); |
| 4917 | |
| 4918 | CASE (sem, INSN_SUBC_COMPACT) : /* subc $rm, $rn */ |
| 4919 | { |
| 4920 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4921 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4922 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 4923 | int UNUSED written = 0; |
| 4924 | IADDR UNUSED pc = abuf->addr; |
| 4925 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4926 | |
| 4927 | { |
| 4928 | BI tmp_flag; |
| 4929 | tmp_flag = SUBCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); |
| 4930 | { |
| 4931 | SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); |
| 4932 | SET_H_GRC (FLD (f_rn), opval); |
| 4933 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4934 | } |
| 4935 | { |
| 4936 | BI opval = tmp_flag; |
| 4937 | SET_H_TBIT (opval); |
| 4938 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4939 | } |
| 4940 | } |
| 4941 | |
| 4942 | #undef FLD |
| 4943 | } |
| 4944 | NEXT (vpc); |
| 4945 | |
| 4946 | CASE (sem, INSN_SUBV_COMPACT) : /* subv $rm, $rn */ |
| 4947 | { |
| 4948 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4949 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4950 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 4951 | int UNUSED written = 0; |
| 4952 | IADDR UNUSED pc = abuf->addr; |
| 4953 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4954 | |
| 4955 | { |
| 4956 | BI tmp_t; |
| 4957 | tmp_t = SUBOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0); |
| 4958 | { |
| 4959 | SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); |
| 4960 | SET_H_GRC (FLD (f_rn), opval); |
| 4961 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4962 | } |
| 4963 | { |
| 4964 | BI opval = ((tmp_t) ? (1) : (0)); |
| 4965 | SET_H_TBIT (opval); |
| 4966 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 4967 | } |
| 4968 | } |
| 4969 | |
| 4970 | #undef FLD |
| 4971 | } |
| 4972 | NEXT (vpc); |
| 4973 | |
| 4974 | CASE (sem, INSN_SWAPB_COMPACT) : /* swap.b $rm, $rn */ |
| 4975 | { |
| 4976 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 4977 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 4978 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 4979 | int UNUSED written = 0; |
| 4980 | IADDR UNUSED pc = abuf->addr; |
| 4981 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 4982 | |
| 4983 | { |
| 4984 | UHI tmp_top_half; |
| 4985 | UQI tmp_byte1; |
| 4986 | UQI tmp_byte0; |
| 4987 | tmp_top_half = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 0); |
| 4988 | tmp_byte1 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 2); |
| 4989 | tmp_byte0 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3); |
| 4990 | { |
| 4991 | SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1)); |
| 4992 | SET_H_GRC (FLD (f_rn), opval); |
| 4993 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 4994 | } |
| 4995 | } |
| 4996 | |
| 4997 | #undef FLD |
| 4998 | } |
| 4999 | NEXT (vpc); |
| 5000 | |
| 5001 | CASE (sem, INSN_SWAPW_COMPACT) : /* swap.w $rm, $rn */ |
| 5002 | { |
| 5003 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5004 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5005 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 5006 | int UNUSED written = 0; |
| 5007 | IADDR UNUSED pc = abuf->addr; |
| 5008 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5009 | |
| 5010 | { |
| 5011 | SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16)); |
| 5012 | SET_H_GRC (FLD (f_rn), opval); |
| 5013 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 5014 | } |
| 5015 | |
| 5016 | #undef FLD |
| 5017 | } |
| 5018 | NEXT (vpc); |
| 5019 | |
| 5020 | CASE (sem, INSN_TASB_COMPACT) : /* tas.b @$rn */ |
| 5021 | { |
| 5022 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5023 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5024 | #define FLD(f) abuf->fields.sfmt_movw10_compact.f |
| 5025 | int UNUSED written = 0; |
| 5026 | IADDR UNUSED pc = abuf->addr; |
| 5027 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5028 | |
| 5029 | { |
| 5030 | UQI tmp_byte; |
| 5031 | tmp_byte = GETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); |
| 5032 | { |
| 5033 | BI opval = ((EQQI (tmp_byte, 0)) ? (1) : (0)); |
| 5034 | SET_H_TBIT (opval); |
| 5035 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 5036 | } |
| 5037 | tmp_byte = ORQI (tmp_byte, 128); |
| 5038 | { |
| 5039 | UQI opval = tmp_byte; |
| 5040 | SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); |
| 5041 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 5042 | } |
| 5043 | } |
| 5044 | |
| 5045 | #undef FLD |
| 5046 | } |
| 5047 | NEXT (vpc); |
| 5048 | |
| 5049 | CASE (sem, INSN_TRAPA_COMPACT) : /* trapa #$uimm8 */ |
| 5050 | { |
| 5051 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5052 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5053 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 5054 | int UNUSED written = 0; |
| 5055 | IADDR UNUSED pc = abuf->addr; |
| 5056 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5057 | |
| 5058 | sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); |
| 5059 | |
| 5060 | #undef FLD |
| 5061 | } |
| 5062 | NEXT (vpc); |
| 5063 | |
| 5064 | CASE (sem, INSN_TST_COMPACT) : /* tst $rm, $rn */ |
| 5065 | { |
| 5066 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5067 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5068 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 5069 | int UNUSED written = 0; |
| 5070 | IADDR UNUSED pc = abuf->addr; |
| 5071 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5072 | |
| 5073 | { |
| 5074 | BI opval = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))), 0)) ? (1) : (0)); |
| 5075 | SET_H_TBIT (opval); |
| 5076 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 5077 | } |
| 5078 | |
| 5079 | #undef FLD |
| 5080 | } |
| 5081 | NEXT (vpc); |
| 5082 | |
| 5083 | CASE (sem, INSN_TSTI_COMPACT) : /* tst #$uimm8, r0 */ |
| 5084 | { |
| 5085 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5086 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5087 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 5088 | int UNUSED written = 0; |
| 5089 | IADDR UNUSED pc = abuf->addr; |
| 5090 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5091 | |
| 5092 | { |
| 5093 | BI opval = ((EQSI (ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSISI (FLD (f_imm8))), 0)) ? (1) : (0)); |
| 5094 | SET_H_TBIT (opval); |
| 5095 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 5096 | } |
| 5097 | |
| 5098 | #undef FLD |
| 5099 | } |
| 5100 | NEXT (vpc); |
| 5101 | |
| 5102 | CASE (sem, INSN_TSTB_COMPACT) : /* tst.b #$imm8, @(r0, gbr) */ |
| 5103 | { |
| 5104 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5105 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5106 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 5107 | int UNUSED written = 0; |
| 5108 | IADDR UNUSED pc = abuf->addr; |
| 5109 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5110 | |
| 5111 | { |
| 5112 | DI tmp_addr; |
| 5113 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); |
| 5114 | { |
| 5115 | BI opval = ((EQQI (ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)), 0)) ? (1) : (0)); |
| 5116 | SET_H_TBIT (opval); |
| 5117 | TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); |
| 5118 | } |
| 5119 | } |
| 5120 | |
| 5121 | #undef FLD |
| 5122 | } |
| 5123 | NEXT (vpc); |
| 5124 | |
| 5125 | CASE (sem, INSN_XOR_COMPACT) : /* xor $rm64, $rn64 */ |
| 5126 | { |
| 5127 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5128 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5129 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 5130 | int UNUSED written = 0; |
| 5131 | IADDR UNUSED pc = abuf->addr; |
| 5132 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5133 | |
| 5134 | { |
| 5135 | DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm))); |
| 5136 | SET_H_GR (FLD (f_rn), opval); |
| 5137 | TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); |
| 5138 | } |
| 5139 | |
| 5140 | #undef FLD |
| 5141 | } |
| 5142 | NEXT (vpc); |
| 5143 | |
| 5144 | CASE (sem, INSN_XORI_COMPACT) : /* xor #$uimm8, r0 */ |
| 5145 | { |
| 5146 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5147 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5148 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 5149 | int UNUSED written = 0; |
| 5150 | IADDR UNUSED pc = abuf->addr; |
| 5151 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5152 | |
| 5153 | { |
| 5154 | SI opval = XORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); |
| 5155 | SET_H_GRC (((UINT) 0), opval); |
| 5156 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 5157 | } |
| 5158 | |
| 5159 | #undef FLD |
| 5160 | } |
| 5161 | NEXT (vpc); |
| 5162 | |
| 5163 | CASE (sem, INSN_XORB_COMPACT) : /* xor.b #$imm8, @(r0, gbr) */ |
| 5164 | { |
| 5165 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5166 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5167 | #define FLD(f) abuf->fields.sfmt_addi_compact.f |
| 5168 | int UNUSED written = 0; |
| 5169 | IADDR UNUSED pc = abuf->addr; |
| 5170 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5171 | |
| 5172 | { |
| 5173 | DI tmp_addr; |
| 5174 | UQI tmp_data; |
| 5175 | tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ()); |
| 5176 | tmp_data = XORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)); |
| 5177 | { |
| 5178 | UQI opval = tmp_data; |
| 5179 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); |
| 5180 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); |
| 5181 | } |
| 5182 | } |
| 5183 | |
| 5184 | #undef FLD |
| 5185 | } |
| 5186 | NEXT (vpc); |
| 5187 | |
| 5188 | CASE (sem, INSN_XTRCT_COMPACT) : /* xtrct $rm, $rn */ |
| 5189 | { |
| 5190 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); |
| 5191 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
| 5192 | #define FLD(f) abuf->fields.sfmt_movl12_compact.f |
| 5193 | int UNUSED written = 0; |
| 5194 | IADDR UNUSED pc = abuf->addr; |
| 5195 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); |
| 5196 | |
| 5197 | { |
| 5198 | SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16)); |
| 5199 | SET_H_GRC (FLD (f_rn), opval); |
| 5200 | TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); |
| 5201 | } |
| 5202 | |
| 5203 | #undef FLD |
| 5204 | } |
| 5205 | NEXT (vpc); |
| 5206 | |
| 5207 | |
| 5208 | } |
| 5209 | ENDSWITCH (sem) /* End of semantic switch. */ |
| 5210 | |
| 5211 | /* At this point `vpc' contains the next insn to execute. */ |
| 5212 | } |
| 5213 | |
| 5214 | #undef DEFINE_SWITCH |
| 5215 | #endif /* DEFINE_SWITCH */ |