| 1 | /* CPU data for sh. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #include "sysdep.h" |
| 26 | #include <ctype.h> |
| 27 | #include <stdio.h> |
| 28 | #include <stdarg.h> |
| 29 | #include "ansidecl.h" |
| 30 | #include "bfd.h" |
| 31 | #include "symcat.h" |
| 32 | #include "sh-desc.h" |
| 33 | #include "sh-opc.h" |
| 34 | #include "opintl.h" |
| 35 | #include "libiberty.h" |
| 36 | |
| 37 | /* Attributes. */ |
| 38 | |
| 39 | static const CGEN_ATTR_ENTRY bool_attr[] = |
| 40 | { |
| 41 | { "#f", 0 }, |
| 42 | { "#t", 1 }, |
| 43 | { 0, 0 } |
| 44 | }; |
| 45 | |
| 46 | static const CGEN_ATTR_ENTRY MACH_attr[] = |
| 47 | { |
| 48 | { "base", MACH_BASE }, |
| 49 | { "sh2", MACH_SH2 }, |
| 50 | { "sh3", MACH_SH3 }, |
| 51 | { "sh3e", MACH_SH3E }, |
| 52 | { "sh4", MACH_SH4 }, |
| 53 | { "sh5", MACH_SH5 }, |
| 54 | { "max", MACH_MAX }, |
| 55 | { 0, 0 } |
| 56 | }; |
| 57 | |
| 58 | static const CGEN_ATTR_ENTRY ISA_attr[] = |
| 59 | { |
| 60 | { "compact", ISA_COMPACT }, |
| 61 | { "media", ISA_MEDIA }, |
| 62 | { "max", ISA_MAX }, |
| 63 | { 0, 0 } |
| 64 | }; |
| 65 | |
| 66 | const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[] = |
| 67 | { |
| 68 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 69 | { "ISA", & ISA_attr[0], & ISA_attr[0] }, |
| 70 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 71 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 72 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 73 | { "RESERVED", &bool_attr[0], &bool_attr[0] }, |
| 74 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, |
| 75 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, |
| 76 | { 0, 0, 0 } |
| 77 | }; |
| 78 | |
| 79 | const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[] = |
| 80 | { |
| 81 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 82 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 83 | { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 84 | { "PC", &bool_attr[0], &bool_attr[0] }, |
| 85 | { "PROFILE", &bool_attr[0], &bool_attr[0] }, |
| 86 | { 0, 0, 0 } |
| 87 | }; |
| 88 | |
| 89 | const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[] = |
| 90 | { |
| 91 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 92 | { "ISA", & ISA_attr[0], & ISA_attr[0] }, |
| 93 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 94 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 95 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 96 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, |
| 97 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, |
| 98 | { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, |
| 99 | { "RELAX", &bool_attr[0], &bool_attr[0] }, |
| 100 | { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, |
| 101 | { 0, 0, 0 } |
| 102 | }; |
| 103 | |
| 104 | const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[] = |
| 105 | { |
| 106 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 107 | { "ISA", & ISA_attr[0], & ISA_attr[0] }, |
| 108 | { "ALIAS", &bool_attr[0], &bool_attr[0] }, |
| 109 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 110 | { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, |
| 111 | { "COND-CTI", &bool_attr[0], &bool_attr[0] }, |
| 112 | { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, |
| 113 | { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, |
| 114 | { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, |
| 115 | { "RELAX", &bool_attr[0], &bool_attr[0] }, |
| 116 | { "NO-DIS", &bool_attr[0], &bool_attr[0] }, |
| 117 | { "PBB", &bool_attr[0], &bool_attr[0] }, |
| 118 | { "ILLSLOT", &bool_attr[0], &bool_attr[0] }, |
| 119 | { "FP-INSN", &bool_attr[0], &bool_attr[0] }, |
| 120 | { 0, 0, 0 } |
| 121 | }; |
| 122 | |
| 123 | /* Instruction set variants. */ |
| 124 | |
| 125 | static const CGEN_ISA sh_cgen_isa_table[] = { |
| 126 | { "media", 32, 32, 32, 32 }, |
| 127 | { "compact", 16, 16, 16, 16 }, |
| 128 | { 0, 0, 0, 0, 0 } |
| 129 | }; |
| 130 | |
| 131 | /* Machine variants. */ |
| 132 | |
| 133 | static const CGEN_MACH sh_cgen_mach_table[] = { |
| 134 | { "sh2", "sh2", MACH_SH2 }, |
| 135 | { "sh3", "sh3", MACH_SH3 }, |
| 136 | { "sh3e", "sh3e", MACH_SH3E }, |
| 137 | { "sh4", "sh4", MACH_SH4 }, |
| 138 | { "sh5", "sh5", MACH_SH5 }, |
| 139 | { 0, 0, 0 } |
| 140 | }; |
| 141 | |
| 142 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_frc_names_entries[] = |
| 143 | { |
| 144 | { "fr0", 0, {0, {0}}, 0, 0 }, |
| 145 | { "fr1", 1, {0, {0}}, 0, 0 }, |
| 146 | { "fr2", 2, {0, {0}}, 0, 0 }, |
| 147 | { "fr3", 3, {0, {0}}, 0, 0 }, |
| 148 | { "fr4", 4, {0, {0}}, 0, 0 }, |
| 149 | { "fr5", 5, {0, {0}}, 0, 0 }, |
| 150 | { "fr6", 6, {0, {0}}, 0, 0 }, |
| 151 | { "fr7", 7, {0, {0}}, 0, 0 }, |
| 152 | { "fr8", 8, {0, {0}}, 0, 0 }, |
| 153 | { "fr9", 9, {0, {0}}, 0, 0 }, |
| 154 | { "fr10", 10, {0, {0}}, 0, 0 }, |
| 155 | { "fr11", 11, {0, {0}}, 0, 0 }, |
| 156 | { "fr12", 12, {0, {0}}, 0, 0 }, |
| 157 | { "fr13", 13, {0, {0}}, 0, 0 }, |
| 158 | { "fr14", 14, {0, {0}}, 0, 0 }, |
| 159 | { "fr15", 15, {0, {0}}, 0, 0 } |
| 160 | }; |
| 161 | |
| 162 | CGEN_KEYWORD sh_cgen_opval_frc_names = |
| 163 | { |
| 164 | & sh_cgen_opval_frc_names_entries[0], |
| 165 | 16, |
| 166 | 0, 0, 0, 0 |
| 167 | }; |
| 168 | |
| 169 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_drc_names_entries[] = |
| 170 | { |
| 171 | { "dr0", 0, {0, {0}}, 0, 0 }, |
| 172 | { "dr2", 2, {0, {0}}, 0, 0 }, |
| 173 | { "dr4", 4, {0, {0}}, 0, 0 }, |
| 174 | { "dr6", 6, {0, {0}}, 0, 0 }, |
| 175 | { "dr8", 8, {0, {0}}, 0, 0 }, |
| 176 | { "dr10", 10, {0, {0}}, 0, 0 }, |
| 177 | { "dr12", 12, {0, {0}}, 0, 0 }, |
| 178 | { "dr14", 14, {0, {0}}, 0, 0 } |
| 179 | }; |
| 180 | |
| 181 | CGEN_KEYWORD sh_cgen_opval_drc_names = |
| 182 | { |
| 183 | & sh_cgen_opval_drc_names_entries[0], |
| 184 | 8, |
| 185 | 0, 0, 0, 0 |
| 186 | }; |
| 187 | |
| 188 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_xf_names_entries[] = |
| 189 | { |
| 190 | { "xf0", 0, {0, {0}}, 0, 0 }, |
| 191 | { "xf1", 1, {0, {0}}, 0, 0 }, |
| 192 | { "xf2", 2, {0, {0}}, 0, 0 }, |
| 193 | { "xf3", 3, {0, {0}}, 0, 0 }, |
| 194 | { "xf4", 4, {0, {0}}, 0, 0 }, |
| 195 | { "xf5", 5, {0, {0}}, 0, 0 }, |
| 196 | { "xf6", 6, {0, {0}}, 0, 0 }, |
| 197 | { "xf7", 7, {0, {0}}, 0, 0 }, |
| 198 | { "xf8", 8, {0, {0}}, 0, 0 }, |
| 199 | { "xf9", 9, {0, {0}}, 0, 0 }, |
| 200 | { "xf10", 10, {0, {0}}, 0, 0 }, |
| 201 | { "xf11", 11, {0, {0}}, 0, 0 }, |
| 202 | { "xf12", 12, {0, {0}}, 0, 0 }, |
| 203 | { "xf13", 13, {0, {0}}, 0, 0 }, |
| 204 | { "xf14", 14, {0, {0}}, 0, 0 }, |
| 205 | { "xf15", 15, {0, {0}}, 0, 0 } |
| 206 | }; |
| 207 | |
| 208 | CGEN_KEYWORD sh_cgen_opval_xf_names = |
| 209 | { |
| 210 | & sh_cgen_opval_xf_names_entries[0], |
| 211 | 16, |
| 212 | 0, 0, 0, 0 |
| 213 | }; |
| 214 | |
| 215 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_gr_entries[] = |
| 216 | { |
| 217 | { "r0", 0, {0, {0}}, 0, 0 }, |
| 218 | { "r1", 1, {0, {0}}, 0, 0 }, |
| 219 | { "r2", 2, {0, {0}}, 0, 0 }, |
| 220 | { "r3", 3, {0, {0}}, 0, 0 }, |
| 221 | { "r4", 4, {0, {0}}, 0, 0 }, |
| 222 | { "r5", 5, {0, {0}}, 0, 0 }, |
| 223 | { "r6", 6, {0, {0}}, 0, 0 }, |
| 224 | { "r7", 7, {0, {0}}, 0, 0 }, |
| 225 | { "r8", 8, {0, {0}}, 0, 0 }, |
| 226 | { "r9", 9, {0, {0}}, 0, 0 }, |
| 227 | { "r10", 10, {0, {0}}, 0, 0 }, |
| 228 | { "r11", 11, {0, {0}}, 0, 0 }, |
| 229 | { "r12", 12, {0, {0}}, 0, 0 }, |
| 230 | { "r13", 13, {0, {0}}, 0, 0 }, |
| 231 | { "r14", 14, {0, {0}}, 0, 0 }, |
| 232 | { "r15", 15, {0, {0}}, 0, 0 }, |
| 233 | { "r16", 16, {0, {0}}, 0, 0 }, |
| 234 | { "r17", 17, {0, {0}}, 0, 0 }, |
| 235 | { "r18", 18, {0, {0}}, 0, 0 }, |
| 236 | { "r19", 19, {0, {0}}, 0, 0 }, |
| 237 | { "r20", 20, {0, {0}}, 0, 0 }, |
| 238 | { "r21", 21, {0, {0}}, 0, 0 }, |
| 239 | { "r22", 22, {0, {0}}, 0, 0 }, |
| 240 | { "r23", 23, {0, {0}}, 0, 0 }, |
| 241 | { "r24", 24, {0, {0}}, 0, 0 }, |
| 242 | { "r25", 25, {0, {0}}, 0, 0 }, |
| 243 | { "r26", 26, {0, {0}}, 0, 0 }, |
| 244 | { "r27", 27, {0, {0}}, 0, 0 }, |
| 245 | { "r28", 28, {0, {0}}, 0, 0 }, |
| 246 | { "r29", 29, {0, {0}}, 0, 0 }, |
| 247 | { "r30", 30, {0, {0}}, 0, 0 }, |
| 248 | { "r31", 31, {0, {0}}, 0, 0 }, |
| 249 | { "r32", 32, {0, {0}}, 0, 0 }, |
| 250 | { "r33", 33, {0, {0}}, 0, 0 }, |
| 251 | { "r34", 34, {0, {0}}, 0, 0 }, |
| 252 | { "r35", 35, {0, {0}}, 0, 0 }, |
| 253 | { "r36", 36, {0, {0}}, 0, 0 }, |
| 254 | { "r37", 37, {0, {0}}, 0, 0 }, |
| 255 | { "r38", 38, {0, {0}}, 0, 0 }, |
| 256 | { "r39", 39, {0, {0}}, 0, 0 }, |
| 257 | { "r40", 40, {0, {0}}, 0, 0 }, |
| 258 | { "r41", 41, {0, {0}}, 0, 0 }, |
| 259 | { "r42", 42, {0, {0}}, 0, 0 }, |
| 260 | { "r43", 43, {0, {0}}, 0, 0 }, |
| 261 | { "r44", 44, {0, {0}}, 0, 0 }, |
| 262 | { "r45", 45, {0, {0}}, 0, 0 }, |
| 263 | { "r46", 46, {0, {0}}, 0, 0 }, |
| 264 | { "r47", 47, {0, {0}}, 0, 0 }, |
| 265 | { "r48", 48, {0, {0}}, 0, 0 }, |
| 266 | { "r49", 49, {0, {0}}, 0, 0 }, |
| 267 | { "r50", 50, {0, {0}}, 0, 0 }, |
| 268 | { "r51", 51, {0, {0}}, 0, 0 }, |
| 269 | { "r52", 52, {0, {0}}, 0, 0 }, |
| 270 | { "r53", 53, {0, {0}}, 0, 0 }, |
| 271 | { "r54", 54, {0, {0}}, 0, 0 }, |
| 272 | { "r55", 55, {0, {0}}, 0, 0 }, |
| 273 | { "r56", 56, {0, {0}}, 0, 0 }, |
| 274 | { "r57", 57, {0, {0}}, 0, 0 }, |
| 275 | { "r58", 58, {0, {0}}, 0, 0 }, |
| 276 | { "r59", 59, {0, {0}}, 0, 0 }, |
| 277 | { "r60", 60, {0, {0}}, 0, 0 }, |
| 278 | { "r61", 61, {0, {0}}, 0, 0 }, |
| 279 | { "r62", 62, {0, {0}}, 0, 0 }, |
| 280 | { "r63", 63, {0, {0}}, 0, 0 } |
| 281 | }; |
| 282 | |
| 283 | CGEN_KEYWORD sh_cgen_opval_h_gr = |
| 284 | { |
| 285 | & sh_cgen_opval_h_gr_entries[0], |
| 286 | 64, |
| 287 | 0, 0, 0, 0 |
| 288 | }; |
| 289 | |
| 290 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_grc_entries[] = |
| 291 | { |
| 292 | { "r0", 0, {0, {0}}, 0, 0 }, |
| 293 | { "r1", 1, {0, {0}}, 0, 0 }, |
| 294 | { "r2", 2, {0, {0}}, 0, 0 }, |
| 295 | { "r3", 3, {0, {0}}, 0, 0 }, |
| 296 | { "r4", 4, {0, {0}}, 0, 0 }, |
| 297 | { "r5", 5, {0, {0}}, 0, 0 }, |
| 298 | { "r6", 6, {0, {0}}, 0, 0 }, |
| 299 | { "r7", 7, {0, {0}}, 0, 0 }, |
| 300 | { "r8", 8, {0, {0}}, 0, 0 }, |
| 301 | { "r9", 9, {0, {0}}, 0, 0 }, |
| 302 | { "r10", 10, {0, {0}}, 0, 0 }, |
| 303 | { "r11", 11, {0, {0}}, 0, 0 }, |
| 304 | { "r12", 12, {0, {0}}, 0, 0 }, |
| 305 | { "r13", 13, {0, {0}}, 0, 0 }, |
| 306 | { "r14", 14, {0, {0}}, 0, 0 }, |
| 307 | { "r15", 15, {0, {0}}, 0, 0 } |
| 308 | }; |
| 309 | |
| 310 | CGEN_KEYWORD sh_cgen_opval_h_grc = |
| 311 | { |
| 312 | & sh_cgen_opval_h_grc_entries[0], |
| 313 | 16, |
| 314 | 0, 0, 0, 0 |
| 315 | }; |
| 316 | |
| 317 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_cr_entries[] = |
| 318 | { |
| 319 | { "cr0", 0, {0, {0}}, 0, 0 }, |
| 320 | { "cr1", 1, {0, {0}}, 0, 0 }, |
| 321 | { "cr2", 2, {0, {0}}, 0, 0 }, |
| 322 | { "cr3", 3, {0, {0}}, 0, 0 }, |
| 323 | { "cr4", 4, {0, {0}}, 0, 0 }, |
| 324 | { "cr5", 5, {0, {0}}, 0, 0 }, |
| 325 | { "cr6", 6, {0, {0}}, 0, 0 }, |
| 326 | { "cr7", 7, {0, {0}}, 0, 0 }, |
| 327 | { "cr8", 8, {0, {0}}, 0, 0 }, |
| 328 | { "cr9", 9, {0, {0}}, 0, 0 }, |
| 329 | { "cr10", 10, {0, {0}}, 0, 0 }, |
| 330 | { "cr11", 11, {0, {0}}, 0, 0 }, |
| 331 | { "cr12", 12, {0, {0}}, 0, 0 }, |
| 332 | { "cr13", 13, {0, {0}}, 0, 0 }, |
| 333 | { "cr14", 14, {0, {0}}, 0, 0 }, |
| 334 | { "cr15", 15, {0, {0}}, 0, 0 }, |
| 335 | { "cr16", 16, {0, {0}}, 0, 0 }, |
| 336 | { "cr17", 17, {0, {0}}, 0, 0 }, |
| 337 | { "cr18", 18, {0, {0}}, 0, 0 }, |
| 338 | { "cr19", 19, {0, {0}}, 0, 0 }, |
| 339 | { "cr20", 20, {0, {0}}, 0, 0 }, |
| 340 | { "cr21", 21, {0, {0}}, 0, 0 }, |
| 341 | { "cr22", 22, {0, {0}}, 0, 0 }, |
| 342 | { "cr23", 23, {0, {0}}, 0, 0 }, |
| 343 | { "cr24", 24, {0, {0}}, 0, 0 }, |
| 344 | { "cr25", 25, {0, {0}}, 0, 0 }, |
| 345 | { "cr26", 26, {0, {0}}, 0, 0 }, |
| 346 | { "cr27", 27, {0, {0}}, 0, 0 }, |
| 347 | { "cr28", 28, {0, {0}}, 0, 0 }, |
| 348 | { "cr29", 29, {0, {0}}, 0, 0 }, |
| 349 | { "cr30", 30, {0, {0}}, 0, 0 }, |
| 350 | { "cr31", 31, {0, {0}}, 0, 0 }, |
| 351 | { "cr32", 32, {0, {0}}, 0, 0 }, |
| 352 | { "cr33", 33, {0, {0}}, 0, 0 }, |
| 353 | { "cr34", 34, {0, {0}}, 0, 0 }, |
| 354 | { "cr35", 35, {0, {0}}, 0, 0 }, |
| 355 | { "cr36", 36, {0, {0}}, 0, 0 }, |
| 356 | { "cr37", 37, {0, {0}}, 0, 0 }, |
| 357 | { "cr38", 38, {0, {0}}, 0, 0 }, |
| 358 | { "cr39", 39, {0, {0}}, 0, 0 }, |
| 359 | { "cr40", 40, {0, {0}}, 0, 0 }, |
| 360 | { "cr41", 41, {0, {0}}, 0, 0 }, |
| 361 | { "cr42", 42, {0, {0}}, 0, 0 }, |
| 362 | { "cr43", 43, {0, {0}}, 0, 0 }, |
| 363 | { "cr44", 44, {0, {0}}, 0, 0 }, |
| 364 | { "cr45", 45, {0, {0}}, 0, 0 }, |
| 365 | { "cr46", 46, {0, {0}}, 0, 0 }, |
| 366 | { "cr47", 47, {0, {0}}, 0, 0 }, |
| 367 | { "cr48", 48, {0, {0}}, 0, 0 }, |
| 368 | { "cr49", 49, {0, {0}}, 0, 0 }, |
| 369 | { "cr50", 50, {0, {0}}, 0, 0 }, |
| 370 | { "cr51", 51, {0, {0}}, 0, 0 }, |
| 371 | { "cr52", 52, {0, {0}}, 0, 0 }, |
| 372 | { "cr53", 53, {0, {0}}, 0, 0 }, |
| 373 | { "cr54", 54, {0, {0}}, 0, 0 }, |
| 374 | { "cr55", 55, {0, {0}}, 0, 0 }, |
| 375 | { "cr56", 56, {0, {0}}, 0, 0 }, |
| 376 | { "cr57", 57, {0, {0}}, 0, 0 }, |
| 377 | { "cr58", 58, {0, {0}}, 0, 0 }, |
| 378 | { "cr59", 59, {0, {0}}, 0, 0 }, |
| 379 | { "cr60", 60, {0, {0}}, 0, 0 }, |
| 380 | { "cr61", 61, {0, {0}}, 0, 0 }, |
| 381 | { "cr62", 62, {0, {0}}, 0, 0 }, |
| 382 | { "cr63", 63, {0, {0}}, 0, 0 } |
| 383 | }; |
| 384 | |
| 385 | CGEN_KEYWORD sh_cgen_opval_h_cr = |
| 386 | { |
| 387 | & sh_cgen_opval_h_cr_entries[0], |
| 388 | 64, |
| 389 | 0, 0, 0, 0 |
| 390 | }; |
| 391 | |
| 392 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fr_entries[] = |
| 393 | { |
| 394 | { "fr0", 0, {0, {0}}, 0, 0 }, |
| 395 | { "fr1", 1, {0, {0}}, 0, 0 }, |
| 396 | { "fr2", 2, {0, {0}}, 0, 0 }, |
| 397 | { "fr3", 3, {0, {0}}, 0, 0 }, |
| 398 | { "fr4", 4, {0, {0}}, 0, 0 }, |
| 399 | { "fr5", 5, {0, {0}}, 0, 0 }, |
| 400 | { "fr6", 6, {0, {0}}, 0, 0 }, |
| 401 | { "fr7", 7, {0, {0}}, 0, 0 }, |
| 402 | { "fr8", 8, {0, {0}}, 0, 0 }, |
| 403 | { "fr9", 9, {0, {0}}, 0, 0 }, |
| 404 | { "fr10", 10, {0, {0}}, 0, 0 }, |
| 405 | { "fr11", 11, {0, {0}}, 0, 0 }, |
| 406 | { "fr12", 12, {0, {0}}, 0, 0 }, |
| 407 | { "fr13", 13, {0, {0}}, 0, 0 }, |
| 408 | { "fr14", 14, {0, {0}}, 0, 0 }, |
| 409 | { "fr15", 15, {0, {0}}, 0, 0 }, |
| 410 | { "fr16", 16, {0, {0}}, 0, 0 }, |
| 411 | { "fr17", 17, {0, {0}}, 0, 0 }, |
| 412 | { "fr18", 18, {0, {0}}, 0, 0 }, |
| 413 | { "fr19", 19, {0, {0}}, 0, 0 }, |
| 414 | { "fr20", 20, {0, {0}}, 0, 0 }, |
| 415 | { "fr21", 21, {0, {0}}, 0, 0 }, |
| 416 | { "fr22", 22, {0, {0}}, 0, 0 }, |
| 417 | { "fr23", 23, {0, {0}}, 0, 0 }, |
| 418 | { "fr24", 24, {0, {0}}, 0, 0 }, |
| 419 | { "fr25", 25, {0, {0}}, 0, 0 }, |
| 420 | { "fr26", 26, {0, {0}}, 0, 0 }, |
| 421 | { "fr27", 27, {0, {0}}, 0, 0 }, |
| 422 | { "fr28", 28, {0, {0}}, 0, 0 }, |
| 423 | { "fr29", 29, {0, {0}}, 0, 0 }, |
| 424 | { "fr30", 30, {0, {0}}, 0, 0 }, |
| 425 | { "fr31", 31, {0, {0}}, 0, 0 }, |
| 426 | { "fr32", 32, {0, {0}}, 0, 0 }, |
| 427 | { "fr33", 33, {0, {0}}, 0, 0 }, |
| 428 | { "fr34", 34, {0, {0}}, 0, 0 }, |
| 429 | { "fr35", 35, {0, {0}}, 0, 0 }, |
| 430 | { "fr36", 36, {0, {0}}, 0, 0 }, |
| 431 | { "fr37", 37, {0, {0}}, 0, 0 }, |
| 432 | { "fr38", 38, {0, {0}}, 0, 0 }, |
| 433 | { "fr39", 39, {0, {0}}, 0, 0 }, |
| 434 | { "fr40", 40, {0, {0}}, 0, 0 }, |
| 435 | { "fr41", 41, {0, {0}}, 0, 0 }, |
| 436 | { "fr42", 42, {0, {0}}, 0, 0 }, |
| 437 | { "fr43", 43, {0, {0}}, 0, 0 }, |
| 438 | { "fr44", 44, {0, {0}}, 0, 0 }, |
| 439 | { "fr45", 45, {0, {0}}, 0, 0 }, |
| 440 | { "fr46", 46, {0, {0}}, 0, 0 }, |
| 441 | { "fr47", 47, {0, {0}}, 0, 0 }, |
| 442 | { "fr48", 48, {0, {0}}, 0, 0 }, |
| 443 | { "fr49", 49, {0, {0}}, 0, 0 }, |
| 444 | { "fr50", 50, {0, {0}}, 0, 0 }, |
| 445 | { "fr51", 51, {0, {0}}, 0, 0 }, |
| 446 | { "fr52", 52, {0, {0}}, 0, 0 }, |
| 447 | { "fr53", 53, {0, {0}}, 0, 0 }, |
| 448 | { "fr54", 54, {0, {0}}, 0, 0 }, |
| 449 | { "fr55", 55, {0, {0}}, 0, 0 }, |
| 450 | { "fr56", 56, {0, {0}}, 0, 0 }, |
| 451 | { "fr57", 57, {0, {0}}, 0, 0 }, |
| 452 | { "fr58", 58, {0, {0}}, 0, 0 }, |
| 453 | { "fr59", 59, {0, {0}}, 0, 0 }, |
| 454 | { "fr60", 60, {0, {0}}, 0, 0 }, |
| 455 | { "fr61", 61, {0, {0}}, 0, 0 }, |
| 456 | { "fr62", 62, {0, {0}}, 0, 0 }, |
| 457 | { "fr63", 63, {0, {0}}, 0, 0 } |
| 458 | }; |
| 459 | |
| 460 | CGEN_KEYWORD sh_cgen_opval_h_fr = |
| 461 | { |
| 462 | & sh_cgen_opval_h_fr_entries[0], |
| 463 | 64, |
| 464 | 0, 0, 0, 0 |
| 465 | }; |
| 466 | |
| 467 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fp_entries[] = |
| 468 | { |
| 469 | { "fp0", 0, {0, {0}}, 0, 0 }, |
| 470 | { "fp1", 1, {0, {0}}, 0, 0 }, |
| 471 | { "fp2", 2, {0, {0}}, 0, 0 }, |
| 472 | { "fp3", 3, {0, {0}}, 0, 0 }, |
| 473 | { "fp4", 4, {0, {0}}, 0, 0 }, |
| 474 | { "fp5", 5, {0, {0}}, 0, 0 }, |
| 475 | { "fp6", 6, {0, {0}}, 0, 0 }, |
| 476 | { "fp7", 7, {0, {0}}, 0, 0 }, |
| 477 | { "fp8", 8, {0, {0}}, 0, 0 }, |
| 478 | { "fp9", 9, {0, {0}}, 0, 0 }, |
| 479 | { "fp10", 10, {0, {0}}, 0, 0 }, |
| 480 | { "fp11", 11, {0, {0}}, 0, 0 }, |
| 481 | { "fp12", 12, {0, {0}}, 0, 0 }, |
| 482 | { "fp13", 13, {0, {0}}, 0, 0 }, |
| 483 | { "fp14", 14, {0, {0}}, 0, 0 }, |
| 484 | { "fp15", 15, {0, {0}}, 0, 0 }, |
| 485 | { "fp16", 16, {0, {0}}, 0, 0 }, |
| 486 | { "fp17", 17, {0, {0}}, 0, 0 }, |
| 487 | { "fp18", 18, {0, {0}}, 0, 0 }, |
| 488 | { "fp19", 19, {0, {0}}, 0, 0 }, |
| 489 | { "fp20", 20, {0, {0}}, 0, 0 }, |
| 490 | { "fp21", 21, {0, {0}}, 0, 0 }, |
| 491 | { "fp22", 22, {0, {0}}, 0, 0 }, |
| 492 | { "fp23", 23, {0, {0}}, 0, 0 }, |
| 493 | { "fp24", 24, {0, {0}}, 0, 0 }, |
| 494 | { "fp25", 25, {0, {0}}, 0, 0 }, |
| 495 | { "fp26", 26, {0, {0}}, 0, 0 }, |
| 496 | { "fp27", 27, {0, {0}}, 0, 0 }, |
| 497 | { "fp28", 28, {0, {0}}, 0, 0 }, |
| 498 | { "fp29", 29, {0, {0}}, 0, 0 }, |
| 499 | { "fp30", 30, {0, {0}}, 0, 0 }, |
| 500 | { "fp31", 31, {0, {0}}, 0, 0 } |
| 501 | }; |
| 502 | |
| 503 | CGEN_KEYWORD sh_cgen_opval_h_fp = |
| 504 | { |
| 505 | & sh_cgen_opval_h_fp_entries[0], |
| 506 | 32, |
| 507 | 0, 0, 0, 0 |
| 508 | }; |
| 509 | |
| 510 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fv_entries[] = |
| 511 | { |
| 512 | { "fv0", 0, {0, {0}}, 0, 0 }, |
| 513 | { "fv1", 1, {0, {0}}, 0, 0 }, |
| 514 | { "fv2", 2, {0, {0}}, 0, 0 }, |
| 515 | { "fv3", 3, {0, {0}}, 0, 0 }, |
| 516 | { "fv4", 4, {0, {0}}, 0, 0 }, |
| 517 | { "fv5", 5, {0, {0}}, 0, 0 }, |
| 518 | { "fv6", 6, {0, {0}}, 0, 0 }, |
| 519 | { "fv7", 7, {0, {0}}, 0, 0 }, |
| 520 | { "fv8", 8, {0, {0}}, 0, 0 }, |
| 521 | { "fv9", 9, {0, {0}}, 0, 0 }, |
| 522 | { "fv10", 10, {0, {0}}, 0, 0 }, |
| 523 | { "fv11", 11, {0, {0}}, 0, 0 }, |
| 524 | { "fv12", 12, {0, {0}}, 0, 0 }, |
| 525 | { "fv13", 13, {0, {0}}, 0, 0 }, |
| 526 | { "fv14", 14, {0, {0}}, 0, 0 }, |
| 527 | { "fv15", 15, {0, {0}}, 0, 0 } |
| 528 | }; |
| 529 | |
| 530 | CGEN_KEYWORD sh_cgen_opval_h_fv = |
| 531 | { |
| 532 | & sh_cgen_opval_h_fv_entries[0], |
| 533 | 16, |
| 534 | 0, 0, 0, 0 |
| 535 | }; |
| 536 | |
| 537 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fmtx_entries[] = |
| 538 | { |
| 539 | { "mtrx0", 0, {0, {0}}, 0, 0 }, |
| 540 | { "mtrx1", 1, {0, {0}}, 0, 0 }, |
| 541 | { "mtrx2", 2, {0, {0}}, 0, 0 }, |
| 542 | { "mtrx3", 3, {0, {0}}, 0, 0 } |
| 543 | }; |
| 544 | |
| 545 | CGEN_KEYWORD sh_cgen_opval_h_fmtx = |
| 546 | { |
| 547 | & sh_cgen_opval_h_fmtx_entries[0], |
| 548 | 4, |
| 549 | 0, 0, 0, 0 |
| 550 | }; |
| 551 | |
| 552 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_dr_entries[] = |
| 553 | { |
| 554 | { "dr0", 0, {0, {0}}, 0, 0 }, |
| 555 | { "dr1", 1, {0, {0}}, 0, 0 }, |
| 556 | { "dr2", 2, {0, {0}}, 0, 0 }, |
| 557 | { "dr3", 3, {0, {0}}, 0, 0 }, |
| 558 | { "dr4", 4, {0, {0}}, 0, 0 }, |
| 559 | { "dr5", 5, {0, {0}}, 0, 0 }, |
| 560 | { "dr6", 6, {0, {0}}, 0, 0 }, |
| 561 | { "dr7", 7, {0, {0}}, 0, 0 }, |
| 562 | { "dr8", 8, {0, {0}}, 0, 0 }, |
| 563 | { "dr9", 9, {0, {0}}, 0, 0 }, |
| 564 | { "dr10", 10, {0, {0}}, 0, 0 }, |
| 565 | { "dr11", 11, {0, {0}}, 0, 0 }, |
| 566 | { "dr12", 12, {0, {0}}, 0, 0 }, |
| 567 | { "dr13", 13, {0, {0}}, 0, 0 }, |
| 568 | { "dr14", 14, {0, {0}}, 0, 0 }, |
| 569 | { "dr15", 15, {0, {0}}, 0, 0 }, |
| 570 | { "dr16", 16, {0, {0}}, 0, 0 }, |
| 571 | { "dr17", 17, {0, {0}}, 0, 0 }, |
| 572 | { "dr18", 18, {0, {0}}, 0, 0 }, |
| 573 | { "dr19", 19, {0, {0}}, 0, 0 }, |
| 574 | { "dr20", 20, {0, {0}}, 0, 0 }, |
| 575 | { "dr21", 21, {0, {0}}, 0, 0 }, |
| 576 | { "dr22", 22, {0, {0}}, 0, 0 }, |
| 577 | { "dr23", 23, {0, {0}}, 0, 0 }, |
| 578 | { "dr24", 24, {0, {0}}, 0, 0 }, |
| 579 | { "dr25", 25, {0, {0}}, 0, 0 }, |
| 580 | { "dr26", 26, {0, {0}}, 0, 0 }, |
| 581 | { "dr27", 27, {0, {0}}, 0, 0 }, |
| 582 | { "dr28", 28, {0, {0}}, 0, 0 }, |
| 583 | { "dr29", 29, {0, {0}}, 0, 0 }, |
| 584 | { "dr30", 30, {0, {0}}, 0, 0 }, |
| 585 | { "dr31", 31, {0, {0}}, 0, 0 }, |
| 586 | { "dr32", 32, {0, {0}}, 0, 0 }, |
| 587 | { "dr33", 33, {0, {0}}, 0, 0 }, |
| 588 | { "dr34", 34, {0, {0}}, 0, 0 }, |
| 589 | { "dr35", 35, {0, {0}}, 0, 0 }, |
| 590 | { "dr36", 36, {0, {0}}, 0, 0 }, |
| 591 | { "dr37", 37, {0, {0}}, 0, 0 }, |
| 592 | { "dr38", 38, {0, {0}}, 0, 0 }, |
| 593 | { "dr39", 39, {0, {0}}, 0, 0 }, |
| 594 | { "dr40", 40, {0, {0}}, 0, 0 }, |
| 595 | { "dr41", 41, {0, {0}}, 0, 0 }, |
| 596 | { "dr42", 42, {0, {0}}, 0, 0 }, |
| 597 | { "dr43", 43, {0, {0}}, 0, 0 }, |
| 598 | { "dr44", 44, {0, {0}}, 0, 0 }, |
| 599 | { "dr45", 45, {0, {0}}, 0, 0 }, |
| 600 | { "dr46", 46, {0, {0}}, 0, 0 }, |
| 601 | { "dr47", 47, {0, {0}}, 0, 0 }, |
| 602 | { "dr48", 48, {0, {0}}, 0, 0 }, |
| 603 | { "dr49", 49, {0, {0}}, 0, 0 }, |
| 604 | { "dr50", 50, {0, {0}}, 0, 0 }, |
| 605 | { "dr51", 51, {0, {0}}, 0, 0 }, |
| 606 | { "dr52", 52, {0, {0}}, 0, 0 }, |
| 607 | { "dr53", 53, {0, {0}}, 0, 0 }, |
| 608 | { "dr54", 54, {0, {0}}, 0, 0 }, |
| 609 | { "dr55", 55, {0, {0}}, 0, 0 }, |
| 610 | { "dr56", 56, {0, {0}}, 0, 0 }, |
| 611 | { "dr57", 57, {0, {0}}, 0, 0 }, |
| 612 | { "dr58", 58, {0, {0}}, 0, 0 }, |
| 613 | { "dr59", 59, {0, {0}}, 0, 0 }, |
| 614 | { "dr60", 60, {0, {0}}, 0, 0 }, |
| 615 | { "dr61", 61, {0, {0}}, 0, 0 }, |
| 616 | { "dr62", 62, {0, {0}}, 0, 0 }, |
| 617 | { "dr63", 63, {0, {0}}, 0, 0 } |
| 618 | }; |
| 619 | |
| 620 | CGEN_KEYWORD sh_cgen_opval_h_dr = |
| 621 | { |
| 622 | & sh_cgen_opval_h_dr_entries[0], |
| 623 | 64, |
| 624 | 0, 0, 0, 0 |
| 625 | }; |
| 626 | |
| 627 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_tr_entries[] = |
| 628 | { |
| 629 | { "tr0", 0, {0, {0}}, 0, 0 }, |
| 630 | { "tr1", 1, {0, {0}}, 0, 0 }, |
| 631 | { "tr2", 2, {0, {0}}, 0, 0 }, |
| 632 | { "tr3", 3, {0, {0}}, 0, 0 }, |
| 633 | { "tr4", 4, {0, {0}}, 0, 0 }, |
| 634 | { "tr5", 5, {0, {0}}, 0, 0 }, |
| 635 | { "tr6", 6, {0, {0}}, 0, 0 }, |
| 636 | { "tr7", 7, {0, {0}}, 0, 0 } |
| 637 | }; |
| 638 | |
| 639 | CGEN_KEYWORD sh_cgen_opval_h_tr = |
| 640 | { |
| 641 | & sh_cgen_opval_h_tr_entries[0], |
| 642 | 8, |
| 643 | 0, 0, 0, 0 |
| 644 | }; |
| 645 | |
| 646 | static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fvc_entries[] = |
| 647 | { |
| 648 | { "fv0", 0, {0, {0}}, 0, 0 }, |
| 649 | { "fv4", 4, {0, {0}}, 0, 0 }, |
| 650 | { "fv8", 8, {0, {0}}, 0, 0 }, |
| 651 | { "fv12", 12, {0, {0}}, 0, 0 } |
| 652 | }; |
| 653 | |
| 654 | CGEN_KEYWORD sh_cgen_opval_h_fvc = |
| 655 | { |
| 656 | & sh_cgen_opval_h_fvc_entries[0], |
| 657 | 4, |
| 658 | 0, 0, 0, 0 |
| 659 | }; |
| 660 | |
| 661 | |
| 662 | /* The hardware table. */ |
| 663 | |
| 664 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 665 | #define A(a) (1 << CGEN_HW_##a) |
| 666 | #else |
| 667 | #define A(a) (1 << CGEN_HW_/**/a) |
| 668 | #endif |
| 669 | |
| 670 | const CGEN_HW_ENTRY sh_cgen_hw_table[] = |
| 671 | { |
| 672 | { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 673 | { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 674 | { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 675 | { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 676 | { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 677 | { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } }, |
| 678 | { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_gr, { 0, { (1<<MACH_BASE) } } }, |
| 679 | { "h-grc", HW_H_GRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_grc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 680 | { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_cr, { 0, { (1<<MACH_BASE) } } }, |
| 681 | { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 682 | { "h-fpscr", HW_H_FPSCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 683 | { "h-frbit", HW_H_FRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 684 | { "h-szbit", HW_H_SZBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 685 | { "h-prbit", HW_H_PRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 686 | { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 687 | { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 688 | { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 689 | { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fr, { 0, { (1<<MACH_BASE) } } }, |
| 690 | { "h-fp", HW_H_FP, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fp, { 0, { (1<<MACH_BASE) } } }, |
| 691 | { "h-fv", HW_H_FV, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fv, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 692 | { "h-fmtx", HW_H_FMTX, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fmtx, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 693 | { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_dr, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 694 | { "h-tr", HW_H_TR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_tr, { 0, { (1<<MACH_BASE) } } }, |
| 695 | { "h-endian", HW_H_ENDIAN, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 696 | { "h-ism", HW_H_ISM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, |
| 697 | { "h-frc", HW_H_FRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 698 | { "h-drc", HW_H_DRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_drc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 699 | { "h-xf", HW_H_XF, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_xf_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 700 | { "h-xd", HW_H_XD, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 701 | { "h-fvc", HW_H_FVC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fvc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 702 | { "h-fpccr", HW_H_FPCCR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 703 | { "h-gbr", HW_H_GBR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 704 | { "h-pr", HW_H_PR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 705 | { "h-macl", HW_H_MACL, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 706 | { "h-mach", HW_H_MACH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 707 | { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
| 708 | { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } |
| 709 | }; |
| 710 | |
| 711 | #undef A |
| 712 | |
| 713 | |
| 714 | /* The instruction field table. */ |
| 715 | |
| 716 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 717 | #define A(a) (1 << CGEN_IFLD_##a) |
| 718 | #else |
| 719 | #define A(a) (1 << CGEN_IFLD_/**/a) |
| 720 | #endif |
| 721 | |
| 722 | const CGEN_IFLD sh_cgen_ifld_table[] = |
| 723 | { |
| 724 | { SH_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 725 | { SH_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 726 | { SH_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 727 | { SH_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 728 | { SH_F_OP16, "f-op16", 0, 16, 15, 16, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 729 | { SH_F_SUB4, "f-sub4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 730 | { SH_F_SUB8, "f-sub8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 731 | { SH_F_SUB10, "f-sub10", 0, 16, 9, 10, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 732 | { SH_F_RN, "f-rn", 0, 16, 11, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 733 | { SH_F_RM, "f-rm", 0, 16, 7, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 734 | { SH_F_8_1, "f-8-1", 0, 16, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 735 | { SH_F_DISP8, "f-disp8", 0, 16, 7, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 736 | { SH_F_DISP12, "f-disp12", 0, 16, 11, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 737 | { SH_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 738 | { SH_F_IMM4, "f-imm4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 739 | { SH_F_IMM4X2, "f-imm4x2", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 740 | { SH_F_IMM4X4, "f-imm4x4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 741 | { SH_F_IMM8X2, "f-imm8x2", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 742 | { SH_F_IMM8X4, "f-imm8x4", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 743 | { SH_F_DN, "f-dn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 744 | { SH_F_DM, "f-dm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 745 | { SH_F_VN, "f-vn", 0, 16, 11, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 746 | { SH_F_VM, "f-vm", 0, 16, 9, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 747 | { SH_F_XN, "f-xn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 748 | { SH_F_XM, "f-xm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 749 | { SH_F_OP, "f-op", 0, 32, 31, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 750 | { SH_F_EXT, "f-ext", 0, 32, 19, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 751 | { SH_F_RSVD, "f-rsvd", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 752 | { SH_F_LEFT, "f-left", 0, 32, 25, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 753 | { SH_F_RIGHT, "f-right", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 754 | { SH_F_DEST, "f-dest", 0, 32, 9, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 755 | { SH_F_TRA, "f-tra", 0, 32, 6, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 756 | { SH_F_TRB, "f-trb", 0, 32, 22, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 757 | { SH_F_LIKELY, "f-likely", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 758 | { SH_F_25, "f-25", 0, 32, 25, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 759 | { SH_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 760 | { SH_F_IMM6, "f-imm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 761 | { SH_F_IMM10, "f-imm10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 762 | { SH_F_IMM16, "f-imm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 763 | { SH_F_UIMM6, "f-uimm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 764 | { SH_F_UIMM16, "f-uimm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 765 | { SH_F_DISP6, "f-disp6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 766 | { SH_F_DISP6X32, "f-disp6x32", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 767 | { SH_F_DISP10, "f-disp10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 768 | { SH_F_DISP10X8, "f-disp10x8", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 769 | { SH_F_DISP10X4, "f-disp10x4", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 770 | { SH_F_DISP10X2, "f-disp10x2", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 771 | { SH_F_DISP16, "f-disp16", 0, 32, 25, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 772 | { 0, 0, 0, 0, 0, 0, {0, {0}} } |
| 773 | }; |
| 774 | |
| 775 | #undef A |
| 776 | |
| 777 | |
| 778 | /* The operand table. */ |
| 779 | |
| 780 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 781 | #define A(a) (1 << CGEN_OPERAND_##a) |
| 782 | #else |
| 783 | #define A(a) (1 << CGEN_OPERAND_/**/a) |
| 784 | #endif |
| 785 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 786 | #define OPERAND(op) SH_OPERAND_##op |
| 787 | #else |
| 788 | #define OPERAND(op) SH_OPERAND_/**/op |
| 789 | #endif |
| 790 | |
| 791 | const CGEN_OPERAND sh_cgen_operand_table[] = |
| 792 | { |
| 793 | /* pc: program counter */ |
| 794 | { "pc", SH_OPERAND_PC, HW_H_PC, 0, 0, |
| 795 | { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 796 | /* endian: Endian mode */ |
| 797 | { "endian", SH_OPERAND_ENDIAN, HW_H_ENDIAN, 0, 0, |
| 798 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } }, |
| 799 | /* ism: Instruction set mode */ |
| 800 | { "ism", SH_OPERAND_ISM, HW_H_ISM, 0, 0, |
| 801 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } }, |
| 802 | /* rm: Left general purpose register */ |
| 803 | { "rm", SH_OPERAND_RM, HW_H_GRC, 7, 4, |
| 804 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 805 | /* rn: Right general purpose register */ |
| 806 | { "rn", SH_OPERAND_RN, HW_H_GRC, 11, 4, |
| 807 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 808 | /* r0: Register 0 */ |
| 809 | { "r0", SH_OPERAND_R0, HW_H_GRC, 0, 0, |
| 810 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 811 | /* frn: Single precision register */ |
| 812 | { "frn", SH_OPERAND_FRN, HW_H_FRC, 11, 4, |
| 813 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 814 | /* frm: Single precision register */ |
| 815 | { "frm", SH_OPERAND_FRM, HW_H_FRC, 7, 4, |
| 816 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 817 | /* fvn: Left floating point vector */ |
| 818 | { "fvn", SH_OPERAND_FVN, HW_H_FVC, 11, 2, |
| 819 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 820 | /* fvm: Right floating point vector */ |
| 821 | { "fvm", SH_OPERAND_FVM, HW_H_FVC, 9, 2, |
| 822 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 823 | /* drn: Left double precision register */ |
| 824 | { "drn", SH_OPERAND_DRN, HW_H_DRC, 11, 3, |
| 825 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 826 | /* drm: Right double precision register */ |
| 827 | { "drm", SH_OPERAND_DRM, HW_H_DRC, 7, 3, |
| 828 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 829 | /* imm4: Immediate value (4 bits) */ |
| 830 | { "imm4", SH_OPERAND_IMM4, HW_H_SINT, 3, 4, |
| 831 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 832 | /* imm8: Immediate value (8 bits) */ |
| 833 | { "imm8", SH_OPERAND_IMM8, HW_H_SINT, 7, 8, |
| 834 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 835 | /* uimm8: Immediate value (8 bits unsigned) */ |
| 836 | { "uimm8", SH_OPERAND_UIMM8, HW_H_UINT, 7, 8, |
| 837 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 838 | /* imm4x2: Immediate value (4 bits, 2x scale) */ |
| 839 | { "imm4x2", SH_OPERAND_IMM4X2, HW_H_UINT, 3, 4, |
| 840 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 841 | /* imm4x4: Immediate value (4 bits, 4x scale) */ |
| 842 | { "imm4x4", SH_OPERAND_IMM4X4, HW_H_UINT, 3, 4, |
| 843 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 844 | /* imm8x2: Immediate value (8 bits, 2x scale) */ |
| 845 | { "imm8x2", SH_OPERAND_IMM8X2, HW_H_UINT, 7, 8, |
| 846 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 847 | /* imm8x4: Immediate value (8 bits, 4x scale) */ |
| 848 | { "imm8x4", SH_OPERAND_IMM8X4, HW_H_UINT, 7, 8, |
| 849 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 850 | /* disp8: Displacement (8 bits) */ |
| 851 | { "disp8", SH_OPERAND_DISP8, HW_H_IADDR, 7, 8, |
| 852 | { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 853 | /* disp12: Displacement (12 bits) */ |
| 854 | { "disp12", SH_OPERAND_DISP12, HW_H_IADDR, 11, 12, |
| 855 | { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 856 | /* rm64: Register m (64 bits) */ |
| 857 | { "rm64", SH_OPERAND_RM64, HW_H_GR, 7, 4, |
| 858 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 859 | /* rn64: Register n (64 bits) */ |
| 860 | { "rn64", SH_OPERAND_RN64, HW_H_GR, 11, 4, |
| 861 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 862 | /* gbr: Global base register */ |
| 863 | { "gbr", SH_OPERAND_GBR, HW_H_GBR, 0, 0, |
| 864 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 865 | /* pr: Procedure link register */ |
| 866 | { "pr", SH_OPERAND_PR, HW_H_PR, 0, 0, |
| 867 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 868 | /* fpscr: Floating point status/control register */ |
| 869 | { "fpscr", SH_OPERAND_FPSCR, HW_H_FPCCR, 0, 0, |
| 870 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 871 | /* tbit: Condition code flag */ |
| 872 | { "tbit", SH_OPERAND_TBIT, HW_H_TBIT, 0, 0, |
| 873 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 874 | /* sbit: Multiply-accumulate saturation flag */ |
| 875 | { "sbit", SH_OPERAND_SBIT, HW_H_SBIT, 0, 0, |
| 876 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 877 | /* mbit: Divide-step M flag */ |
| 878 | { "mbit", SH_OPERAND_MBIT, HW_H_MBIT, 0, 0, |
| 879 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 880 | /* qbit: Divide-step Q flag */ |
| 881 | { "qbit", SH_OPERAND_QBIT, HW_H_QBIT, 0, 0, |
| 882 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 883 | /* fpul: Floating point ??? */ |
| 884 | { "fpul", SH_OPERAND_FPUL, HW_H_FR, 0, 0, |
| 885 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 886 | /* frbit: Floating point register bank bit */ |
| 887 | { "frbit", SH_OPERAND_FRBIT, HW_H_FRBIT, 0, 0, |
| 888 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 889 | /* szbit: Floating point transfer size bit */ |
| 890 | { "szbit", SH_OPERAND_SZBIT, HW_H_SZBIT, 0, 0, |
| 891 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 892 | /* prbit: Floating point precision bit */ |
| 893 | { "prbit", SH_OPERAND_PRBIT, HW_H_PRBIT, 0, 0, |
| 894 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 895 | /* macl: Multiply-accumulate low register */ |
| 896 | { "macl", SH_OPERAND_MACL, HW_H_MACL, 0, 0, |
| 897 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 898 | /* mach: Multiply-accumulate high register */ |
| 899 | { "mach", SH_OPERAND_MACH, HW_H_MACH, 0, 0, |
| 900 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 901 | /* fsdm: bar */ |
| 902 | { "fsdm", SH_OPERAND_FSDM, HW_H_FRC, 7, 4, |
| 903 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 904 | /* fsdn: bar */ |
| 905 | { "fsdn", SH_OPERAND_FSDN, HW_H_FRC, 11, 4, |
| 906 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, |
| 907 | /* rm: Left general purpose reg */ |
| 908 | { "rm", SH_OPERAND_RM, HW_H_GR, 25, 6, |
| 909 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 910 | /* rn: Right general purpose reg */ |
| 911 | { "rn", SH_OPERAND_RN, HW_H_GR, 15, 6, |
| 912 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 913 | /* rd: Destination general purpose reg */ |
| 914 | { "rd", SH_OPERAND_RD, HW_H_GR, 9, 6, |
| 915 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 916 | /* frg: Left single precision register */ |
| 917 | { "frg", SH_OPERAND_FRG, HW_H_FR, 25, 6, |
| 918 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 919 | /* frh: Right single precision register */ |
| 920 | { "frh", SH_OPERAND_FRH, HW_H_FR, 15, 6, |
| 921 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 922 | /* frf: Destination single precision reg */ |
| 923 | { "frf", SH_OPERAND_FRF, HW_H_FR, 9, 6, |
| 924 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 925 | /* frgh: Single precision register pair */ |
| 926 | { "frgh", SH_OPERAND_FRGH, HW_H_FR, 15, 12, |
| 927 | { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 928 | /* fpf: Pair of single precision registers */ |
| 929 | { "fpf", SH_OPERAND_FPF, HW_H_FP, 9, 6, |
| 930 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 931 | /* fvg: Left single precision vector */ |
| 932 | { "fvg", SH_OPERAND_FVG, HW_H_FV, 25, 6, |
| 933 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 934 | /* fvh: Right single precision vector */ |
| 935 | { "fvh", SH_OPERAND_FVH, HW_H_FV, 15, 6, |
| 936 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 937 | /* fvf: Destination single precision vector */ |
| 938 | { "fvf", SH_OPERAND_FVF, HW_H_FV, 9, 6, |
| 939 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 940 | /* mtrxg: Left single precision matrix */ |
| 941 | { "mtrxg", SH_OPERAND_MTRXG, HW_H_FMTX, 25, 6, |
| 942 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 943 | /* drg: Left double precision register */ |
| 944 | { "drg", SH_OPERAND_DRG, HW_H_DR, 25, 6, |
| 945 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 946 | /* drh: Right double precision register */ |
| 947 | { "drh", SH_OPERAND_DRH, HW_H_DR, 15, 6, |
| 948 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 949 | /* drf: Destination double precision reg */ |
| 950 | { "drf", SH_OPERAND_DRF, HW_H_DR, 9, 6, |
| 951 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 952 | /* drgh: Double precision register pair */ |
| 953 | { "drgh", SH_OPERAND_DRGH, HW_H_DR, 15, 12, |
| 954 | { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 955 | /* fpscr: Floating point status register */ |
| 956 | { "fpscr", SH_OPERAND_FPSCR, HW_H_FPSCR, 0, 0, |
| 957 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 958 | /* crj: Control register j */ |
| 959 | { "crj", SH_OPERAND_CRJ, HW_H_CR, 9, 6, |
| 960 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 961 | /* crk: Control register k */ |
| 962 | { "crk", SH_OPERAND_CRK, HW_H_CR, 25, 6, |
| 963 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 964 | /* tra: Target register a */ |
| 965 | { "tra", SH_OPERAND_TRA, HW_H_TR, 6, 3, |
| 966 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 967 | /* trb: Target register b */ |
| 968 | { "trb", SH_OPERAND_TRB, HW_H_TR, 22, 3, |
| 969 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 970 | /* disp6: Displacement (6 bits) */ |
| 971 | { "disp6", SH_OPERAND_DISP6, HW_H_SINT, 15, 6, |
| 972 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 973 | /* disp6x32: Displacement (6 bits, scale 32) */ |
| 974 | { "disp6x32", SH_OPERAND_DISP6X32, HW_H_SINT, 15, 6, |
| 975 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 976 | /* disp10: Displacement (10 bits) */ |
| 977 | { "disp10", SH_OPERAND_DISP10, HW_H_SINT, 19, 10, |
| 978 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 979 | /* disp10x2: Displacement (10 bits, scale 2) */ |
| 980 | { "disp10x2", SH_OPERAND_DISP10X2, HW_H_SINT, 19, 10, |
| 981 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 982 | /* disp10x4: Displacement (10 bits, scale 4) */ |
| 983 | { "disp10x4", SH_OPERAND_DISP10X4, HW_H_SINT, 19, 10, |
| 984 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 985 | /* disp10x8: Displacement (10 bits, scale 8) */ |
| 986 | { "disp10x8", SH_OPERAND_DISP10X8, HW_H_SINT, 19, 10, |
| 987 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 988 | /* disp16: Displacement (16 bits) */ |
| 989 | { "disp16", SH_OPERAND_DISP16, HW_H_SINT, 25, 16, |
| 990 | { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 991 | /* imm6: Immediate (6 bits) */ |
| 992 | { "imm6", SH_OPERAND_IMM6, HW_H_SINT, 15, 6, |
| 993 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 994 | /* imm10: Immediate (10 bits) */ |
| 995 | { "imm10", SH_OPERAND_IMM10, HW_H_SINT, 19, 10, |
| 996 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 997 | /* imm16: Immediate (16 bits) */ |
| 998 | { "imm16", SH_OPERAND_IMM16, HW_H_SINT, 25, 16, |
| 999 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 1000 | /* uimm6: Immediate (6 bits) */ |
| 1001 | { "uimm6", SH_OPERAND_UIMM6, HW_H_UINT, 15, 6, |
| 1002 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 1003 | /* uimm16: Unsigned immediate (16 bits) */ |
| 1004 | { "uimm16", SH_OPERAND_UIMM16, HW_H_UINT, 25, 16, |
| 1005 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 1006 | /* likely: Likely branch? */ |
| 1007 | { "likely", SH_OPERAND_LIKELY, HW_H_UINT, 9, 1, |
| 1008 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, |
| 1009 | { 0, 0, 0, 0, 0, {0, {0}} } |
| 1010 | }; |
| 1011 | |
| 1012 | #undef A |
| 1013 | |
| 1014 | |
| 1015 | /* The instruction table. */ |
| 1016 | |
| 1017 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) |
| 1018 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 1019 | #define A(a) (1 << CGEN_INSN_##a) |
| 1020 | #else |
| 1021 | #define A(a) (1 << CGEN_INSN_/**/a) |
| 1022 | #endif |
| 1023 | |
| 1024 | static const CGEN_IBASE sh_cgen_insn_table[MAX_INSNS] = |
| 1025 | { |
| 1026 | /* Special null first entry. |
| 1027 | A `num' value of zero is thus invalid. |
| 1028 | Also, the special `invalid' insn resides here. */ |
| 1029 | { 0, 0, 0, 0, {0, {0}} }, |
| 1030 | /* add $rm, $rn */ |
| 1031 | { |
| 1032 | SH_INSN_ADD_COMPACT, "add-compact", "add", 16, |
| 1033 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1034 | }, |
| 1035 | /* add #$imm8, $rn */ |
| 1036 | { |
| 1037 | SH_INSN_ADDI_COMPACT, "addi-compact", "add", 16, |
| 1038 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1039 | }, |
| 1040 | /* addc $rm, $rn */ |
| 1041 | { |
| 1042 | SH_INSN_ADDC_COMPACT, "addc-compact", "addc", 16, |
| 1043 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1044 | }, |
| 1045 | /* addv $rm, $rn */ |
| 1046 | { |
| 1047 | SH_INSN_ADDV_COMPACT, "addv-compact", "addv", 16, |
| 1048 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1049 | }, |
| 1050 | /* and $rm64, $rn64 */ |
| 1051 | { |
| 1052 | SH_INSN_AND_COMPACT, "and-compact", "and", 16, |
| 1053 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1054 | }, |
| 1055 | /* and #$uimm8, r0 */ |
| 1056 | { |
| 1057 | SH_INSN_ANDI_COMPACT, "andi-compact", "and", 16, |
| 1058 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1059 | }, |
| 1060 | /* and.b #$imm8, @(r0, gbr) */ |
| 1061 | { |
| 1062 | SH_INSN_ANDB_COMPACT, "andb-compact", "and.b", 16, |
| 1063 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1064 | }, |
| 1065 | /* bf $disp8 */ |
| 1066 | { |
| 1067 | SH_INSN_BF_COMPACT, "bf-compact", "bf", 16, |
| 1068 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1069 | }, |
| 1070 | /* bf/s $disp8 */ |
| 1071 | { |
| 1072 | SH_INSN_BFS_COMPACT, "bfs-compact", "bf/s", 16, |
| 1073 | { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1074 | }, |
| 1075 | /* bra $disp12 */ |
| 1076 | { |
| 1077 | SH_INSN_BRA_COMPACT, "bra-compact", "bra", 16, |
| 1078 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1079 | }, |
| 1080 | /* braf $rn */ |
| 1081 | { |
| 1082 | SH_INSN_BRAF_COMPACT, "braf-compact", "braf", 16, |
| 1083 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1084 | }, |
| 1085 | /* brk */ |
| 1086 | { |
| 1087 | SH_INSN_BRK_COMPACT, "brk-compact", "brk", 16, |
| 1088 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1089 | }, |
| 1090 | /* bsr $disp12 */ |
| 1091 | { |
| 1092 | SH_INSN_BSR_COMPACT, "bsr-compact", "bsr", 16, |
| 1093 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1094 | }, |
| 1095 | /* bsrf $rn */ |
| 1096 | { |
| 1097 | SH_INSN_BSRF_COMPACT, "bsrf-compact", "bsrf", 16, |
| 1098 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1099 | }, |
| 1100 | /* bt $disp8 */ |
| 1101 | { |
| 1102 | SH_INSN_BT_COMPACT, "bt-compact", "bt", 16, |
| 1103 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1104 | }, |
| 1105 | /* bt/s $disp8 */ |
| 1106 | { |
| 1107 | SH_INSN_BTS_COMPACT, "bts-compact", "bt/s", 16, |
| 1108 | { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1109 | }, |
| 1110 | /* clrmac */ |
| 1111 | { |
| 1112 | SH_INSN_CLRMAC_COMPACT, "clrmac-compact", "clrmac", 16, |
| 1113 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1114 | }, |
| 1115 | /* clrs */ |
| 1116 | { |
| 1117 | SH_INSN_CLRS_COMPACT, "clrs-compact", "clrs", 16, |
| 1118 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1119 | }, |
| 1120 | /* clrt */ |
| 1121 | { |
| 1122 | SH_INSN_CLRT_COMPACT, "clrt-compact", "clrt", 16, |
| 1123 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1124 | }, |
| 1125 | /* cmp/eq $rm, $rn */ |
| 1126 | { |
| 1127 | SH_INSN_CMPEQ_COMPACT, "cmpeq-compact", "cmp/eq", 16, |
| 1128 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1129 | }, |
| 1130 | /* cmp/eq #$imm8, r0 */ |
| 1131 | { |
| 1132 | SH_INSN_CMPEQI_COMPACT, "cmpeqi-compact", "cmp/eq", 16, |
| 1133 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1134 | }, |
| 1135 | /* cmp/ge $rm, $rn */ |
| 1136 | { |
| 1137 | SH_INSN_CMPGE_COMPACT, "cmpge-compact", "cmp/ge", 16, |
| 1138 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1139 | }, |
| 1140 | /* cmp/gt $rm, $rn */ |
| 1141 | { |
| 1142 | SH_INSN_CMPGT_COMPACT, "cmpgt-compact", "cmp/gt", 16, |
| 1143 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1144 | }, |
| 1145 | /* cmp/hi $rm, $rn */ |
| 1146 | { |
| 1147 | SH_INSN_CMPHI_COMPACT, "cmphi-compact", "cmp/hi", 16, |
| 1148 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1149 | }, |
| 1150 | /* cmp/hs $rm, $rn */ |
| 1151 | { |
| 1152 | SH_INSN_CMPHS_COMPACT, "cmphs-compact", "cmp/hs", 16, |
| 1153 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1154 | }, |
| 1155 | /* cmp/pl $rn */ |
| 1156 | { |
| 1157 | SH_INSN_CMPPL_COMPACT, "cmppl-compact", "cmp/pl", 16, |
| 1158 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1159 | }, |
| 1160 | /* cmp/pz $rn */ |
| 1161 | { |
| 1162 | SH_INSN_CMPPZ_COMPACT, "cmppz-compact", "cmp/pz", 16, |
| 1163 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1164 | }, |
| 1165 | /* cmp/str $rm, $rn */ |
| 1166 | { |
| 1167 | SH_INSN_CMPSTR_COMPACT, "cmpstr-compact", "cmp/str", 16, |
| 1168 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1169 | }, |
| 1170 | /* div0s $rm, $rn */ |
| 1171 | { |
| 1172 | SH_INSN_DIV0S_COMPACT, "div0s-compact", "div0s", 16, |
| 1173 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1174 | }, |
| 1175 | /* div0u */ |
| 1176 | { |
| 1177 | SH_INSN_DIV0U_COMPACT, "div0u-compact", "div0u", 16, |
| 1178 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1179 | }, |
| 1180 | /* div1 $rm, $rn */ |
| 1181 | { |
| 1182 | SH_INSN_DIV1_COMPACT, "div1-compact", "div1", 16, |
| 1183 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1184 | }, |
| 1185 | /* dmuls.l $rm, $rn */ |
| 1186 | { |
| 1187 | SH_INSN_DMULSL_COMPACT, "dmulsl-compact", "dmuls.l", 16, |
| 1188 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1189 | }, |
| 1190 | /* dmulu.l $rm, $rn */ |
| 1191 | { |
| 1192 | SH_INSN_DMULUL_COMPACT, "dmulul-compact", "dmulu.l", 16, |
| 1193 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1194 | }, |
| 1195 | /* dt $rn */ |
| 1196 | { |
| 1197 | SH_INSN_DT_COMPACT, "dt-compact", "dt", 16, |
| 1198 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1199 | }, |
| 1200 | /* exts.b $rm, $rn */ |
| 1201 | { |
| 1202 | SH_INSN_EXTSB_COMPACT, "extsb-compact", "exts.b", 16, |
| 1203 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1204 | }, |
| 1205 | /* exts.w $rm, $rn */ |
| 1206 | { |
| 1207 | SH_INSN_EXTSW_COMPACT, "extsw-compact", "exts.w", 16, |
| 1208 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1209 | }, |
| 1210 | /* extu.b $rm, $rn */ |
| 1211 | { |
| 1212 | SH_INSN_EXTUB_COMPACT, "extub-compact", "extu.b", 16, |
| 1213 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1214 | }, |
| 1215 | /* extu.w $rm, $rn */ |
| 1216 | { |
| 1217 | SH_INSN_EXTUW_COMPACT, "extuw-compact", "extu.w", 16, |
| 1218 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1219 | }, |
| 1220 | /* fabs $fsdn */ |
| 1221 | { |
| 1222 | SH_INSN_FABS_COMPACT, "fabs-compact", "fabs", 16, |
| 1223 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1224 | }, |
| 1225 | /* fadd $fsdm, $fsdn */ |
| 1226 | { |
| 1227 | SH_INSN_FADD_COMPACT, "fadd-compact", "fadd", 16, |
| 1228 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1229 | }, |
| 1230 | /* fcmp/eq $fsdm, $fsdn */ |
| 1231 | { |
| 1232 | SH_INSN_FCMPEQ_COMPACT, "fcmpeq-compact", "fcmp/eq", 16, |
| 1233 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1234 | }, |
| 1235 | /* fcmp/gt $fsdm, $fsdn */ |
| 1236 | { |
| 1237 | SH_INSN_FCMPGT_COMPACT, "fcmpgt-compact", "fcmp/gt", 16, |
| 1238 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1239 | }, |
| 1240 | /* fcnvds $drn, fpul */ |
| 1241 | { |
| 1242 | SH_INSN_FCNVDS_COMPACT, "fcnvds-compact", "fcnvds", 16, |
| 1243 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1244 | }, |
| 1245 | /* fcnvsd fpul, $drn */ |
| 1246 | { |
| 1247 | SH_INSN_FCNVSD_COMPACT, "fcnvsd-compact", "fcnvsd", 16, |
| 1248 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1249 | }, |
| 1250 | /* fdiv $fsdm, $fsdn */ |
| 1251 | { |
| 1252 | SH_INSN_FDIV_COMPACT, "fdiv-compact", "fdiv", 16, |
| 1253 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1254 | }, |
| 1255 | /* fipr $fvm, $fvn */ |
| 1256 | { |
| 1257 | SH_INSN_FIPR_COMPACT, "fipr-compact", "fipr", 16, |
| 1258 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1259 | }, |
| 1260 | /* flds $frn */ |
| 1261 | { |
| 1262 | SH_INSN_FLDS_COMPACT, "flds-compact", "flds", 16, |
| 1263 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1264 | }, |
| 1265 | /* fldi0 $frn */ |
| 1266 | { |
| 1267 | SH_INSN_FLDI0_COMPACT, "fldi0-compact", "fldi0", 16, |
| 1268 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1269 | }, |
| 1270 | /* fldi1 $frn */ |
| 1271 | { |
| 1272 | SH_INSN_FLDI1_COMPACT, "fldi1-compact", "fldi1", 16, |
| 1273 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1274 | }, |
| 1275 | /* float fpul, $fsdn */ |
| 1276 | { |
| 1277 | SH_INSN_FLOAT_COMPACT, "float-compact", "float", 16, |
| 1278 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1279 | }, |
| 1280 | /* fmac fr0, $frm, $frn */ |
| 1281 | { |
| 1282 | SH_INSN_FMAC_COMPACT, "fmac-compact", "fmac", 16, |
| 1283 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1284 | }, |
| 1285 | /* fmov $frm, $frn */ |
| 1286 | { |
| 1287 | SH_INSN_FMOV1_COMPACT, "fmov1-compact", "fmov", 16, |
| 1288 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1289 | }, |
| 1290 | /* fmov @$rm, $frn */ |
| 1291 | { |
| 1292 | SH_INSN_FMOV2_COMPACT, "fmov2-compact", "fmov", 16, |
| 1293 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1294 | }, |
| 1295 | /* fmov @${rm}+, frn */ |
| 1296 | { |
| 1297 | SH_INSN_FMOV3_COMPACT, "fmov3-compact", "fmov", 16, |
| 1298 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1299 | }, |
| 1300 | /* fmov @(r0, $rm), $frn */ |
| 1301 | { |
| 1302 | SH_INSN_FMOV4_COMPACT, "fmov4-compact", "fmov", 16, |
| 1303 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1304 | }, |
| 1305 | /* fmov $frm, @$rn */ |
| 1306 | { |
| 1307 | SH_INSN_FMOV5_COMPACT, "fmov5-compact", "fmov", 16, |
| 1308 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1309 | }, |
| 1310 | /* fmov $frm, @-$rn */ |
| 1311 | { |
| 1312 | SH_INSN_FMOV6_COMPACT, "fmov6-compact", "fmov", 16, |
| 1313 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1314 | }, |
| 1315 | /* fmov $frm, @(r0, $rn) */ |
| 1316 | { |
| 1317 | SH_INSN_FMOV7_COMPACT, "fmov7-compact", "fmov", 16, |
| 1318 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1319 | }, |
| 1320 | /* fmul $fsdm, $fsdn */ |
| 1321 | { |
| 1322 | SH_INSN_FMUL_COMPACT, "fmul-compact", "fmul", 16, |
| 1323 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1324 | }, |
| 1325 | /* fneg $fsdn */ |
| 1326 | { |
| 1327 | SH_INSN_FNEG_COMPACT, "fneg-compact", "fneg", 16, |
| 1328 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1329 | }, |
| 1330 | /* frchg */ |
| 1331 | { |
| 1332 | SH_INSN_FRCHG_COMPACT, "frchg-compact", "frchg", 16, |
| 1333 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1334 | }, |
| 1335 | /* fschg */ |
| 1336 | { |
| 1337 | SH_INSN_FSCHG_COMPACT, "fschg-compact", "fschg", 16, |
| 1338 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1339 | }, |
| 1340 | /* fsqrt $fsdn */ |
| 1341 | { |
| 1342 | SH_INSN_FSQRT_COMPACT, "fsqrt-compact", "fsqrt", 16, |
| 1343 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1344 | }, |
| 1345 | /* fsts fpul, $frn */ |
| 1346 | { |
| 1347 | SH_INSN_FSTS_COMPACT, "fsts-compact", "fsts", 16, |
| 1348 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1349 | }, |
| 1350 | /* fsub $fsdm, $fsdn */ |
| 1351 | { |
| 1352 | SH_INSN_FSUB_COMPACT, "fsub-compact", "fsub", 16, |
| 1353 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1354 | }, |
| 1355 | /* ftrc $fsdn, fpul */ |
| 1356 | { |
| 1357 | SH_INSN_FTRC_COMPACT, "ftrc-compact", "ftrc", 16, |
| 1358 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1359 | }, |
| 1360 | /* ftrv xmtrx, $fvn */ |
| 1361 | { |
| 1362 | SH_INSN_FTRV_COMPACT, "ftrv-compact", "ftrv", 16, |
| 1363 | { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1364 | }, |
| 1365 | /* jmp @$rn */ |
| 1366 | { |
| 1367 | SH_INSN_JMP_COMPACT, "jmp-compact", "jmp", 16, |
| 1368 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1369 | }, |
| 1370 | /* jsr @$rn */ |
| 1371 | { |
| 1372 | SH_INSN_JSR_COMPACT, "jsr-compact", "jsr", 16, |
| 1373 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1374 | }, |
| 1375 | /* ldc $rn, gbr */ |
| 1376 | { |
| 1377 | SH_INSN_LDC_COMPACT, "ldc-compact", "ldc", 16, |
| 1378 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1379 | }, |
| 1380 | /* ldc.l @${rn}+, gbr */ |
| 1381 | { |
| 1382 | SH_INSN_LDCL_COMPACT, "ldcl-compact", "ldc.l", 16, |
| 1383 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1384 | }, |
| 1385 | /* lds $rn, fpscr */ |
| 1386 | { |
| 1387 | SH_INSN_LDS_FPSCR_COMPACT, "lds-fpscr-compact", "lds", 16, |
| 1388 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1389 | }, |
| 1390 | /* lds.l @${rn}+, fpscr */ |
| 1391 | { |
| 1392 | SH_INSN_LDSL_FPSCR_COMPACT, "ldsl-fpscr-compact", "lds.l", 16, |
| 1393 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1394 | }, |
| 1395 | /* lds $rn, fpul */ |
| 1396 | { |
| 1397 | SH_INSN_LDS_FPUL_COMPACT, "lds-fpul-compact", "lds", 16, |
| 1398 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1399 | }, |
| 1400 | /* lds.l @${rn}+, fpul */ |
| 1401 | { |
| 1402 | SH_INSN_LDSL_FPUL_COMPACT, "ldsl-fpul-compact", "lds.l", 16, |
| 1403 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1404 | }, |
| 1405 | /* lds $rn, mach */ |
| 1406 | { |
| 1407 | SH_INSN_LDS_MACH_COMPACT, "lds-mach-compact", "lds", 16, |
| 1408 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1409 | }, |
| 1410 | /* lds.l @${rn}+, mach */ |
| 1411 | { |
| 1412 | SH_INSN_LDSL_MACH_COMPACT, "ldsl-mach-compact", "lds.l", 16, |
| 1413 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1414 | }, |
| 1415 | /* lds $rn, macl */ |
| 1416 | { |
| 1417 | SH_INSN_LDS_MACL_COMPACT, "lds-macl-compact", "lds", 16, |
| 1418 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1419 | }, |
| 1420 | /* lds.l @${rn}+, macl */ |
| 1421 | { |
| 1422 | SH_INSN_LDSL_MACL_COMPACT, "ldsl-macl-compact", "lds.l", 16, |
| 1423 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1424 | }, |
| 1425 | /* lds $rn, pr */ |
| 1426 | { |
| 1427 | SH_INSN_LDS_PR_COMPACT, "lds-pr-compact", "lds", 16, |
| 1428 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1429 | }, |
| 1430 | /* lds.l @${rn}+, pr */ |
| 1431 | { |
| 1432 | SH_INSN_LDSL_PR_COMPACT, "ldsl-pr-compact", "lds.l", 16, |
| 1433 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1434 | }, |
| 1435 | /* mac.l @${rm}+, @${rn}+ */ |
| 1436 | { |
| 1437 | SH_INSN_MACL_COMPACT, "macl-compact", "mac.l", 16, |
| 1438 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1439 | }, |
| 1440 | /* mac.w @${rm}+, @${rn}+ */ |
| 1441 | { |
| 1442 | SH_INSN_MACW_COMPACT, "macw-compact", "mac.w", 16, |
| 1443 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1444 | }, |
| 1445 | /* mov $rm64, $rn64 */ |
| 1446 | { |
| 1447 | SH_INSN_MOV_COMPACT, "mov-compact", "mov", 16, |
| 1448 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1449 | }, |
| 1450 | /* mov #$imm8, $rn */ |
| 1451 | { |
| 1452 | SH_INSN_MOVI_COMPACT, "movi-compact", "mov", 16, |
| 1453 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1454 | }, |
| 1455 | /* mov.b $rm, @$rn */ |
| 1456 | { |
| 1457 | SH_INSN_MOVB1_COMPACT, "movb1-compact", "mov.b", 16, |
| 1458 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1459 | }, |
| 1460 | /* mov.b $rm, @-$rn */ |
| 1461 | { |
| 1462 | SH_INSN_MOVB2_COMPACT, "movb2-compact", "mov.b", 16, |
| 1463 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1464 | }, |
| 1465 | /* mov.b $rm, @(r0,$rn) */ |
| 1466 | { |
| 1467 | SH_INSN_MOVB3_COMPACT, "movb3-compact", "mov.b", 16, |
| 1468 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1469 | }, |
| 1470 | /* mov.b r0, @($imm8, gbr) */ |
| 1471 | { |
| 1472 | SH_INSN_MOVB4_COMPACT, "movb4-compact", "mov.b", 16, |
| 1473 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1474 | }, |
| 1475 | /* mov.b r0, @($imm4, $rm) */ |
| 1476 | { |
| 1477 | SH_INSN_MOVB5_COMPACT, "movb5-compact", "mov.b", 16, |
| 1478 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1479 | }, |
| 1480 | /* mov.b @$rm, $rn */ |
| 1481 | { |
| 1482 | SH_INSN_MOVB6_COMPACT, "movb6-compact", "mov.b", 16, |
| 1483 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1484 | }, |
| 1485 | /* mov.b @${rm}+, $rn */ |
| 1486 | { |
| 1487 | SH_INSN_MOVB7_COMPACT, "movb7-compact", "mov.b", 16, |
| 1488 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1489 | }, |
| 1490 | /* mov.b @(r0, $rm), $rn */ |
| 1491 | { |
| 1492 | SH_INSN_MOVB8_COMPACT, "movb8-compact", "mov.b", 16, |
| 1493 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1494 | }, |
| 1495 | /* mov.b @($imm8, gbr), r0 */ |
| 1496 | { |
| 1497 | SH_INSN_MOVB9_COMPACT, "movb9-compact", "mov.b", 16, |
| 1498 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1499 | }, |
| 1500 | /* mov.b @($imm4, $rm), r0 */ |
| 1501 | { |
| 1502 | SH_INSN_MOVB10_COMPACT, "movb10-compact", "mov.b", 16, |
| 1503 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1504 | }, |
| 1505 | /* mov.l $rm, @$rn */ |
| 1506 | { |
| 1507 | SH_INSN_MOVL1_COMPACT, "movl1-compact", "mov.l", 16, |
| 1508 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1509 | }, |
| 1510 | /* mov.l $rm, @-$rn */ |
| 1511 | { |
| 1512 | SH_INSN_MOVL2_COMPACT, "movl2-compact", "mov.l", 16, |
| 1513 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1514 | }, |
| 1515 | /* mov.l $rm, @(r0, $rn) */ |
| 1516 | { |
| 1517 | SH_INSN_MOVL3_COMPACT, "movl3-compact", "mov.l", 16, |
| 1518 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1519 | }, |
| 1520 | /* mov.l r0, @($imm8x4, gbr) */ |
| 1521 | { |
| 1522 | SH_INSN_MOVL4_COMPACT, "movl4-compact", "mov.l", 16, |
| 1523 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1524 | }, |
| 1525 | /* mov.l $rm, @($imm4x4, $rn) */ |
| 1526 | { |
| 1527 | SH_INSN_MOVL5_COMPACT, "movl5-compact", "mov.l", 16, |
| 1528 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1529 | }, |
| 1530 | /* mov.l @$rm, $rn */ |
| 1531 | { |
| 1532 | SH_INSN_MOVL6_COMPACT, "movl6-compact", "mov.l", 16, |
| 1533 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1534 | }, |
| 1535 | /* mov.l @${rm}+, $rn */ |
| 1536 | { |
| 1537 | SH_INSN_MOVL7_COMPACT, "movl7-compact", "mov.l", 16, |
| 1538 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1539 | }, |
| 1540 | /* mov.l @(r0, $rm), $rn */ |
| 1541 | { |
| 1542 | SH_INSN_MOVL8_COMPACT, "movl8-compact", "mov.l", 16, |
| 1543 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1544 | }, |
| 1545 | /* mov.l @($imm8x4, gbr), r0 */ |
| 1546 | { |
| 1547 | SH_INSN_MOVL9_COMPACT, "movl9-compact", "mov.l", 16, |
| 1548 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1549 | }, |
| 1550 | /* mov.l @($imm8x4, pc), $rn */ |
| 1551 | { |
| 1552 | SH_INSN_MOVL10_COMPACT, "movl10-compact", "mov.l", 16, |
| 1553 | { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1554 | }, |
| 1555 | /* mov.l @($imm4x4, $rm), $rn */ |
| 1556 | { |
| 1557 | SH_INSN_MOVL11_COMPACT, "movl11-compact", "mov.l", 16, |
| 1558 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1559 | }, |
| 1560 | /* mov.w $rm, @$rn */ |
| 1561 | { |
| 1562 | SH_INSN_MOVW1_COMPACT, "movw1-compact", "mov.w", 16, |
| 1563 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1564 | }, |
| 1565 | /* mov.w $rm, @-$rn */ |
| 1566 | { |
| 1567 | SH_INSN_MOVW2_COMPACT, "movw2-compact", "mov.w", 16, |
| 1568 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1569 | }, |
| 1570 | /* mov.w $rm, @(r0, $rn) */ |
| 1571 | { |
| 1572 | SH_INSN_MOVW3_COMPACT, "movw3-compact", "mov.w", 16, |
| 1573 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1574 | }, |
| 1575 | /* mov.w r0, @($imm8x2, gbr) */ |
| 1576 | { |
| 1577 | SH_INSN_MOVW4_COMPACT, "movw4-compact", "mov.w", 16, |
| 1578 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1579 | }, |
| 1580 | /* mov.w r0, @($imm4x2, $rn) */ |
| 1581 | { |
| 1582 | SH_INSN_MOVW5_COMPACT, "movw5-compact", "mov.w", 16, |
| 1583 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1584 | }, |
| 1585 | /* mov.w @$rm, $rn */ |
| 1586 | { |
| 1587 | SH_INSN_MOVW6_COMPACT, "movw6-compact", "mov.w", 16, |
| 1588 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1589 | }, |
| 1590 | /* mov.w @${rm}+, $rn */ |
| 1591 | { |
| 1592 | SH_INSN_MOVW7_COMPACT, "movw7-compact", "mov.w", 16, |
| 1593 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1594 | }, |
| 1595 | /* mov.w @(r0, $rm), $rn */ |
| 1596 | { |
| 1597 | SH_INSN_MOVW8_COMPACT, "movw8-compact", "mov.w", 16, |
| 1598 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1599 | }, |
| 1600 | /* mov.w @($imm8x2, gbr), r0 */ |
| 1601 | { |
| 1602 | SH_INSN_MOVW9_COMPACT, "movw9-compact", "mov.w", 16, |
| 1603 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1604 | }, |
| 1605 | /* mov.w @($imm8x2, pc), $rn */ |
| 1606 | { |
| 1607 | SH_INSN_MOVW10_COMPACT, "movw10-compact", "mov.w", 16, |
| 1608 | { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1609 | }, |
| 1610 | /* mov.w @($imm4x2, $rm), r0 */ |
| 1611 | { |
| 1612 | SH_INSN_MOVW11_COMPACT, "movw11-compact", "mov.w", 16, |
| 1613 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1614 | }, |
| 1615 | /* mova @($imm8x4, pc), r0 */ |
| 1616 | { |
| 1617 | SH_INSN_MOVA_COMPACT, "mova-compact", "mova", 16, |
| 1618 | { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1619 | }, |
| 1620 | /* movca.l r0, @$rn */ |
| 1621 | { |
| 1622 | SH_INSN_MOVCAL_COMPACT, "movcal-compact", "movca.l", 16, |
| 1623 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1624 | }, |
| 1625 | /* movt $rn */ |
| 1626 | { |
| 1627 | SH_INSN_MOVT_COMPACT, "movt-compact", "movt", 16, |
| 1628 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1629 | }, |
| 1630 | /* mul.l $rm, $rn */ |
| 1631 | { |
| 1632 | SH_INSN_MULL_COMPACT, "mull-compact", "mul.l", 16, |
| 1633 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1634 | }, |
| 1635 | /* muls.w $rm, $rn */ |
| 1636 | { |
| 1637 | SH_INSN_MULSW_COMPACT, "mulsw-compact", "muls.w", 16, |
| 1638 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1639 | }, |
| 1640 | /* mulu.w $rm, $rn */ |
| 1641 | { |
| 1642 | SH_INSN_MULUW_COMPACT, "muluw-compact", "mulu.w", 16, |
| 1643 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1644 | }, |
| 1645 | /* neg $rm, $rn */ |
| 1646 | { |
| 1647 | SH_INSN_NEG_COMPACT, "neg-compact", "neg", 16, |
| 1648 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1649 | }, |
| 1650 | /* negc $rm, $rn */ |
| 1651 | { |
| 1652 | SH_INSN_NEGC_COMPACT, "negc-compact", "negc", 16, |
| 1653 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1654 | }, |
| 1655 | /* nop */ |
| 1656 | { |
| 1657 | SH_INSN_NOP_COMPACT, "nop-compact", "nop", 16, |
| 1658 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1659 | }, |
| 1660 | /* not $rm64, $rn64 */ |
| 1661 | { |
| 1662 | SH_INSN_NOT_COMPACT, "not-compact", "not", 16, |
| 1663 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1664 | }, |
| 1665 | /* ocbi @$rn */ |
| 1666 | { |
| 1667 | SH_INSN_OCBI_COMPACT, "ocbi-compact", "ocbi", 16, |
| 1668 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1669 | }, |
| 1670 | /* ocbp @$rn */ |
| 1671 | { |
| 1672 | SH_INSN_OCBP_COMPACT, "ocbp-compact", "ocbp", 16, |
| 1673 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1674 | }, |
| 1675 | /* ocbwb @$rn */ |
| 1676 | { |
| 1677 | SH_INSN_OCBWB_COMPACT, "ocbwb-compact", "ocbwb", 16, |
| 1678 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1679 | }, |
| 1680 | /* or $rm64, $rn64 */ |
| 1681 | { |
| 1682 | SH_INSN_OR_COMPACT, "or-compact", "or", 16, |
| 1683 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1684 | }, |
| 1685 | /* or #$uimm8, r0 */ |
| 1686 | { |
| 1687 | SH_INSN_ORI_COMPACT, "ori-compact", "or", 16, |
| 1688 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1689 | }, |
| 1690 | /* or.b #$imm8, @(r0, gbr) */ |
| 1691 | { |
| 1692 | SH_INSN_ORB_COMPACT, "orb-compact", "or.b", 16, |
| 1693 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1694 | }, |
| 1695 | /* pref @$rn */ |
| 1696 | { |
| 1697 | SH_INSN_PREF_COMPACT, "pref-compact", "pref", 16, |
| 1698 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1699 | }, |
| 1700 | /* rotcl $rn */ |
| 1701 | { |
| 1702 | SH_INSN_ROTCL_COMPACT, "rotcl-compact", "rotcl", 16, |
| 1703 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1704 | }, |
| 1705 | /* rotcr $rn */ |
| 1706 | { |
| 1707 | SH_INSN_ROTCR_COMPACT, "rotcr-compact", "rotcr", 16, |
| 1708 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1709 | }, |
| 1710 | /* rotl $rn */ |
| 1711 | { |
| 1712 | SH_INSN_ROTL_COMPACT, "rotl-compact", "rotl", 16, |
| 1713 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1714 | }, |
| 1715 | /* rotr $rn */ |
| 1716 | { |
| 1717 | SH_INSN_ROTR_COMPACT, "rotr-compact", "rotr", 16, |
| 1718 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1719 | }, |
| 1720 | /* rts */ |
| 1721 | { |
| 1722 | SH_INSN_RTS_COMPACT, "rts-compact", "rts", 16, |
| 1723 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1724 | }, |
| 1725 | /* sets */ |
| 1726 | { |
| 1727 | SH_INSN_SETS_COMPACT, "sets-compact", "sets", 16, |
| 1728 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1729 | }, |
| 1730 | /* sett */ |
| 1731 | { |
| 1732 | SH_INSN_SETT_COMPACT, "sett-compact", "sett", 16, |
| 1733 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1734 | }, |
| 1735 | /* shad $rm, $rn */ |
| 1736 | { |
| 1737 | SH_INSN_SHAD_COMPACT, "shad-compact", "shad", 16, |
| 1738 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1739 | }, |
| 1740 | /* shal $rn */ |
| 1741 | { |
| 1742 | SH_INSN_SHAL_COMPACT, "shal-compact", "shal", 16, |
| 1743 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1744 | }, |
| 1745 | /* shar $rn */ |
| 1746 | { |
| 1747 | SH_INSN_SHAR_COMPACT, "shar-compact", "shar", 16, |
| 1748 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1749 | }, |
| 1750 | /* shld $rm, $rn */ |
| 1751 | { |
| 1752 | SH_INSN_SHLD_COMPACT, "shld-compact", "shld", 16, |
| 1753 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1754 | }, |
| 1755 | /* shll $rn */ |
| 1756 | { |
| 1757 | SH_INSN_SHLL_COMPACT, "shll-compact", "shll", 16, |
| 1758 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1759 | }, |
| 1760 | /* shll2 $rn */ |
| 1761 | { |
| 1762 | SH_INSN_SHLL2_COMPACT, "shll2-compact", "shll2", 16, |
| 1763 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1764 | }, |
| 1765 | /* shll8 $rn */ |
| 1766 | { |
| 1767 | SH_INSN_SHLL8_COMPACT, "shll8-compact", "shll8", 16, |
| 1768 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1769 | }, |
| 1770 | /* shll16 $rn */ |
| 1771 | { |
| 1772 | SH_INSN_SHLL16_COMPACT, "shll16-compact", "shll16", 16, |
| 1773 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1774 | }, |
| 1775 | /* shlr $rn */ |
| 1776 | { |
| 1777 | SH_INSN_SHLR_COMPACT, "shlr-compact", "shlr", 16, |
| 1778 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1779 | }, |
| 1780 | /* shlr2 $rn */ |
| 1781 | { |
| 1782 | SH_INSN_SHLR2_COMPACT, "shlr2-compact", "shlr2", 16, |
| 1783 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1784 | }, |
| 1785 | /* shlr8 $rn */ |
| 1786 | { |
| 1787 | SH_INSN_SHLR8_COMPACT, "shlr8-compact", "shlr8", 16, |
| 1788 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1789 | }, |
| 1790 | /* shlr16 $rn */ |
| 1791 | { |
| 1792 | SH_INSN_SHLR16_COMPACT, "shlr16-compact", "shlr16", 16, |
| 1793 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1794 | }, |
| 1795 | /* stc gbr, $rn */ |
| 1796 | { |
| 1797 | SH_INSN_STC_GBR_COMPACT, "stc-gbr-compact", "stc", 16, |
| 1798 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1799 | }, |
| 1800 | /* stc.l gbr, @-$rn */ |
| 1801 | { |
| 1802 | SH_INSN_STCL_GBR_COMPACT, "stcl-gbr-compact", "stc.l", 16, |
| 1803 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1804 | }, |
| 1805 | /* sts fpscr, $rn */ |
| 1806 | { |
| 1807 | SH_INSN_STS_FPSCR_COMPACT, "sts-fpscr-compact", "sts", 16, |
| 1808 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1809 | }, |
| 1810 | /* sts.l fpscr, @-$rn */ |
| 1811 | { |
| 1812 | SH_INSN_STSL_FPSCR_COMPACT, "stsl-fpscr-compact", "sts.l", 16, |
| 1813 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1814 | }, |
| 1815 | /* sts fpul, $rn */ |
| 1816 | { |
| 1817 | SH_INSN_STS_FPUL_COMPACT, "sts-fpul-compact", "sts", 16, |
| 1818 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1819 | }, |
| 1820 | /* sts.l fpul, @-$rn */ |
| 1821 | { |
| 1822 | SH_INSN_STSL_FPUL_COMPACT, "stsl-fpul-compact", "sts.l", 16, |
| 1823 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1824 | }, |
| 1825 | /* sts mach, $rn */ |
| 1826 | { |
| 1827 | SH_INSN_STS_MACH_COMPACT, "sts-mach-compact", "sts", 16, |
| 1828 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1829 | }, |
| 1830 | /* sts.l mach, @-$rn */ |
| 1831 | { |
| 1832 | SH_INSN_STSL_MACH_COMPACT, "stsl-mach-compact", "sts.l", 16, |
| 1833 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1834 | }, |
| 1835 | /* sts macl, $rn */ |
| 1836 | { |
| 1837 | SH_INSN_STS_MACL_COMPACT, "sts-macl-compact", "sts", 16, |
| 1838 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1839 | }, |
| 1840 | /* sts.l macl, @-$rn */ |
| 1841 | { |
| 1842 | SH_INSN_STSL_MACL_COMPACT, "stsl-macl-compact", "sts.l", 16, |
| 1843 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1844 | }, |
| 1845 | /* sts pr, $rn */ |
| 1846 | { |
| 1847 | SH_INSN_STS_PR_COMPACT, "sts-pr-compact", "sts", 16, |
| 1848 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1849 | }, |
| 1850 | /* sts.l pr, @-$rn */ |
| 1851 | { |
| 1852 | SH_INSN_STSL_PR_COMPACT, "stsl-pr-compact", "sts.l", 16, |
| 1853 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1854 | }, |
| 1855 | /* sub $rm, $rn */ |
| 1856 | { |
| 1857 | SH_INSN_SUB_COMPACT, "sub-compact", "sub", 16, |
| 1858 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1859 | }, |
| 1860 | /* subc $rm, $rn */ |
| 1861 | { |
| 1862 | SH_INSN_SUBC_COMPACT, "subc-compact", "subc", 16, |
| 1863 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1864 | }, |
| 1865 | /* subv $rm, $rn */ |
| 1866 | { |
| 1867 | SH_INSN_SUBV_COMPACT, "subv-compact", "subv", 16, |
| 1868 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1869 | }, |
| 1870 | /* swap.b $rm, $rn */ |
| 1871 | { |
| 1872 | SH_INSN_SWAPB_COMPACT, "swapb-compact", "swap.b", 16, |
| 1873 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1874 | }, |
| 1875 | /* swap.w $rm, $rn */ |
| 1876 | { |
| 1877 | SH_INSN_SWAPW_COMPACT, "swapw-compact", "swap.w", 16, |
| 1878 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1879 | }, |
| 1880 | /* tas.b @$rn */ |
| 1881 | { |
| 1882 | SH_INSN_TASB_COMPACT, "tasb-compact", "tas.b", 16, |
| 1883 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1884 | }, |
| 1885 | /* trapa #$uimm8 */ |
| 1886 | { |
| 1887 | SH_INSN_TRAPA_COMPACT, "trapa-compact", "trapa", 16, |
| 1888 | { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1889 | }, |
| 1890 | /* tst $rm, $rn */ |
| 1891 | { |
| 1892 | SH_INSN_TST_COMPACT, "tst-compact", "tst", 16, |
| 1893 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1894 | }, |
| 1895 | /* tst #$uimm8, r0 */ |
| 1896 | { |
| 1897 | SH_INSN_TSTI_COMPACT, "tsti-compact", "tst", 16, |
| 1898 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1899 | }, |
| 1900 | /* tst.b #$imm8, @(r0, gbr) */ |
| 1901 | { |
| 1902 | SH_INSN_TSTB_COMPACT, "tstb-compact", "tst.b", 16, |
| 1903 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1904 | }, |
| 1905 | /* xor $rm64, $rn64 */ |
| 1906 | { |
| 1907 | SH_INSN_XOR_COMPACT, "xor-compact", "xor", 16, |
| 1908 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1909 | }, |
| 1910 | /* xor #$uimm8, r0 */ |
| 1911 | { |
| 1912 | SH_INSN_XORI_COMPACT, "xori-compact", "xor", 16, |
| 1913 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1914 | }, |
| 1915 | /* xor.b #$imm8, @(r0, gbr) */ |
| 1916 | { |
| 1917 | SH_INSN_XORB_COMPACT, "xorb-compact", "xor.b", 16, |
| 1918 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1919 | }, |
| 1920 | /* xtrct $rm, $rn */ |
| 1921 | { |
| 1922 | SH_INSN_XTRCT_COMPACT, "xtrct-compact", "xtrct", 16, |
| 1923 | { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } |
| 1924 | }, |
| 1925 | /* add $rm, $rn, $rd */ |
| 1926 | { |
| 1927 | SH_INSN_ADD, "add", "add", 32, |
| 1928 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1929 | }, |
| 1930 | /* add.l $rm, $rn, $rd */ |
| 1931 | { |
| 1932 | SH_INSN_ADDL, "addl", "add.l", 32, |
| 1933 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1934 | }, |
| 1935 | /* addi $rm, $disp10, $rd */ |
| 1936 | { |
| 1937 | SH_INSN_ADDI, "addi", "addi", 32, |
| 1938 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1939 | }, |
| 1940 | /* addi.l $rm, $disp10, $rd */ |
| 1941 | { |
| 1942 | SH_INSN_ADDIL, "addil", "addi.l", 32, |
| 1943 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1944 | }, |
| 1945 | /* addz.l $rm, $rn, $rd */ |
| 1946 | { |
| 1947 | SH_INSN_ADDZL, "addzl", "addz.l", 32, |
| 1948 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1949 | }, |
| 1950 | /* alloco $rm, $disp6x32 */ |
| 1951 | { |
| 1952 | SH_INSN_ALLOCO, "alloco", "alloco", 32, |
| 1953 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1954 | }, |
| 1955 | /* and $rm, $rn, $rd */ |
| 1956 | { |
| 1957 | SH_INSN_AND, "and", "and", 32, |
| 1958 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1959 | }, |
| 1960 | /* andc $rm, $rn, $rd */ |
| 1961 | { |
| 1962 | SH_INSN_ANDC, "andc", "andc", 32, |
| 1963 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1964 | }, |
| 1965 | /* andi $rm, $disp10, $rd */ |
| 1966 | { |
| 1967 | SH_INSN_ANDI, "andi", "andi", 32, |
| 1968 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1969 | }, |
| 1970 | /* beq$likely $rm, $rn, $tra */ |
| 1971 | { |
| 1972 | SH_INSN_BEQ, "beq", "beq", 32, |
| 1973 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1974 | }, |
| 1975 | /* beqi$likely $rm, $imm6, $tra */ |
| 1976 | { |
| 1977 | SH_INSN_BEQI, "beqi", "beqi", 32, |
| 1978 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1979 | }, |
| 1980 | /* bge$likely $rm, $rn, $tra */ |
| 1981 | { |
| 1982 | SH_INSN_BGE, "bge", "bge", 32, |
| 1983 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1984 | }, |
| 1985 | /* bgeu$likely $rm, $rn, $tra */ |
| 1986 | { |
| 1987 | SH_INSN_BGEU, "bgeu", "bgeu", 32, |
| 1988 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1989 | }, |
| 1990 | /* bgt$likely $rm, $rn, $tra */ |
| 1991 | { |
| 1992 | SH_INSN_BGT, "bgt", "bgt", 32, |
| 1993 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1994 | }, |
| 1995 | /* bgtu$likely $rm, $rn, $tra */ |
| 1996 | { |
| 1997 | SH_INSN_BGTU, "bgtu", "bgtu", 32, |
| 1998 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 1999 | }, |
| 2000 | /* blink $trb, $rd */ |
| 2001 | { |
| 2002 | SH_INSN_BLINK, "blink", "blink", 32, |
| 2003 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2004 | }, |
| 2005 | /* bne$likely $rm, $rn, $tra */ |
| 2006 | { |
| 2007 | SH_INSN_BNE, "bne", "bne", 32, |
| 2008 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2009 | }, |
| 2010 | /* bnei$likely $rm, $imm6, $tra */ |
| 2011 | { |
| 2012 | SH_INSN_BNEI, "bnei", "bnei", 32, |
| 2013 | { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2014 | }, |
| 2015 | /* brk */ |
| 2016 | { |
| 2017 | SH_INSN_BRK, "brk", "brk", 32, |
| 2018 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2019 | }, |
| 2020 | /* byterev $rm, $rd */ |
| 2021 | { |
| 2022 | SH_INSN_BYTEREV, "byterev", "byterev", 32, |
| 2023 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2024 | }, |
| 2025 | /* cmpeq $rm, $rn, $rd */ |
| 2026 | { |
| 2027 | SH_INSN_CMPEQ, "cmpeq", "cmpeq", 32, |
| 2028 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2029 | }, |
| 2030 | /* cmpgt $rm, $rn, $rd */ |
| 2031 | { |
| 2032 | SH_INSN_CMPGT, "cmpgt", "cmpgt", 32, |
| 2033 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2034 | }, |
| 2035 | /* cmpgtu $rm,$rn, $rd */ |
| 2036 | { |
| 2037 | SH_INSN_CMPGTU, "cmpgtu", "cmpgtu", 32, |
| 2038 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2039 | }, |
| 2040 | /* cmveq $rm, $rn, $rd */ |
| 2041 | { |
| 2042 | SH_INSN_CMVEQ, "cmveq", "cmveq", 32, |
| 2043 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2044 | }, |
| 2045 | /* cmvne $rm, $rn, $rd */ |
| 2046 | { |
| 2047 | SH_INSN_CMVNE, "cmvne", "cmvne", 32, |
| 2048 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2049 | }, |
| 2050 | /* fabs.d $drgh, $drf */ |
| 2051 | { |
| 2052 | SH_INSN_FABSD, "fabsd", "fabs.d", 32, |
| 2053 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2054 | }, |
| 2055 | /* fabs.s $frgh, $frf */ |
| 2056 | { |
| 2057 | SH_INSN_FABSS, "fabss", "fabs.s", 32, |
| 2058 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2059 | }, |
| 2060 | /* fadd.d $drg, $drh, $drf */ |
| 2061 | { |
| 2062 | SH_INSN_FADDD, "faddd", "fadd.d", 32, |
| 2063 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2064 | }, |
| 2065 | /* fadd.s $frg, $frh, $frf */ |
| 2066 | { |
| 2067 | SH_INSN_FADDS, "fadds", "fadd.s", 32, |
| 2068 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2069 | }, |
| 2070 | /* fcmpeq.d $drg, $drh, $rd */ |
| 2071 | { |
| 2072 | SH_INSN_FCMPEQD, "fcmpeqd", "fcmpeq.d", 32, |
| 2073 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2074 | }, |
| 2075 | /* fcmpeq.s $frg, $frh, $rd */ |
| 2076 | { |
| 2077 | SH_INSN_FCMPEQS, "fcmpeqs", "fcmpeq.s", 32, |
| 2078 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2079 | }, |
| 2080 | /* fcmpge.d $drg, $drh, $rd */ |
| 2081 | { |
| 2082 | SH_INSN_FCMPGED, "fcmpged", "fcmpge.d", 32, |
| 2083 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2084 | }, |
| 2085 | /* fcmpge.s $frg, $frh, $rd */ |
| 2086 | { |
| 2087 | SH_INSN_FCMPGES, "fcmpges", "fcmpge.s", 32, |
| 2088 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2089 | }, |
| 2090 | /* fcmpgt.d $drg, $drh, $rd */ |
| 2091 | { |
| 2092 | SH_INSN_FCMPGTD, "fcmpgtd", "fcmpgt.d", 32, |
| 2093 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2094 | }, |
| 2095 | /* fcmpgt.s $frg, $frh, $rd */ |
| 2096 | { |
| 2097 | SH_INSN_FCMPGTS, "fcmpgts", "fcmpgt.s", 32, |
| 2098 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2099 | }, |
| 2100 | /* fcmpun.d $drg, $drh, $rd */ |
| 2101 | { |
| 2102 | SH_INSN_FCMPUND, "fcmpund", "fcmpun.d", 32, |
| 2103 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2104 | }, |
| 2105 | /* fcmpun.s $frg, $frh, $rd */ |
| 2106 | { |
| 2107 | SH_INSN_FCMPUNS, "fcmpuns", "fcmpun.s", 32, |
| 2108 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2109 | }, |
| 2110 | /* fcnv.ds $drgh, $frf */ |
| 2111 | { |
| 2112 | SH_INSN_FCNVDS, "fcnvds", "fcnv.ds", 32, |
| 2113 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2114 | }, |
| 2115 | /* fcnv.sd $frgh, $drf */ |
| 2116 | { |
| 2117 | SH_INSN_FCNVSD, "fcnvsd", "fcnv.sd", 32, |
| 2118 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2119 | }, |
| 2120 | /* fdiv.d $drg, $drh, $drf */ |
| 2121 | { |
| 2122 | SH_INSN_FDIVD, "fdivd", "fdiv.d", 32, |
| 2123 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2124 | }, |
| 2125 | /* fdiv.s $frg, $frh, $frf */ |
| 2126 | { |
| 2127 | SH_INSN_FDIVS, "fdivs", "fdiv.s", 32, |
| 2128 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2129 | }, |
| 2130 | /* fgetscr $frf */ |
| 2131 | { |
| 2132 | SH_INSN_FGETSCR, "fgetscr", "fgetscr", 32, |
| 2133 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2134 | }, |
| 2135 | /* fipr.s $fvg, $fvh, $frf */ |
| 2136 | { |
| 2137 | SH_INSN_FIPRS, "fiprs", "fipr.s", 32, |
| 2138 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2139 | }, |
| 2140 | /* fld.d $rm, $disp10x8, $drf */ |
| 2141 | { |
| 2142 | SH_INSN_FLDD, "fldd", "fld.d", 32, |
| 2143 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2144 | }, |
| 2145 | /* fld.p $rm, $disp10x8, $fpf */ |
| 2146 | { |
| 2147 | SH_INSN_FLDP, "fldp", "fld.p", 32, |
| 2148 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2149 | }, |
| 2150 | /* fld.s $rm, $disp10x4, $frf */ |
| 2151 | { |
| 2152 | SH_INSN_FLDS, "flds", "fld.s", 32, |
| 2153 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2154 | }, |
| 2155 | /* fldx.d $rm, $rn, $drf */ |
| 2156 | { |
| 2157 | SH_INSN_FLDXD, "fldxd", "fldx.d", 32, |
| 2158 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2159 | }, |
| 2160 | /* fldx.p $rm, $rn, $fpf */ |
| 2161 | { |
| 2162 | SH_INSN_FLDXP, "fldxp", "fldx.p", 32, |
| 2163 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2164 | }, |
| 2165 | /* fldx.s $rm, $rn, $frf */ |
| 2166 | { |
| 2167 | SH_INSN_FLDXS, "fldxs", "fldx.s", 32, |
| 2168 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2169 | }, |
| 2170 | /* float.ld $frgh, $drf */ |
| 2171 | { |
| 2172 | SH_INSN_FLOATLD, "floatld", "float.ld", 32, |
| 2173 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2174 | }, |
| 2175 | /* float.ls $frgh, $frf */ |
| 2176 | { |
| 2177 | SH_INSN_FLOATLS, "floatls", "float.ls", 32, |
| 2178 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2179 | }, |
| 2180 | /* float.qd $drgh, $drf */ |
| 2181 | { |
| 2182 | SH_INSN_FLOATQD, "floatqd", "float.qd", 32, |
| 2183 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2184 | }, |
| 2185 | /* float.qs $drgh, $frf */ |
| 2186 | { |
| 2187 | SH_INSN_FLOATQS, "floatqs", "float.qs", 32, |
| 2188 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2189 | }, |
| 2190 | /* fmac.s $frg, $frh, $frf */ |
| 2191 | { |
| 2192 | SH_INSN_FMACS, "fmacs", "fmac.s", 32, |
| 2193 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2194 | }, |
| 2195 | /* fmov.d $drgh, $drf */ |
| 2196 | { |
| 2197 | SH_INSN_FMOVD, "fmovd", "fmov.d", 32, |
| 2198 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2199 | }, |
| 2200 | /* fmov.dq $drgh, $rd */ |
| 2201 | { |
| 2202 | SH_INSN_FMOVDQ, "fmovdq", "fmov.dq", 32, |
| 2203 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2204 | }, |
| 2205 | /* fmov.ls $rm, $frf */ |
| 2206 | { |
| 2207 | SH_INSN_FMOVLS, "fmovls", "fmov.ls", 32, |
| 2208 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2209 | }, |
| 2210 | /* fmov.qd $rm, $drf */ |
| 2211 | { |
| 2212 | SH_INSN_FMOVQD, "fmovqd", "fmov.qd", 32, |
| 2213 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2214 | }, |
| 2215 | /* fmov.s $frgh, $frf */ |
| 2216 | { |
| 2217 | SH_INSN_FMOVS, "fmovs", "fmov.s", 32, |
| 2218 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2219 | }, |
| 2220 | /* fmov.sl $frgh, $rd */ |
| 2221 | { |
| 2222 | SH_INSN_FMOVSL, "fmovsl", "fmov.sl", 32, |
| 2223 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2224 | }, |
| 2225 | /* fmul.d $drg, $drh, $drf */ |
| 2226 | { |
| 2227 | SH_INSN_FMULD, "fmuld", "fmul.d", 32, |
| 2228 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2229 | }, |
| 2230 | /* fmul.s $frg, $frh, $frf */ |
| 2231 | { |
| 2232 | SH_INSN_FMULS, "fmuls", "fmul.s", 32, |
| 2233 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2234 | }, |
| 2235 | /* fneg.d $drgh, $drf */ |
| 2236 | { |
| 2237 | SH_INSN_FNEGD, "fnegd", "fneg.d", 32, |
| 2238 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2239 | }, |
| 2240 | /* fneg.s $frgh, $frf */ |
| 2241 | { |
| 2242 | SH_INSN_FNEGS, "fnegs", "fneg.s", 32, |
| 2243 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2244 | }, |
| 2245 | /* fputscr $frgh */ |
| 2246 | { |
| 2247 | SH_INSN_FPUTSCR, "fputscr", "fputscr", 32, |
| 2248 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2249 | }, |
| 2250 | /* fsqrt.d $drgh, $drf */ |
| 2251 | { |
| 2252 | SH_INSN_FSQRTD, "fsqrtd", "fsqrt.d", 32, |
| 2253 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2254 | }, |
| 2255 | /* fsqrt.s $frgh, $frf */ |
| 2256 | { |
| 2257 | SH_INSN_FSQRTS, "fsqrts", "fsqrt.s", 32, |
| 2258 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2259 | }, |
| 2260 | /* fst.d $rm, $disp10x8, $drf */ |
| 2261 | { |
| 2262 | SH_INSN_FSTD, "fstd", "fst.d", 32, |
| 2263 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2264 | }, |
| 2265 | /* fst.p $rm, $disp10x8, $fpf */ |
| 2266 | { |
| 2267 | SH_INSN_FSTP, "fstp", "fst.p", 32, |
| 2268 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2269 | }, |
| 2270 | /* fst.s $rm, $disp10x4, $frf */ |
| 2271 | { |
| 2272 | SH_INSN_FSTS, "fsts", "fst.s", 32, |
| 2273 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2274 | }, |
| 2275 | /* fstx.d $rm, $rn, $drf */ |
| 2276 | { |
| 2277 | SH_INSN_FSTXD, "fstxd", "fstx.d", 32, |
| 2278 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2279 | }, |
| 2280 | /* fstx.p $rm, $rn, $fpf */ |
| 2281 | { |
| 2282 | SH_INSN_FSTXP, "fstxp", "fstx.p", 32, |
| 2283 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2284 | }, |
| 2285 | /* fstx.s $rm, $rn, $frf */ |
| 2286 | { |
| 2287 | SH_INSN_FSTXS, "fstxs", "fstx.s", 32, |
| 2288 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2289 | }, |
| 2290 | /* fsub.d $drg, $drh, $drf */ |
| 2291 | { |
| 2292 | SH_INSN_FSUBD, "fsubd", "fsub.d", 32, |
| 2293 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2294 | }, |
| 2295 | /* fsub.s $frg, $frh, $frf */ |
| 2296 | { |
| 2297 | SH_INSN_FSUBS, "fsubs", "fsub.s", 32, |
| 2298 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2299 | }, |
| 2300 | /* ftrc.dl $drgh, $frf */ |
| 2301 | { |
| 2302 | SH_INSN_FTRCDL, "ftrcdl", "ftrc.dl", 32, |
| 2303 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2304 | }, |
| 2305 | /* ftrc.sl $frgh, $frf */ |
| 2306 | { |
| 2307 | SH_INSN_FTRCSL, "ftrcsl", "ftrc.sl", 32, |
| 2308 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2309 | }, |
| 2310 | /* ftrc.dq $drgh, $drf */ |
| 2311 | { |
| 2312 | SH_INSN_FTRCDQ, "ftrcdq", "ftrc.dq", 32, |
| 2313 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2314 | }, |
| 2315 | /* ftrc.sq $frgh, $drf */ |
| 2316 | { |
| 2317 | SH_INSN_FTRCSQ, "ftrcsq", "ftrc.sq", 32, |
| 2318 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2319 | }, |
| 2320 | /* ftrv.s $mtrxg, $fvh, $fvf */ |
| 2321 | { |
| 2322 | SH_INSN_FTRVS, "ftrvs", "ftrv.s", 32, |
| 2323 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2324 | }, |
| 2325 | /* getcfg $rm, $disp6, $rd */ |
| 2326 | { |
| 2327 | SH_INSN_GETCFG, "getcfg", "getcfg", 32, |
| 2328 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2329 | }, |
| 2330 | /* getcon $crk, $rd */ |
| 2331 | { |
| 2332 | SH_INSN_GETCON, "getcon", "getcon", 32, |
| 2333 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2334 | }, |
| 2335 | /* gettr $trb, $rd */ |
| 2336 | { |
| 2337 | SH_INSN_GETTR, "gettr", "gettr", 32, |
| 2338 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2339 | }, |
| 2340 | /* icbi $rm, $disp6x32 */ |
| 2341 | { |
| 2342 | SH_INSN_ICBI, "icbi", "icbi", 32, |
| 2343 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2344 | }, |
| 2345 | /* ld.b $rm, $disp10, $rd */ |
| 2346 | { |
| 2347 | SH_INSN_LDB, "ldb", "ld.b", 32, |
| 2348 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2349 | }, |
| 2350 | /* ld.l $rm, $disp10x4, $rd */ |
| 2351 | { |
| 2352 | SH_INSN_LDL, "ldl", "ld.l", 32, |
| 2353 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2354 | }, |
| 2355 | /* ld.q $rm, $disp10x8, $rd */ |
| 2356 | { |
| 2357 | SH_INSN_LDQ, "ldq", "ld.q", 32, |
| 2358 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2359 | }, |
| 2360 | /* ld.ub $rm, $disp10, $rd */ |
| 2361 | { |
| 2362 | SH_INSN_LDUB, "ldub", "ld.ub", 32, |
| 2363 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2364 | }, |
| 2365 | /* ld.uw $rm, $disp10x2, $rd */ |
| 2366 | { |
| 2367 | SH_INSN_LDUW, "lduw", "ld.uw", 32, |
| 2368 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2369 | }, |
| 2370 | /* ld.w $rm, $disp10x2, $rd */ |
| 2371 | { |
| 2372 | SH_INSN_LDW, "ldw", "ld.w", 32, |
| 2373 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2374 | }, |
| 2375 | /* ldhi.l $rm, $disp6, $rd */ |
| 2376 | { |
| 2377 | SH_INSN_LDHIL, "ldhil", "ldhi.l", 32, |
| 2378 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2379 | }, |
| 2380 | /* ldhi.q $rm, $disp6, $rd */ |
| 2381 | { |
| 2382 | SH_INSN_LDHIQ, "ldhiq", "ldhi.q", 32, |
| 2383 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2384 | }, |
| 2385 | /* ldlo.l $rm, $disp6, $rd */ |
| 2386 | { |
| 2387 | SH_INSN_LDLOL, "ldlol", "ldlo.l", 32, |
| 2388 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2389 | }, |
| 2390 | /* ldlo.q $rm, $disp6, $rd */ |
| 2391 | { |
| 2392 | SH_INSN_LDLOQ, "ldloq", "ldlo.q", 32, |
| 2393 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2394 | }, |
| 2395 | /* ldx.b $rm, $rn, $rd */ |
| 2396 | { |
| 2397 | SH_INSN_LDXB, "ldxb", "ldx.b", 32, |
| 2398 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2399 | }, |
| 2400 | /* ldx.l $rm, $rn, $rd */ |
| 2401 | { |
| 2402 | SH_INSN_LDXL, "ldxl", "ldx.l", 32, |
| 2403 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2404 | }, |
| 2405 | /* ldx.q $rm, $rn, $rd */ |
| 2406 | { |
| 2407 | SH_INSN_LDXQ, "ldxq", "ldx.q", 32, |
| 2408 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2409 | }, |
| 2410 | /* ldx.ub $rm, $rn, $rd */ |
| 2411 | { |
| 2412 | SH_INSN_LDXUB, "ldxub", "ldx.ub", 32, |
| 2413 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2414 | }, |
| 2415 | /* ldx.uw $rm, $rn, $rd */ |
| 2416 | { |
| 2417 | SH_INSN_LDXUW, "ldxuw", "ldx.uw", 32, |
| 2418 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2419 | }, |
| 2420 | /* ldx.w $rm, $rn, $rd */ |
| 2421 | { |
| 2422 | SH_INSN_LDXW, "ldxw", "ldx.w", 32, |
| 2423 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2424 | }, |
| 2425 | /* mabs.l $rm, $rd */ |
| 2426 | { |
| 2427 | SH_INSN_MABSL, "mabsl", "mabs.l", 32, |
| 2428 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2429 | }, |
| 2430 | /* mabs.w $rm, $rd */ |
| 2431 | { |
| 2432 | SH_INSN_MABSW, "mabsw", "mabs.w", 32, |
| 2433 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2434 | }, |
| 2435 | /* madd.l $rm, $rn, $rd */ |
| 2436 | { |
| 2437 | SH_INSN_MADDL, "maddl", "madd.l", 32, |
| 2438 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2439 | }, |
| 2440 | /* madd.w $rm, $rn, $rd */ |
| 2441 | { |
| 2442 | SH_INSN_MADDW, "maddw", "madd.w", 32, |
| 2443 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2444 | }, |
| 2445 | /* madds.l $rm, $rn, $rd */ |
| 2446 | { |
| 2447 | SH_INSN_MADDSL, "maddsl", "madds.l", 32, |
| 2448 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2449 | }, |
| 2450 | /* madds.ub $rm, $rn, $rd */ |
| 2451 | { |
| 2452 | SH_INSN_MADDSUB, "maddsub", "madds.ub", 32, |
| 2453 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2454 | }, |
| 2455 | /* madds.w $rm, $rn, $rd */ |
| 2456 | { |
| 2457 | SH_INSN_MADDSW, "maddsw", "madds.w", 32, |
| 2458 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2459 | }, |
| 2460 | /* mcmpeq.b $rm, $rn, $rd */ |
| 2461 | { |
| 2462 | SH_INSN_MCMPEQB, "mcmpeqb", "mcmpeq.b", 32, |
| 2463 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2464 | }, |
| 2465 | /* mcmpeq.l $rm, $rn, $rd */ |
| 2466 | { |
| 2467 | SH_INSN_MCMPEQL, "mcmpeql", "mcmpeq.l", 32, |
| 2468 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2469 | }, |
| 2470 | /* mcmpeq.w $rm, $rn, $rd */ |
| 2471 | { |
| 2472 | SH_INSN_MCMPEQW, "mcmpeqw", "mcmpeq.w", 32, |
| 2473 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2474 | }, |
| 2475 | /* mcmpgt.l $rm, $rn, $rd */ |
| 2476 | { |
| 2477 | SH_INSN_MCMPGTL, "mcmpgtl", "mcmpgt.l", 32, |
| 2478 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2479 | }, |
| 2480 | /* mcmpgt.ub $rm, $rn, $rd */ |
| 2481 | { |
| 2482 | SH_INSN_MCMPGTUB, "mcmpgtub", "mcmpgt.ub", 32, |
| 2483 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2484 | }, |
| 2485 | /* mcmpgt.w $rm, $rn, $rd */ |
| 2486 | { |
| 2487 | SH_INSN_MCMPGTW, "mcmpgtw", "mcmpgt.w", 32, |
| 2488 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2489 | }, |
| 2490 | /* mcmv $rm, $rn, $rd */ |
| 2491 | { |
| 2492 | SH_INSN_MCMV, "mcmv", "mcmv", 32, |
| 2493 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2494 | }, |
| 2495 | /* mcnvs.lw $rm, $rn, $rd */ |
| 2496 | { |
| 2497 | SH_INSN_MCNVSLW, "mcnvslw", "mcnvs.lw", 32, |
| 2498 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2499 | }, |
| 2500 | /* mcnvs.wb $rm, $rn, $rd */ |
| 2501 | { |
| 2502 | SH_INSN_MCNVSWB, "mcnvswb", "mcnvs.wb", 32, |
| 2503 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2504 | }, |
| 2505 | /* mcnvs.wub $rm, $rn, $rd */ |
| 2506 | { |
| 2507 | SH_INSN_MCNVSWUB, "mcnvswub", "mcnvs.wub", 32, |
| 2508 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2509 | }, |
| 2510 | /* mextr1 $rm, $rn, $rd */ |
| 2511 | { |
| 2512 | SH_INSN_MEXTR1, "mextr1", "mextr1", 32, |
| 2513 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2514 | }, |
| 2515 | /* mextr2 $rm, $rn, $rd */ |
| 2516 | { |
| 2517 | SH_INSN_MEXTR2, "mextr2", "mextr2", 32, |
| 2518 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2519 | }, |
| 2520 | /* mextr3 $rm, $rn, $rd */ |
| 2521 | { |
| 2522 | SH_INSN_MEXTR3, "mextr3", "mextr3", 32, |
| 2523 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2524 | }, |
| 2525 | /* mextr4 $rm, $rn, $rd */ |
| 2526 | { |
| 2527 | SH_INSN_MEXTR4, "mextr4", "mextr4", 32, |
| 2528 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2529 | }, |
| 2530 | /* mextr5 $rm, $rn, $rd */ |
| 2531 | { |
| 2532 | SH_INSN_MEXTR5, "mextr5", "mextr5", 32, |
| 2533 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2534 | }, |
| 2535 | /* mextr6 $rm, $rn, $rd */ |
| 2536 | { |
| 2537 | SH_INSN_MEXTR6, "mextr6", "mextr6", 32, |
| 2538 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2539 | }, |
| 2540 | /* mextr7 $rm, $rn, $rd */ |
| 2541 | { |
| 2542 | SH_INSN_MEXTR7, "mextr7", "mextr7", 32, |
| 2543 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2544 | }, |
| 2545 | /* mmacfx.wl $rm, $rn, $rd */ |
| 2546 | { |
| 2547 | SH_INSN_MMACFXWL, "mmacfxwl", "mmacfx.wl", 32, |
| 2548 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2549 | }, |
| 2550 | /* mmacnfx.wl $rm, $rn, $rd */ |
| 2551 | { |
| 2552 | SH_INSN_MMACNFX_WL, "mmacnfx.wl", "mmacnfx.wl", 32, |
| 2553 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2554 | }, |
| 2555 | /* mmul.l $rm, $rn, $rd */ |
| 2556 | { |
| 2557 | SH_INSN_MMULL, "mmull", "mmul.l", 32, |
| 2558 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2559 | }, |
| 2560 | /* mmul.w $rm, $rn, $rd */ |
| 2561 | { |
| 2562 | SH_INSN_MMULW, "mmulw", "mmul.w", 32, |
| 2563 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2564 | }, |
| 2565 | /* mmulfx.l $rm, $rn, $rd */ |
| 2566 | { |
| 2567 | SH_INSN_MMULFXL, "mmulfxl", "mmulfx.l", 32, |
| 2568 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2569 | }, |
| 2570 | /* mmulfx.w $rm, $rn, $rd */ |
| 2571 | { |
| 2572 | SH_INSN_MMULFXW, "mmulfxw", "mmulfx.w", 32, |
| 2573 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2574 | }, |
| 2575 | /* mmulfxrp.w $rm, $rn, $rd */ |
| 2576 | { |
| 2577 | SH_INSN_MMULFXRPW, "mmulfxrpw", "mmulfxrp.w", 32, |
| 2578 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2579 | }, |
| 2580 | /* mmulhi.wl $rm, $rn, $rd */ |
| 2581 | { |
| 2582 | SH_INSN_MMULHIWL, "mmulhiwl", "mmulhi.wl", 32, |
| 2583 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2584 | }, |
| 2585 | /* mmullo.wl $rm, $rn, $rd */ |
| 2586 | { |
| 2587 | SH_INSN_MMULLOWL, "mmullowl", "mmullo.wl", 32, |
| 2588 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2589 | }, |
| 2590 | /* mmulsum.wq $rm, $rn, $rd */ |
| 2591 | { |
| 2592 | SH_INSN_MMULSUMWQ, "mmulsumwq", "mmulsum.wq", 32, |
| 2593 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2594 | }, |
| 2595 | /* movi $imm16, $rd */ |
| 2596 | { |
| 2597 | SH_INSN_MOVI, "movi", "movi", 32, |
| 2598 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2599 | }, |
| 2600 | /* mperm.w $rm, $rn, $rd */ |
| 2601 | { |
| 2602 | SH_INSN_MPERMW, "mpermw", "mperm.w", 32, |
| 2603 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2604 | }, |
| 2605 | /* msad.ubq $rm, $rn, $rd */ |
| 2606 | { |
| 2607 | SH_INSN_MSADUBQ, "msadubq", "msad.ubq", 32, |
| 2608 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2609 | }, |
| 2610 | /* mshalds.l $rm, $rn, $rd */ |
| 2611 | { |
| 2612 | SH_INSN_MSHALDSL, "mshaldsl", "mshalds.l", 32, |
| 2613 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2614 | }, |
| 2615 | /* mshalds.w $rm, $rn, $rd */ |
| 2616 | { |
| 2617 | SH_INSN_MSHALDSW, "mshaldsw", "mshalds.w", 32, |
| 2618 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2619 | }, |
| 2620 | /* mshard.l $rm, $rn, $rd */ |
| 2621 | { |
| 2622 | SH_INSN_MSHARDL, "mshardl", "mshard.l", 32, |
| 2623 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2624 | }, |
| 2625 | /* mshard.w $rm, $rn, $rd */ |
| 2626 | { |
| 2627 | SH_INSN_MSHARDW, "mshardw", "mshard.w", 32, |
| 2628 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2629 | }, |
| 2630 | /* mshards.q $rm, $rn, $rd */ |
| 2631 | { |
| 2632 | SH_INSN_MSHARDSQ, "mshardsq", "mshards.q", 32, |
| 2633 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2634 | }, |
| 2635 | /* mshfhi.b $rm, $rn, $rd */ |
| 2636 | { |
| 2637 | SH_INSN_MSHFHIB, "mshfhib", "mshfhi.b", 32, |
| 2638 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2639 | }, |
| 2640 | /* mshfhi.l $rm, $rn, $rd */ |
| 2641 | { |
| 2642 | SH_INSN_MSHFHIL, "mshfhil", "mshfhi.l", 32, |
| 2643 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2644 | }, |
| 2645 | /* mshfhi.w $rm, $rn, $rd */ |
| 2646 | { |
| 2647 | SH_INSN_MSHFHIW, "mshfhiw", "mshfhi.w", 32, |
| 2648 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2649 | }, |
| 2650 | /* mshflo.b $rm, $rn, $rd */ |
| 2651 | { |
| 2652 | SH_INSN_MSHFLOB, "mshflob", "mshflo.b", 32, |
| 2653 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2654 | }, |
| 2655 | /* mshflo.l $rm, $rn, $rd */ |
| 2656 | { |
| 2657 | SH_INSN_MSHFLOL, "mshflol", "mshflo.l", 32, |
| 2658 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2659 | }, |
| 2660 | /* mshflo.w $rm, $rn, $rd */ |
| 2661 | { |
| 2662 | SH_INSN_MSHFLOW, "mshflow", "mshflo.w", 32, |
| 2663 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2664 | }, |
| 2665 | /* mshlld.l $rm, $rn, $rd */ |
| 2666 | { |
| 2667 | SH_INSN_MSHLLDL, "mshlldl", "mshlld.l", 32, |
| 2668 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2669 | }, |
| 2670 | /* mshlld.w $rm, $rn, $rd */ |
| 2671 | { |
| 2672 | SH_INSN_MSHLLDW, "mshlldw", "mshlld.w", 32, |
| 2673 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2674 | }, |
| 2675 | /* mshlrd.l $rm, $rn, $rd */ |
| 2676 | { |
| 2677 | SH_INSN_MSHLRDL, "mshlrdl", "mshlrd.l", 32, |
| 2678 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2679 | }, |
| 2680 | /* mshlrd.w $rm, $rn, $rd */ |
| 2681 | { |
| 2682 | SH_INSN_MSHLRDW, "mshlrdw", "mshlrd.w", 32, |
| 2683 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2684 | }, |
| 2685 | /* msub.l $rm, $rn, $rd */ |
| 2686 | { |
| 2687 | SH_INSN_MSUBL, "msubl", "msub.l", 32, |
| 2688 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2689 | }, |
| 2690 | /* msub.w $rm, $rn, $rd */ |
| 2691 | { |
| 2692 | SH_INSN_MSUBW, "msubw", "msub.w", 32, |
| 2693 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2694 | }, |
| 2695 | /* msubs.l $rm, $rn, $rd */ |
| 2696 | { |
| 2697 | SH_INSN_MSUBSL, "msubsl", "msubs.l", 32, |
| 2698 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2699 | }, |
| 2700 | /* msubs.ub $rm, $rn, $rd */ |
| 2701 | { |
| 2702 | SH_INSN_MSUBSUB, "msubsub", "msubs.ub", 32, |
| 2703 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2704 | }, |
| 2705 | /* msubs.w $rm, $rn, $rd */ |
| 2706 | { |
| 2707 | SH_INSN_MSUBSW, "msubsw", "msubs.w", 32, |
| 2708 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2709 | }, |
| 2710 | /* muls.l $rm, $rn, $rd */ |
| 2711 | { |
| 2712 | SH_INSN_MULSL, "mulsl", "muls.l", 32, |
| 2713 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2714 | }, |
| 2715 | /* mulu.l $rm, $rn, $rd */ |
| 2716 | { |
| 2717 | SH_INSN_MULUL, "mulul", "mulu.l", 32, |
| 2718 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2719 | }, |
| 2720 | /* nop */ |
| 2721 | { |
| 2722 | SH_INSN_NOP, "nop", "nop", 32, |
| 2723 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2724 | }, |
| 2725 | /* nsb $rm, $rd */ |
| 2726 | { |
| 2727 | SH_INSN_NSB, "nsb", "nsb", 32, |
| 2728 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2729 | }, |
| 2730 | /* ocbi $rm, $disp6x32 */ |
| 2731 | { |
| 2732 | SH_INSN_OCBI, "ocbi", "ocbi", 32, |
| 2733 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2734 | }, |
| 2735 | /* ocbp $rm, $disp6x32 */ |
| 2736 | { |
| 2737 | SH_INSN_OCBP, "ocbp", "ocbp", 32, |
| 2738 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2739 | }, |
| 2740 | /* ocbwb $rm, $disp6x32 */ |
| 2741 | { |
| 2742 | SH_INSN_OCBWB, "ocbwb", "ocbwb", 32, |
| 2743 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2744 | }, |
| 2745 | /* or $rm, $rn, $rd */ |
| 2746 | { |
| 2747 | SH_INSN_OR, "or", "or", 32, |
| 2748 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2749 | }, |
| 2750 | /* ori $rm, $imm10, $rd */ |
| 2751 | { |
| 2752 | SH_INSN_ORI, "ori", "ori", 32, |
| 2753 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2754 | }, |
| 2755 | /* prefi $rm, $disp6x32 */ |
| 2756 | { |
| 2757 | SH_INSN_PREFI, "prefi", "prefi", 32, |
| 2758 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2759 | }, |
| 2760 | /* pta$likely $disp16, $tra */ |
| 2761 | { |
| 2762 | SH_INSN_PTA, "pta", "pta", 32, |
| 2763 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2764 | }, |
| 2765 | /* ptabs$likely $rn, $tra */ |
| 2766 | { |
| 2767 | SH_INSN_PTABS, "ptabs", "ptabs", 32, |
| 2768 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2769 | }, |
| 2770 | /* ptb$likely $disp16, $tra */ |
| 2771 | { |
| 2772 | SH_INSN_PTB, "ptb", "ptb", 32, |
| 2773 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2774 | }, |
| 2775 | /* ptrel$likely $rn, $tra */ |
| 2776 | { |
| 2777 | SH_INSN_PTREL, "ptrel", "ptrel", 32, |
| 2778 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2779 | }, |
| 2780 | /* putcfg $rm, $disp6, $rd */ |
| 2781 | { |
| 2782 | SH_INSN_PUTCFG, "putcfg", "putcfg", 32, |
| 2783 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2784 | }, |
| 2785 | /* putcon $rm, $crj */ |
| 2786 | { |
| 2787 | SH_INSN_PUTCON, "putcon", "putcon", 32, |
| 2788 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2789 | }, |
| 2790 | /* rte */ |
| 2791 | { |
| 2792 | SH_INSN_RTE, "rte", "rte", 32, |
| 2793 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2794 | }, |
| 2795 | /* shard $rm, $rn, $rd */ |
| 2796 | { |
| 2797 | SH_INSN_SHARD, "shard", "shard", 32, |
| 2798 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2799 | }, |
| 2800 | /* shard.l $rm, $rn, $rd */ |
| 2801 | { |
| 2802 | SH_INSN_SHARDL, "shardl", "shard.l", 32, |
| 2803 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2804 | }, |
| 2805 | /* shari $rm, $uimm6, $rd */ |
| 2806 | { |
| 2807 | SH_INSN_SHARI, "shari", "shari", 32, |
| 2808 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2809 | }, |
| 2810 | /* shari.l $rm, $uimm6, $rd */ |
| 2811 | { |
| 2812 | SH_INSN_SHARIL, "sharil", "shari.l", 32, |
| 2813 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2814 | }, |
| 2815 | /* shlld $rm, $rn, $rd */ |
| 2816 | { |
| 2817 | SH_INSN_SHLLD, "shlld", "shlld", 32, |
| 2818 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2819 | }, |
| 2820 | /* shlld.l $rm, $rn, $rd */ |
| 2821 | { |
| 2822 | SH_INSN_SHLLDL, "shlldl", "shlld.l", 32, |
| 2823 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2824 | }, |
| 2825 | /* shlli $rm, $uimm6, $rd */ |
| 2826 | { |
| 2827 | SH_INSN_SHLLI, "shlli", "shlli", 32, |
| 2828 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2829 | }, |
| 2830 | /* shlli.l $rm, $uimm6, $rd */ |
| 2831 | { |
| 2832 | SH_INSN_SHLLIL, "shllil", "shlli.l", 32, |
| 2833 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2834 | }, |
| 2835 | /* shlrd $rm, $rn, $rd */ |
| 2836 | { |
| 2837 | SH_INSN_SHLRD, "shlrd", "shlrd", 32, |
| 2838 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2839 | }, |
| 2840 | /* shlrd.l $rm, $rn, $rd */ |
| 2841 | { |
| 2842 | SH_INSN_SHLRDL, "shlrdl", "shlrd.l", 32, |
| 2843 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2844 | }, |
| 2845 | /* shlri $rm, $uimm6, $rd */ |
| 2846 | { |
| 2847 | SH_INSN_SHLRI, "shlri", "shlri", 32, |
| 2848 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2849 | }, |
| 2850 | /* shlri.l $rm, $uimm6, $rd */ |
| 2851 | { |
| 2852 | SH_INSN_SHLRIL, "shlril", "shlri.l", 32, |
| 2853 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2854 | }, |
| 2855 | /* shori $uimm16, $rd */ |
| 2856 | { |
| 2857 | SH_INSN_SHORI, "shori", "shori", 32, |
| 2858 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2859 | }, |
| 2860 | /* sleep */ |
| 2861 | { |
| 2862 | SH_INSN_SLEEP, "sleep", "sleep", 32, |
| 2863 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2864 | }, |
| 2865 | /* st.b $rm, $disp10, $rd */ |
| 2866 | { |
| 2867 | SH_INSN_STB, "stb", "st.b", 32, |
| 2868 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2869 | }, |
| 2870 | /* st.l $rm, $disp10x4, $rd */ |
| 2871 | { |
| 2872 | SH_INSN_STL, "stl", "st.l", 32, |
| 2873 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2874 | }, |
| 2875 | /* st.q $rm, $disp10x8, $rd */ |
| 2876 | { |
| 2877 | SH_INSN_STQ, "stq", "st.q", 32, |
| 2878 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2879 | }, |
| 2880 | /* st.w $rm, $disp10x2, $rd */ |
| 2881 | { |
| 2882 | SH_INSN_STW, "stw", "st.w", 32, |
| 2883 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2884 | }, |
| 2885 | /* sthi.l $rm, $disp6, $rd */ |
| 2886 | { |
| 2887 | SH_INSN_STHIL, "sthil", "sthi.l", 32, |
| 2888 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2889 | }, |
| 2890 | /* sthi.q $rm, $disp6, $rd */ |
| 2891 | { |
| 2892 | SH_INSN_STHIQ, "sthiq", "sthi.q", 32, |
| 2893 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2894 | }, |
| 2895 | /* stlo.l $rm, $disp6, $rd */ |
| 2896 | { |
| 2897 | SH_INSN_STLOL, "stlol", "stlo.l", 32, |
| 2898 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2899 | }, |
| 2900 | /* stlo.q $rm, $disp6, $rd */ |
| 2901 | { |
| 2902 | SH_INSN_STLOQ, "stloq", "stlo.q", 32, |
| 2903 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2904 | }, |
| 2905 | /* stx.b $rm, $rn, $rd */ |
| 2906 | { |
| 2907 | SH_INSN_STXB, "stxb", "stx.b", 32, |
| 2908 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2909 | }, |
| 2910 | /* stx.l $rm, $rn, $rd */ |
| 2911 | { |
| 2912 | SH_INSN_STXL, "stxl", "stx.l", 32, |
| 2913 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2914 | }, |
| 2915 | /* stx.q $rm, $rn, $rd */ |
| 2916 | { |
| 2917 | SH_INSN_STXQ, "stxq", "stx.q", 32, |
| 2918 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2919 | }, |
| 2920 | /* stx.w $rm, $rn, $rd */ |
| 2921 | { |
| 2922 | SH_INSN_STXW, "stxw", "stx.w", 32, |
| 2923 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2924 | }, |
| 2925 | /* sub $rm, $rn, $rd */ |
| 2926 | { |
| 2927 | SH_INSN_SUB, "sub", "sub", 32, |
| 2928 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2929 | }, |
| 2930 | /* sub.l $rm, $rn, $rd */ |
| 2931 | { |
| 2932 | SH_INSN_SUBL, "subl", "sub.l", 32, |
| 2933 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2934 | }, |
| 2935 | /* swap.q $rm, $rn, $rd */ |
| 2936 | { |
| 2937 | SH_INSN_SWAPQ, "swapq", "swap.q", 32, |
| 2938 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2939 | }, |
| 2940 | /* synci */ |
| 2941 | { |
| 2942 | SH_INSN_SYNCI, "synci", "synci", 32, |
| 2943 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2944 | }, |
| 2945 | /* synco */ |
| 2946 | { |
| 2947 | SH_INSN_SYNCO, "synco", "synco", 32, |
| 2948 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2949 | }, |
| 2950 | /* trapa $rm */ |
| 2951 | { |
| 2952 | SH_INSN_TRAPA, "trapa", "trapa", 32, |
| 2953 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2954 | }, |
| 2955 | /* xor $rm, $rn, $rd */ |
| 2956 | { |
| 2957 | SH_INSN_XOR, "xor", "xor", 32, |
| 2958 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2959 | }, |
| 2960 | /* xori $rm, $imm6, $rd */ |
| 2961 | { |
| 2962 | SH_INSN_XORI, "xori", "xori", 32, |
| 2963 | { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } |
| 2964 | }, |
| 2965 | }; |
| 2966 | |
| 2967 | #undef OP |
| 2968 | #undef A |
| 2969 | |
| 2970 | /* Initialize anything needed to be done once, before any cpu_open call. */ |
| 2971 | |
| 2972 | static void |
| 2973 | init_tables () |
| 2974 | { |
| 2975 | } |
| 2976 | |
| 2977 | /* Subroutine of sh_cgen_cpu_open to look up a mach via its bfd name. */ |
| 2978 | |
| 2979 | static const CGEN_MACH * |
| 2980 | lookup_mach_via_bfd_name (table, name) |
| 2981 | const CGEN_MACH *table; |
| 2982 | const char *name; |
| 2983 | { |
| 2984 | while (table->name) |
| 2985 | { |
| 2986 | if (strcmp (name, table->bfd_name) == 0) |
| 2987 | return table; |
| 2988 | ++table; |
| 2989 | } |
| 2990 | abort (); |
| 2991 | } |
| 2992 | |
| 2993 | /* Subroutine of sh_cgen_cpu_open to build the hardware table. */ |
| 2994 | |
| 2995 | static void |
| 2996 | build_hw_table (cd) |
| 2997 | CGEN_CPU_TABLE *cd; |
| 2998 | { |
| 2999 | int i; |
| 3000 | int machs = cd->machs; |
| 3001 | const CGEN_HW_ENTRY *init = & sh_cgen_hw_table[0]; |
| 3002 | /* MAX_HW is only an upper bound on the number of selected entries. |
| 3003 | However each entry is indexed by it's enum so there can be holes in |
| 3004 | the table. */ |
| 3005 | const CGEN_HW_ENTRY **selected = |
| 3006 | (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); |
| 3007 | |
| 3008 | cd->hw_table.init_entries = init; |
| 3009 | cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); |
| 3010 | memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); |
| 3011 | /* ??? For now we just use machs to determine which ones we want. */ |
| 3012 | for (i = 0; init[i].name != NULL; ++i) |
| 3013 | if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) |
| 3014 | & machs) |
| 3015 | selected[init[i].type] = &init[i]; |
| 3016 | cd->hw_table.entries = selected; |
| 3017 | cd->hw_table.num_entries = MAX_HW; |
| 3018 | } |
| 3019 | |
| 3020 | /* Subroutine of sh_cgen_cpu_open to build the hardware table. */ |
| 3021 | |
| 3022 | static void |
| 3023 | build_ifield_table (cd) |
| 3024 | CGEN_CPU_TABLE *cd; |
| 3025 | { |
| 3026 | cd->ifld_table = & sh_cgen_ifld_table[0]; |
| 3027 | } |
| 3028 | |
| 3029 | /* Subroutine of sh_cgen_cpu_open to build the hardware table. */ |
| 3030 | |
| 3031 | static void |
| 3032 | build_operand_table (cd) |
| 3033 | CGEN_CPU_TABLE *cd; |
| 3034 | { |
| 3035 | int i; |
| 3036 | int machs = cd->machs; |
| 3037 | const CGEN_OPERAND *init = & sh_cgen_operand_table[0]; |
| 3038 | /* MAX_OPERANDS is only an upper bound on the number of selected entries. |
| 3039 | However each entry is indexed by it's enum so there can be holes in |
| 3040 | the table. */ |
| 3041 | const CGEN_OPERAND **selected = |
| 3042 | (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); |
| 3043 | |
| 3044 | cd->operand_table.init_entries = init; |
| 3045 | cd->operand_table.entry_size = sizeof (CGEN_OPERAND); |
| 3046 | memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); |
| 3047 | /* ??? For now we just use mach to determine which ones we want. */ |
| 3048 | for (i = 0; init[i].name != NULL; ++i) |
| 3049 | if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) |
| 3050 | & machs) |
| 3051 | selected[init[i].type] = &init[i]; |
| 3052 | cd->operand_table.entries = selected; |
| 3053 | cd->operand_table.num_entries = MAX_OPERANDS; |
| 3054 | } |
| 3055 | |
| 3056 | /* Subroutine of sh_cgen_cpu_open to build the hardware table. |
| 3057 | ??? This could leave out insns not supported by the specified mach/isa, |
| 3058 | but that would cause errors like "foo only supported by bar" to become |
| 3059 | "unknown insn", so for now we include all insns and require the app to |
| 3060 | do the checking later. |
| 3061 | ??? On the other hand, parsing of such insns may require their hardware or |
| 3062 | operand elements to be in the table [which they mightn't be]. */ |
| 3063 | |
| 3064 | static void |
| 3065 | build_insn_table (cd) |
| 3066 | CGEN_CPU_TABLE *cd; |
| 3067 | { |
| 3068 | int i; |
| 3069 | const CGEN_IBASE *ib = & sh_cgen_insn_table[0]; |
| 3070 | CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); |
| 3071 | |
| 3072 | memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); |
| 3073 | for (i = 0; i < MAX_INSNS; ++i) |
| 3074 | insns[i].base = &ib[i]; |
| 3075 | cd->insn_table.init_entries = insns; |
| 3076 | cd->insn_table.entry_size = sizeof (CGEN_IBASE); |
| 3077 | cd->insn_table.num_init_entries = MAX_INSNS; |
| 3078 | } |
| 3079 | |
| 3080 | /* Subroutine of sh_cgen_cpu_open to rebuild the tables. */ |
| 3081 | |
| 3082 | static void |
| 3083 | sh_cgen_rebuild_tables (cd) |
| 3084 | CGEN_CPU_TABLE *cd; |
| 3085 | { |
| 3086 | int i,n_isas; |
| 3087 | unsigned int isas = cd->isas; |
| 3088 | #if 0 |
| 3089 | unsigned int machs = cd->machs; |
| 3090 | #endif |
| 3091 | |
| 3092 | cd->int_insn_p = CGEN_INT_INSN_P; |
| 3093 | |
| 3094 | /* Data derived from the isa spec. */ |
| 3095 | #define UNSET (CGEN_SIZE_UNKNOWN + 1) |
| 3096 | cd->default_insn_bitsize = UNSET; |
| 3097 | cd->base_insn_bitsize = UNSET; |
| 3098 | cd->min_insn_bitsize = 65535; /* some ridiculously big number */ |
| 3099 | cd->max_insn_bitsize = 0; |
| 3100 | for (i = 0; i < MAX_ISAS; ++i) |
| 3101 | if (((1 << i) & isas) != 0) |
| 3102 | { |
| 3103 | const CGEN_ISA *isa = & sh_cgen_isa_table[i]; |
| 3104 | |
| 3105 | /* Default insn sizes of all selected isas must be equal or we set |
| 3106 | the result to 0, meaning "unknown". */ |
| 3107 | if (cd->default_insn_bitsize == UNSET) |
| 3108 | cd->default_insn_bitsize = isa->default_insn_bitsize; |
| 3109 | else if (isa->default_insn_bitsize == cd->default_insn_bitsize) |
| 3110 | ; /* this is ok */ |
| 3111 | else |
| 3112 | cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; |
| 3113 | |
| 3114 | /* Base insn sizes of all selected isas must be equal or we set |
| 3115 | the result to 0, meaning "unknown". */ |
| 3116 | if (cd->base_insn_bitsize == UNSET) |
| 3117 | cd->base_insn_bitsize = isa->base_insn_bitsize; |
| 3118 | else if (isa->base_insn_bitsize == cd->base_insn_bitsize) |
| 3119 | ; /* this is ok */ |
| 3120 | else |
| 3121 | cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; |
| 3122 | |
| 3123 | /* Set min,max insn sizes. */ |
| 3124 | if (isa->min_insn_bitsize < cd->min_insn_bitsize) |
| 3125 | cd->min_insn_bitsize = isa->min_insn_bitsize; |
| 3126 | if (isa->max_insn_bitsize > cd->max_insn_bitsize) |
| 3127 | cd->max_insn_bitsize = isa->max_insn_bitsize; |
| 3128 | |
| 3129 | ++n_isas; |
| 3130 | } |
| 3131 | |
| 3132 | #if 0 /* Does nothing?? */ |
| 3133 | /* Data derived from the mach spec. */ |
| 3134 | for (i = 0; i < MAX_MACHS; ++i) |
| 3135 | if (((1 << i) & machs) != 0) |
| 3136 | { |
| 3137 | const CGEN_MACH *mach = & sh_cgen_mach_table[i]; |
| 3138 | |
| 3139 | ++n_machs; |
| 3140 | } |
| 3141 | #endif |
| 3142 | |
| 3143 | /* Determine which hw elements are used by MACH. */ |
| 3144 | build_hw_table (cd); |
| 3145 | |
| 3146 | /* Build the ifield table. */ |
| 3147 | build_ifield_table (cd); |
| 3148 | |
| 3149 | /* Determine which operands are used by MACH/ISA. */ |
| 3150 | build_operand_table (cd); |
| 3151 | |
| 3152 | /* Build the instruction table. */ |
| 3153 | build_insn_table (cd); |
| 3154 | } |
| 3155 | |
| 3156 | /* Initialize a cpu table and return a descriptor. |
| 3157 | It's much like opening a file, and must be the first function called. |
| 3158 | The arguments are a set of (type/value) pairs, terminated with |
| 3159 | CGEN_CPU_OPEN_END. |
| 3160 | |
| 3161 | Currently supported values: |
| 3162 | CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr |
| 3163 | CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr |
| 3164 | CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name |
| 3165 | CGEN_CPU_OPEN_ENDIAN: specify endian choice |
| 3166 | CGEN_CPU_OPEN_END: terminates arguments |
| 3167 | |
| 3168 | ??? Simultaneous multiple isas might not make sense, but it's not (yet) |
| 3169 | precluded. |
| 3170 | |
| 3171 | ??? We only support ISO C stdargs here, not K&R. |
| 3172 | Laziness, plus experiment to see if anything requires K&R - eventually |
| 3173 | K&R will no longer be supported - e.g. GDB is currently trying this. */ |
| 3174 | |
| 3175 | CGEN_CPU_DESC |
| 3176 | sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) |
| 3177 | { |
| 3178 | CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); |
| 3179 | static int init_p; |
| 3180 | unsigned int isas = 0; /* 0 = "unspecified" */ |
| 3181 | unsigned int machs = 0; /* 0 = "unspecified" */ |
| 3182 | enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; |
| 3183 | va_list ap; |
| 3184 | |
| 3185 | if (! init_p) |
| 3186 | { |
| 3187 | init_tables (); |
| 3188 | init_p = 1; |
| 3189 | } |
| 3190 | |
| 3191 | memset (cd, 0, sizeof (*cd)); |
| 3192 | |
| 3193 | va_start (ap, arg_type); |
| 3194 | while (arg_type != CGEN_CPU_OPEN_END) |
| 3195 | { |
| 3196 | switch (arg_type) |
| 3197 | { |
| 3198 | case CGEN_CPU_OPEN_ISAS : |
| 3199 | isas = va_arg (ap, unsigned int); |
| 3200 | break; |
| 3201 | case CGEN_CPU_OPEN_MACHS : |
| 3202 | machs = va_arg (ap, unsigned int); |
| 3203 | break; |
| 3204 | case CGEN_CPU_OPEN_BFDMACH : |
| 3205 | { |
| 3206 | const char *name = va_arg (ap, const char *); |
| 3207 | const CGEN_MACH *mach = |
| 3208 | lookup_mach_via_bfd_name (sh_cgen_mach_table, name); |
| 3209 | |
| 3210 | machs |= mach->num << 1; |
| 3211 | break; |
| 3212 | } |
| 3213 | case CGEN_CPU_OPEN_ENDIAN : |
| 3214 | endian = va_arg (ap, enum cgen_endian); |
| 3215 | break; |
| 3216 | default : |
| 3217 | fprintf (stderr, "sh_cgen_cpu_open: unsupported argument `%d'\n", |
| 3218 | arg_type); |
| 3219 | abort (); /* ??? return NULL? */ |
| 3220 | } |
| 3221 | arg_type = va_arg (ap, enum cgen_cpu_open_arg); |
| 3222 | } |
| 3223 | va_end (ap); |
| 3224 | |
| 3225 | /* mach unspecified means "all" */ |
| 3226 | if (machs == 0) |
| 3227 | machs = (1 << MAX_MACHS) - 1; |
| 3228 | /* base mach is always selected */ |
| 3229 | machs |= 1; |
| 3230 | /* isa unspecified means "all" */ |
| 3231 | if (isas == 0) |
| 3232 | isas = (1 << MAX_ISAS) - 1; |
| 3233 | if (endian == CGEN_ENDIAN_UNKNOWN) |
| 3234 | { |
| 3235 | /* ??? If target has only one, could have a default. */ |
| 3236 | fprintf (stderr, "sh_cgen_cpu_open: no endianness specified\n"); |
| 3237 | abort (); |
| 3238 | } |
| 3239 | |
| 3240 | cd->isas = isas; |
| 3241 | cd->machs = machs; |
| 3242 | cd->endian = endian; |
| 3243 | /* FIXME: for the sparc case we can determine insn-endianness statically. |
| 3244 | The worry here is where both data and insn endian can be independently |
| 3245 | chosen, in which case this function will need another argument. |
| 3246 | Actually, will want to allow for more arguments in the future anyway. */ |
| 3247 | cd->insn_endian = endian; |
| 3248 | |
| 3249 | /* Table (re)builder. */ |
| 3250 | cd->rebuild_tables = sh_cgen_rebuild_tables; |
| 3251 | sh_cgen_rebuild_tables (cd); |
| 3252 | |
| 3253 | /* Default to not allowing signed overflow. */ |
| 3254 | cd->signed_overflow_ok_p = 0; |
| 3255 | |
| 3256 | return (CGEN_CPU_DESC) cd; |
| 3257 | } |
| 3258 | |
| 3259 | /* Cover fn to sh_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. |
| 3260 | MACH_NAME is the bfd name of the mach. */ |
| 3261 | |
| 3262 | CGEN_CPU_DESC |
| 3263 | sh_cgen_cpu_open_1 (mach_name, endian) |
| 3264 | const char *mach_name; |
| 3265 | enum cgen_endian endian; |
| 3266 | { |
| 3267 | return sh_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, |
| 3268 | CGEN_CPU_OPEN_ENDIAN, endian, |
| 3269 | CGEN_CPU_OPEN_END); |
| 3270 | } |
| 3271 | |
| 3272 | /* Close a cpu table. |
| 3273 | ??? This can live in a machine independent file, but there's currently |
| 3274 | no place to put this file (there's no libcgen). libopcodes is the wrong |
| 3275 | place as some simulator ports use this but they don't use libopcodes. */ |
| 3276 | |
| 3277 | void |
| 3278 | sh_cgen_cpu_close (cd) |
| 3279 | CGEN_CPU_DESC cd; |
| 3280 | { |
| 3281 | if (cd->insn_table.init_entries) |
| 3282 | free ((CGEN_INSN *) cd->insn_table.init_entries); |
| 3283 | if (cd->hw_table.entries) |
| 3284 | free ((CGEN_HW_ENTRY *) cd->hw_table.entries); |
| 3285 | free (cd); |
| 3286 | } |
| 3287 | |