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ASoC: Add helper functions bias level management
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
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1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <trace/events/asoc.h>
33
34#include <linux/mfd/wm8994/core.h>
35#include <linux/mfd/wm8994/registers.h>
36#include <linux/mfd/wm8994/pdata.h>
37#include <linux/mfd/wm8994/gpio.h>
38
39#include "wm8994.h"
40#include "wm_hubs.h"
41
42#define WM1811_JACKDET_MODE_NONE 0x0000
43#define WM1811_JACKDET_MODE_JACK 0x0100
44#define WM1811_JACKDET_MODE_MIC 0x0080
45#define WM1811_JACKDET_MODE_AUDIO 0x0180
46
47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
50static struct {
51 unsigned int reg;
52 unsigned int mask;
53} wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81};
82
83static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87};
88
89static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93};
94
95static const struct wm8958_micd_rate micdet_rates[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
100};
101
102static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
107};
108
109static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110{
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112 struct wm8994 *control = wm8994->wm8994;
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
129 } else if (wm8994->jackdet) {
130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
137 best = 0;
138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
140 continue;
141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
143 best = i;
144 else if (rates[best].idle != idle)
145 best = i;
146 }
147
148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150
151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158}
159
160static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161{
162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
203
204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211}
212
213static int configure_clock(struct snd_soc_codec *codec)
214{
215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
216 int change, new;
217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
231 return 0;
232 }
233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
243
244 wm8958_micd_set_rate(codec);
245
246 return 0;
247}
248
249static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251{
252 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
253 int reg = snd_soc_read(codec, WM8994_CLOCKING_1);
254 const char *clk;
255
256 /* Check what we're currently using for CLK_SYS */
257 if (reg & WM8994_SYSCLK_SRC)
258 clk = "AIF2CLK";
259 else
260 clk = "AIF1CLK";
261
262 return strcmp(source->name, clk) == 0;
263}
264
265static const char *sidetone_hpf_text[] = {
266 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
267};
268
269static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
270 WM8994_SIDETONE, 7, sidetone_hpf_text);
271
272static const char *adc_hpf_text[] = {
273 "HiFi", "Voice 1", "Voice 2", "Voice 3"
274};
275
276static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
277 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
278
279static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
280 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
281
282static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
283 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
284
285static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
286static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
287static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
288static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
289static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
290static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
291static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
292
293#define WM8994_DRC_SWITCH(xname, reg, shift) \
294 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
295 snd_soc_get_volsw, wm8994_put_drc_sw)
296
297static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299{
300 struct soc_mixer_control *mc =
301 (struct soc_mixer_control *)kcontrol->private_value;
302 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
303 int mask, ret;
304
305 /* Can't enable both ADC and DAC paths simultaneously */
306 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
307 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
308 WM8994_AIF1ADC1R_DRC_ENA_MASK;
309 else
310 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
311
312 ret = snd_soc_read(codec, mc->reg);
313 if (ret < 0)
314 return ret;
315 if (ret & mask)
316 return -EINVAL;
317
318 return snd_soc_put_volsw(kcontrol, ucontrol);
319}
320
321static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
322{
323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
324 struct wm8994 *control = wm8994->wm8994;
325 struct wm8994_pdata *pdata = &control->pdata;
326 int base = wm8994_drc_base[drc];
327 int cfg = wm8994->drc_cfg[drc];
328 int save, i;
329
330 /* Save any enables; the configuration should clear them. */
331 save = snd_soc_read(codec, base);
332 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
333 WM8994_AIF1ADC1R_DRC_ENA;
334
335 for (i = 0; i < WM8994_DRC_REGS; i++)
336 snd_soc_update_bits(codec, base + i, 0xffff,
337 pdata->drc_cfgs[cfg].regs[i]);
338
339 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
340 WM8994_AIF1ADC1L_DRC_ENA |
341 WM8994_AIF1ADC1R_DRC_ENA, save);
342}
343
344/* Icky as hell but saves code duplication */
345static int wm8994_get_drc(const char *name)
346{
347 if (strcmp(name, "AIF1DRC1 Mode") == 0)
348 return 0;
349 if (strcmp(name, "AIF1DRC2 Mode") == 0)
350 return 1;
351 if (strcmp(name, "AIF2DRC Mode") == 0)
352 return 2;
353 return -EINVAL;
354}
355
356static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
357 struct snd_ctl_elem_value *ucontrol)
358{
359 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
360 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
361 struct wm8994 *control = wm8994->wm8994;
362 struct wm8994_pdata *pdata = &control->pdata;
363 int drc = wm8994_get_drc(kcontrol->id.name);
364 int value = ucontrol->value.integer.value[0];
365
366 if (drc < 0)
367 return drc;
368
369 if (value >= pdata->num_drc_cfgs)
370 return -EINVAL;
371
372 wm8994->drc_cfg[drc] = value;
373
374 wm8994_set_drc(codec, drc);
375
376 return 0;
377}
378
379static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381{
382 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
384 int drc = wm8994_get_drc(kcontrol->id.name);
385
386 if (drc < 0)
387 return drc;
388 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
389
390 return 0;
391}
392
393static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
394{
395 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
396 struct wm8994 *control = wm8994->wm8994;
397 struct wm8994_pdata *pdata = &control->pdata;
398 int base = wm8994_retune_mobile_base[block];
399 int iface, best, best_val, save, i, cfg;
400
401 if (!pdata || !wm8994->num_retune_mobile_texts)
402 return;
403
404 switch (block) {
405 case 0:
406 case 1:
407 iface = 0;
408 break;
409 case 2:
410 iface = 1;
411 break;
412 default:
413 return;
414 }
415
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg = wm8994->retune_mobile_cfg[block];
419 best = 0;
420 best_val = INT_MAX;
421 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423 wm8994->retune_mobile_texts[cfg]) == 0 &&
424 abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]) < best_val) {
426 best = i;
427 best_val = abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]);
429 }
430 }
431
432 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433 block,
434 pdata->retune_mobile_cfgs[best].name,
435 pdata->retune_mobile_cfgs[best].rate,
436 wm8994->dac_rates[iface]);
437
438 /* The EQ will be disabled while reconfiguring it, remember the
439 * current configuration.
440 */
441 save = snd_soc_read(codec, base);
442 save &= WM8994_AIF1DAC1_EQ_ENA;
443
444 for (i = 0; i < WM8994_EQ_REGS; i++)
445 snd_soc_update_bits(codec, base + i, 0xffff,
446 pdata->retune_mobile_cfgs[best].regs[i]);
447
448 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
449}
450
451/* Icky as hell but saves code duplication */
452static int wm8994_get_retune_mobile_block(const char *name)
453{
454 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
455 return 0;
456 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
457 return 1;
458 if (strcmp(name, "AIF2 EQ Mode") == 0)
459 return 2;
460 return -EINVAL;
461}
462
463static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
465{
466 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
468 struct wm8994 *control = wm8994->wm8994;
469 struct wm8994_pdata *pdata = &control->pdata;
470 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
471 int value = ucontrol->value.integer.value[0];
472
473 if (block < 0)
474 return block;
475
476 if (value >= pdata->num_retune_mobile_cfgs)
477 return -EINVAL;
478
479 wm8994->retune_mobile_cfg[block] = value;
480
481 wm8994_set_retune_mobile(codec, block);
482
483 return 0;
484}
485
486static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
487 struct snd_ctl_elem_value *ucontrol)
488{
489 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
490 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
491 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
492
493 if (block < 0)
494 return block;
495
496 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
497
498 return 0;
499}
500
501static const char *aif_chan_src_text[] = {
502 "Left", "Right"
503};
504
505static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
506 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
507
508static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
509 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
510
511static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
512 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
513
514static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
515 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
516
517static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
518 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
519
520static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
521 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
522
523static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
524 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
525
526static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
527 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
528
529static const char *osr_text[] = {
530 "Low Power", "High Performance",
531};
532
533static SOC_ENUM_SINGLE_DECL(dac_osr,
534 WM8994_OVERSAMPLING, 0, osr_text);
535
536static SOC_ENUM_SINGLE_DECL(adc_osr,
537 WM8994_OVERSAMPLING, 1, osr_text);
538
539static const struct snd_kcontrol_new wm8994_snd_controls[] = {
540SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
541 WM8994_AIF1_ADC1_RIGHT_VOLUME,
542 1, 119, 0, digital_tlv),
543SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
544 WM8994_AIF1_ADC2_RIGHT_VOLUME,
545 1, 119, 0, digital_tlv),
546SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
547 WM8994_AIF2_ADC_RIGHT_VOLUME,
548 1, 119, 0, digital_tlv),
549
550SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
551SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
552SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
553SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
554
555SOC_ENUM("AIF1DACL Source", aif1dacl_src),
556SOC_ENUM("AIF1DACR Source", aif1dacr_src),
557SOC_ENUM("AIF2DACL Source", aif2dacl_src),
558SOC_ENUM("AIF2DACR Source", aif2dacr_src),
559
560SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
561 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
563 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
564SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
565 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
566
567SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
568SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
569
570SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
571SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
572SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
573
574WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
575WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
576WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
577
578WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
579WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
580WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
581
582WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
583WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
584WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
585
586SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
591 5, 12, 0, st_tlv),
592SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
593 0, 12, 0, st_tlv),
594SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
595SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
596
597SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
598SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
599
600SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
601SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
602
603SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
604SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
605
606SOC_ENUM("ADC OSR", adc_osr),
607SOC_ENUM("DAC OSR", dac_osr),
608
609SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
610 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
611SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
612 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
613
614SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
615 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
616SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
617 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
618
619SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
620 6, 1, 1, wm_hubs_spkmix_tlv),
621SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
622 2, 1, 1, wm_hubs_spkmix_tlv),
623
624SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
625 6, 1, 1, wm_hubs_spkmix_tlv),
626SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
627 2, 1, 1, wm_hubs_spkmix_tlv),
628
629SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
632 8, 1, 0),
633SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
634 10, 15, 0, wm8994_3d_tlv),
635SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
636 8, 1, 0),
637SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
638 10, 15, 0, wm8994_3d_tlv),
639SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
640 8, 1, 0),
641};
642
643static const struct snd_kcontrol_new wm8994_eq_controls[] = {
644SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
649 eq_tlv),
650SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
651 eq_tlv),
652SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
653 eq_tlv),
654
655SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
660 eq_tlv),
661SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
662 eq_tlv),
663SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
664 eq_tlv),
665
666SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
667 eq_tlv),
668SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
669 eq_tlv),
670SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
671 eq_tlv),
672SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
673 eq_tlv),
674SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
675 eq_tlv),
676};
677
678static const struct snd_kcontrol_new wm8994_drc_controls[] = {
679SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
680 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
681 WM8994_AIF1ADC1R_DRC_ENA),
682SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
683 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
684 WM8994_AIF1ADC2R_DRC_ENA),
685SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
686 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
687 WM8994_AIF2ADCR_DRC_ENA),
688};
689
690static const char *wm8958_ng_text[] = {
691 "30ms", "125ms", "250ms", "500ms",
692};
693
694static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
695 WM8958_AIF1_DAC1_NOISE_GATE,
696 WM8958_AIF1DAC1_NG_THR_SHIFT,
697 wm8958_ng_text);
698
699static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
700 WM8958_AIF1_DAC2_NOISE_GATE,
701 WM8958_AIF1DAC2_NG_THR_SHIFT,
702 wm8958_ng_text);
703
704static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
705 WM8958_AIF2_DAC_NOISE_GATE,
706 WM8958_AIF2DAC_NG_THR_SHIFT,
707 wm8958_ng_text);
708
709static const struct snd_kcontrol_new wm8958_snd_controls[] = {
710SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
711
712SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
713 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
714SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
715SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
717 7, 1, ng_tlv),
718
719SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
720 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
721SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
722SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
723 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
724 7, 1, ng_tlv),
725
726SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
727 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
728SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
729SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
730 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
731 7, 1, ng_tlv),
732};
733
734static const struct snd_kcontrol_new wm1811_snd_controls[] = {
735SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
736 mixin_boost_tlv),
737SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
738 mixin_boost_tlv),
739};
740
741/* We run all mode setting through a function to enforce audio mode */
742static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
743{
744 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
745
746 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
747 return;
748
749 if (wm8994->active_refcount)
750 mode = WM1811_JACKDET_MODE_AUDIO;
751
752 if (mode == wm8994->jackdet_mode)
753 return;
754
755 wm8994->jackdet_mode = mode;
756
757 /* Always use audio mode to detect while the system is active */
758 if (mode != WM1811_JACKDET_MODE_NONE)
759 mode = WM1811_JACKDET_MODE_AUDIO;
760
761 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
762 WM1811_JACKDET_MODE_MASK, mode);
763}
764
765static void active_reference(struct snd_soc_codec *codec)
766{
767 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
768
769 mutex_lock(&wm8994->accdet_lock);
770
771 wm8994->active_refcount++;
772
773 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
774 wm8994->active_refcount);
775
776 /* If we're using jack detection go into audio mode */
777 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
778
779 mutex_unlock(&wm8994->accdet_lock);
780}
781
782static void active_dereference(struct snd_soc_codec *codec)
783{
784 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
785 u16 mode;
786
787 mutex_lock(&wm8994->accdet_lock);
788
789 wm8994->active_refcount--;
790
791 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
792 wm8994->active_refcount);
793
794 if (wm8994->active_refcount == 0) {
795 /* Go into appropriate detection only mode */
796 if (wm8994->jack_mic || wm8994->mic_detecting)
797 mode = WM1811_JACKDET_MODE_MIC;
798 else
799 mode = WM1811_JACKDET_MODE_JACK;
800
801 wm1811_jackdet_set_mode(codec, mode);
802 }
803
804 mutex_unlock(&wm8994->accdet_lock);
805}
806
807static int clk_sys_event(struct snd_soc_dapm_widget *w,
808 struct snd_kcontrol *kcontrol, int event)
809{
810 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
811 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
812
813 switch (event) {
814 case SND_SOC_DAPM_PRE_PMU:
815 return configure_clock(codec);
816
817 case SND_SOC_DAPM_POST_PMU:
818 /*
819 * JACKDET won't run until we start the clock and it
820 * only reports deltas, make sure we notify the state
821 * up the stack on startup. Use a *very* generous
822 * timeout for paranoia, there's no urgency and we
823 * don't want false reports.
824 */
825 if (wm8994->jackdet && !wm8994->clk_has_run) {
826 queue_delayed_work(system_power_efficient_wq,
827 &wm8994->jackdet_bootstrap,
828 msecs_to_jiffies(1000));
829 wm8994->clk_has_run = true;
830 }
831 break;
832
833 case SND_SOC_DAPM_POST_PMD:
834 configure_clock(codec);
835 break;
836 }
837
838 return 0;
839}
840
841static void vmid_reference(struct snd_soc_codec *codec)
842{
843 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
844
845 pm_runtime_get_sync(codec->dev);
846
847 wm8994->vmid_refcount++;
848
849 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
850 wm8994->vmid_refcount);
851
852 if (wm8994->vmid_refcount == 1) {
853 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
854 WM8994_LINEOUT1_DISCH |
855 WM8994_LINEOUT2_DISCH, 0);
856
857 wm_hubs_vmid_ena(codec);
858
859 switch (wm8994->vmid_mode) {
860 default:
861 WARN_ON(NULL == "Invalid VMID mode");
862 case WM8994_VMID_NORMAL:
863 /* Startup bias, VMID ramp & buffer */
864 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
865 WM8994_BIAS_SRC |
866 WM8994_VMID_DISCH |
867 WM8994_STARTUP_BIAS_ENA |
868 WM8994_VMID_BUF_ENA |
869 WM8994_VMID_RAMP_MASK,
870 WM8994_BIAS_SRC |
871 WM8994_STARTUP_BIAS_ENA |
872 WM8994_VMID_BUF_ENA |
873 (0x2 << WM8994_VMID_RAMP_SHIFT));
874
875 /* Main bias enable, VMID=2x40k */
876 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
877 WM8994_BIAS_ENA |
878 WM8994_VMID_SEL_MASK,
879 WM8994_BIAS_ENA | 0x2);
880
881 msleep(300);
882
883 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884 WM8994_VMID_RAMP_MASK |
885 WM8994_BIAS_SRC,
886 0);
887 break;
888
889 case WM8994_VMID_FORCE:
890 /* Startup bias, slow VMID ramp & buffer */
891 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
892 WM8994_BIAS_SRC |
893 WM8994_VMID_DISCH |
894 WM8994_STARTUP_BIAS_ENA |
895 WM8994_VMID_BUF_ENA |
896 WM8994_VMID_RAMP_MASK,
897 WM8994_BIAS_SRC |
898 WM8994_STARTUP_BIAS_ENA |
899 WM8994_VMID_BUF_ENA |
900 (0x2 << WM8994_VMID_RAMP_SHIFT));
901
902 /* Main bias enable, VMID=2x40k */
903 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
904 WM8994_BIAS_ENA |
905 WM8994_VMID_SEL_MASK,
906 WM8994_BIAS_ENA | 0x2);
907
908 msleep(400);
909
910 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
911 WM8994_VMID_RAMP_MASK |
912 WM8994_BIAS_SRC,
913 0);
914 break;
915 }
916 }
917}
918
919static void vmid_dereference(struct snd_soc_codec *codec)
920{
921 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
922
923 wm8994->vmid_refcount--;
924
925 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
926 wm8994->vmid_refcount);
927
928 if (wm8994->vmid_refcount == 0) {
929 if (wm8994->hubs.lineout1_se)
930 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
931 WM8994_LINEOUT1N_ENA |
932 WM8994_LINEOUT1P_ENA,
933 WM8994_LINEOUT1N_ENA |
934 WM8994_LINEOUT1P_ENA);
935
936 if (wm8994->hubs.lineout2_se)
937 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
938 WM8994_LINEOUT2N_ENA |
939 WM8994_LINEOUT2P_ENA,
940 WM8994_LINEOUT2N_ENA |
941 WM8994_LINEOUT2P_ENA);
942
943 /* Start discharging VMID */
944 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
945 WM8994_BIAS_SRC |
946 WM8994_VMID_DISCH,
947 WM8994_BIAS_SRC |
948 WM8994_VMID_DISCH);
949
950 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
951 WM8994_VMID_SEL_MASK, 0);
952
953 msleep(400);
954
955 /* Active discharge */
956 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
957 WM8994_LINEOUT1_DISCH |
958 WM8994_LINEOUT2_DISCH,
959 WM8994_LINEOUT1_DISCH |
960 WM8994_LINEOUT2_DISCH);
961
962 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
963 WM8994_LINEOUT1N_ENA |
964 WM8994_LINEOUT1P_ENA |
965 WM8994_LINEOUT2N_ENA |
966 WM8994_LINEOUT2P_ENA, 0);
967
968 /* Switch off startup biases */
969 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
970 WM8994_BIAS_SRC |
971 WM8994_STARTUP_BIAS_ENA |
972 WM8994_VMID_BUF_ENA |
973 WM8994_VMID_RAMP_MASK, 0);
974
975 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
976 WM8994_VMID_SEL_MASK, 0);
977 }
978
979 pm_runtime_put(codec->dev);
980}
981
982static int vmid_event(struct snd_soc_dapm_widget *w,
983 struct snd_kcontrol *kcontrol, int event)
984{
985 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
986
987 switch (event) {
988 case SND_SOC_DAPM_PRE_PMU:
989 vmid_reference(codec);
990 break;
991
992 case SND_SOC_DAPM_POST_PMD:
993 vmid_dereference(codec);
994 break;
995 }
996
997 return 0;
998}
999
1000static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
1001{
1002 int source = 0; /* GCC flow analysis can't track enable */
1003 int reg, reg_r;
1004
1005 /* We also need the same AIF source for L/R and only one path */
1006 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1007 switch (reg) {
1008 case WM8994_AIF2DACL_TO_DAC1L:
1009 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1010 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 case WM8994_AIF1DAC2L_TO_DAC1L:
1013 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1014 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1015 break;
1016 case WM8994_AIF1DAC1L_TO_DAC1L:
1017 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1018 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1019 break;
1020 default:
1021 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1022 return false;
1023 }
1024
1025 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1026 if (reg_r != reg) {
1027 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1028 return false;
1029 }
1030
1031 /* Set the source up */
1032 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1033 WM8994_CP_DYN_SRC_SEL_MASK, source);
1034
1035 return true;
1036}
1037
1038static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1039 struct snd_kcontrol *kcontrol, int event)
1040{
1041 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1042 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1043 struct wm8994 *control = wm8994->wm8994;
1044 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1045 int i;
1046 int dac;
1047 int adc;
1048 int val;
1049
1050 switch (control->type) {
1051 case WM8994:
1052 case WM8958:
1053 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1054 break;
1055 default:
1056 break;
1057 }
1058
1059 switch (event) {
1060 case SND_SOC_DAPM_PRE_PMU:
1061 /* Don't enable timeslot 2 if not in use */
1062 if (wm8994->channels[0] <= 2)
1063 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1064
1065 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1066 if ((val & WM8994_AIF1ADCL_SRC) &&
1067 (val & WM8994_AIF1ADCR_SRC))
1068 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1069 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1070 !(val & WM8994_AIF1ADCR_SRC))
1071 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1072 else
1073 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1074 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1075
1076 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1077 if ((val & WM8994_AIF1DACL_SRC) &&
1078 (val & WM8994_AIF1DACR_SRC))
1079 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1080 else if (!(val & WM8994_AIF1DACL_SRC) &&
1081 !(val & WM8994_AIF1DACR_SRC))
1082 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1083 else
1084 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1085 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1086
1087 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1088 mask, adc);
1089 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1090 mask, dac);
1091 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1092 WM8994_AIF1DSPCLK_ENA |
1093 WM8994_SYSDSPCLK_ENA,
1094 WM8994_AIF1DSPCLK_ENA |
1095 WM8994_SYSDSPCLK_ENA);
1096 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1097 WM8994_AIF1ADC1R_ENA |
1098 WM8994_AIF1ADC1L_ENA |
1099 WM8994_AIF1ADC2R_ENA |
1100 WM8994_AIF1ADC2L_ENA);
1101 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1102 WM8994_AIF1DAC1R_ENA |
1103 WM8994_AIF1DAC1L_ENA |
1104 WM8994_AIF1DAC2R_ENA |
1105 WM8994_AIF1DAC2L_ENA);
1106 break;
1107
1108 case SND_SOC_DAPM_POST_PMU:
1109 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1110 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1111 snd_soc_read(codec,
1112 wm8994_vu_bits[i].reg));
1113 break;
1114
1115 case SND_SOC_DAPM_PRE_PMD:
1116 case SND_SOC_DAPM_POST_PMD:
1117 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1118 mask, 0);
1119 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1120 mask, 0);
1121
1122 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1123 if (val & WM8994_AIF2DSPCLK_ENA)
1124 val = WM8994_SYSDSPCLK_ENA;
1125 else
1126 val = 0;
1127 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1128 WM8994_SYSDSPCLK_ENA |
1129 WM8994_AIF1DSPCLK_ENA, val);
1130 break;
1131 }
1132
1133 return 0;
1134}
1135
1136static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1137 struct snd_kcontrol *kcontrol, int event)
1138{
1139 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1140 int i;
1141 int dac;
1142 int adc;
1143 int val;
1144
1145 switch (event) {
1146 case SND_SOC_DAPM_PRE_PMU:
1147 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1148 if ((val & WM8994_AIF2ADCL_SRC) &&
1149 (val & WM8994_AIF2ADCR_SRC))
1150 adc = WM8994_AIF2ADCR_ENA;
1151 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1152 !(val & WM8994_AIF2ADCR_SRC))
1153 adc = WM8994_AIF2ADCL_ENA;
1154 else
1155 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1156
1157
1158 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1159 if ((val & WM8994_AIF2DACL_SRC) &&
1160 (val & WM8994_AIF2DACR_SRC))
1161 dac = WM8994_AIF2DACR_ENA;
1162 else if (!(val & WM8994_AIF2DACL_SRC) &&
1163 !(val & WM8994_AIF2DACR_SRC))
1164 dac = WM8994_AIF2DACL_ENA;
1165 else
1166 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1167
1168 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1169 WM8994_AIF2ADCL_ENA |
1170 WM8994_AIF2ADCR_ENA, adc);
1171 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1172 WM8994_AIF2DACL_ENA |
1173 WM8994_AIF2DACR_ENA, dac);
1174 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1175 WM8994_AIF2DSPCLK_ENA |
1176 WM8994_SYSDSPCLK_ENA,
1177 WM8994_AIF2DSPCLK_ENA |
1178 WM8994_SYSDSPCLK_ENA);
1179 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1180 WM8994_AIF2ADCL_ENA |
1181 WM8994_AIF2ADCR_ENA,
1182 WM8994_AIF2ADCL_ENA |
1183 WM8994_AIF2ADCR_ENA);
1184 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1185 WM8994_AIF2DACL_ENA |
1186 WM8994_AIF2DACR_ENA,
1187 WM8994_AIF2DACL_ENA |
1188 WM8994_AIF2DACR_ENA);
1189 break;
1190
1191 case SND_SOC_DAPM_POST_PMU:
1192 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1193 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1194 snd_soc_read(codec,
1195 wm8994_vu_bits[i].reg));
1196 break;
1197
1198 case SND_SOC_DAPM_PRE_PMD:
1199 case SND_SOC_DAPM_POST_PMD:
1200 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1201 WM8994_AIF2DACL_ENA |
1202 WM8994_AIF2DACR_ENA, 0);
1203 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1204 WM8994_AIF2ADCL_ENA |
1205 WM8994_AIF2ADCR_ENA, 0);
1206
1207 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1208 if (val & WM8994_AIF1DSPCLK_ENA)
1209 val = WM8994_SYSDSPCLK_ENA;
1210 else
1211 val = 0;
1212 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1213 WM8994_SYSDSPCLK_ENA |
1214 WM8994_AIF2DSPCLK_ENA, val);
1215 break;
1216 }
1217
1218 return 0;
1219}
1220
1221static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1222 struct snd_kcontrol *kcontrol, int event)
1223{
1224 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1225 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1226
1227 switch (event) {
1228 case SND_SOC_DAPM_PRE_PMU:
1229 wm8994->aif1clk_enable = 1;
1230 break;
1231 case SND_SOC_DAPM_POST_PMD:
1232 wm8994->aif1clk_disable = 1;
1233 break;
1234 }
1235
1236 return 0;
1237}
1238
1239static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1240 struct snd_kcontrol *kcontrol, int event)
1241{
1242 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1243 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1244
1245 switch (event) {
1246 case SND_SOC_DAPM_PRE_PMU:
1247 wm8994->aif2clk_enable = 1;
1248 break;
1249 case SND_SOC_DAPM_POST_PMD:
1250 wm8994->aif2clk_disable = 1;
1251 break;
1252 }
1253
1254 return 0;
1255}
1256
1257static int late_enable_ev(struct snd_soc_dapm_widget *w,
1258 struct snd_kcontrol *kcontrol, int event)
1259{
1260 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1261 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1262
1263 switch (event) {
1264 case SND_SOC_DAPM_PRE_PMU:
1265 if (wm8994->aif1clk_enable) {
1266 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1267 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1268 WM8994_AIF1CLK_ENA_MASK,
1269 WM8994_AIF1CLK_ENA);
1270 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1271 wm8994->aif1clk_enable = 0;
1272 }
1273 if (wm8994->aif2clk_enable) {
1274 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1275 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1276 WM8994_AIF2CLK_ENA_MASK,
1277 WM8994_AIF2CLK_ENA);
1278 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1279 wm8994->aif2clk_enable = 0;
1280 }
1281 break;
1282 }
1283
1284 /* We may also have postponed startup of DSP, handle that. */
1285 wm8958_aif_ev(w, kcontrol, event);
1286
1287 return 0;
1288}
1289
1290static int late_disable_ev(struct snd_soc_dapm_widget *w,
1291 struct snd_kcontrol *kcontrol, int event)
1292{
1293 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1294 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1295
1296 switch (event) {
1297 case SND_SOC_DAPM_POST_PMD:
1298 if (wm8994->aif1clk_disable) {
1299 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1300 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1301 WM8994_AIF1CLK_ENA_MASK, 0);
1302 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1303 wm8994->aif1clk_disable = 0;
1304 }
1305 if (wm8994->aif2clk_disable) {
1306 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1307 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1308 WM8994_AIF2CLK_ENA_MASK, 0);
1309 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1310 wm8994->aif2clk_disable = 0;
1311 }
1312 break;
1313 }
1314
1315 return 0;
1316}
1317
1318static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1319 struct snd_kcontrol *kcontrol, int event)
1320{
1321 late_enable_ev(w, kcontrol, event);
1322 return 0;
1323}
1324
1325static int micbias_ev(struct snd_soc_dapm_widget *w,
1326 struct snd_kcontrol *kcontrol, int event)
1327{
1328 late_enable_ev(w, kcontrol, event);
1329 return 0;
1330}
1331
1332static int dac_ev(struct snd_soc_dapm_widget *w,
1333 struct snd_kcontrol *kcontrol, int event)
1334{
1335 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1336 unsigned int mask = 1 << w->shift;
1337
1338 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1339 mask, mask);
1340 return 0;
1341}
1342
1343static const char *adc_mux_text[] = {
1344 "ADC",
1345 "DMIC",
1346};
1347
1348static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1349
1350static const struct snd_kcontrol_new adcl_mux =
1351 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1352
1353static const struct snd_kcontrol_new adcr_mux =
1354 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1355
1356static const struct snd_kcontrol_new left_speaker_mixer[] = {
1357SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1358SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1359SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1360SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1361SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1362};
1363
1364static const struct snd_kcontrol_new right_speaker_mixer[] = {
1365SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1366SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1367SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1368SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1369SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1370};
1371
1372/* Debugging; dump chip status after DAPM transitions */
1373static int post_ev(struct snd_soc_dapm_widget *w,
1374 struct snd_kcontrol *kcontrol, int event)
1375{
1376 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1377 dev_dbg(codec->dev, "SRC status: %x\n",
1378 snd_soc_read(codec,
1379 WM8994_RATE_STATUS));
1380 return 0;
1381}
1382
1383static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1384SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1385 1, 1, 0),
1386SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1387 0, 1, 0),
1388};
1389
1390static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1391SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1392 1, 1, 0),
1393SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1394 0, 1, 0),
1395};
1396
1397static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1398SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1399 1, 1, 0),
1400SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1401 0, 1, 0),
1402};
1403
1404static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1405SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1406 1, 1, 0),
1407SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1408 0, 1, 0),
1409};
1410
1411static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1412SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1413 5, 1, 0),
1414SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1415 4, 1, 0),
1416SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1417 2, 1, 0),
1418SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1419 1, 1, 0),
1420SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1421 0, 1, 0),
1422};
1423
1424static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1425SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1426 5, 1, 0),
1427SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1428 4, 1, 0),
1429SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1430 2, 1, 0),
1431SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1432 1, 1, 0),
1433SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1434 0, 1, 0),
1435};
1436
1437#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1438 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1439 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1440
1441static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1442 struct snd_ctl_elem_value *ucontrol)
1443{
1444 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
1445 int ret;
1446
1447 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1448
1449 wm_hubs_update_class_w(codec);
1450
1451 return ret;
1452}
1453
1454static const struct snd_kcontrol_new dac1l_mix[] = {
1455WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 5, 1, 0),
1457WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458 4, 1, 0),
1459WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460 2, 1, 0),
1461WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1462 1, 1, 0),
1463WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1464 0, 1, 0),
1465};
1466
1467static const struct snd_kcontrol_new dac1r_mix[] = {
1468WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 5, 1, 0),
1470WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471 4, 1, 0),
1472WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473 2, 1, 0),
1474WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1475 1, 1, 0),
1476WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1477 0, 1, 0),
1478};
1479
1480static const char *sidetone_text[] = {
1481 "ADC/DMIC1", "DMIC2",
1482};
1483
1484static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1485 WM8994_SIDETONE, 0, sidetone_text);
1486
1487static const struct snd_kcontrol_new sidetone1_mux =
1488 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1489
1490static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1491 WM8994_SIDETONE, 1, sidetone_text);
1492
1493static const struct snd_kcontrol_new sidetone2_mux =
1494 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1495
1496static const char *aif1dac_text[] = {
1497 "AIF1DACDAT", "AIF3DACDAT",
1498};
1499
1500static const char *loopback_text[] = {
1501 "None", "ADCDAT",
1502};
1503
1504static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1505 WM8994_AIF1_CONTROL_2,
1506 WM8994_AIF1_LOOPBACK_SHIFT,
1507 loopback_text);
1508
1509static const struct snd_kcontrol_new aif1_loopback =
1510 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1511
1512static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1513 WM8994_AIF2_CONTROL_2,
1514 WM8994_AIF2_LOOPBACK_SHIFT,
1515 loopback_text);
1516
1517static const struct snd_kcontrol_new aif2_loopback =
1518 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1519
1520static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1521 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1522
1523static const struct snd_kcontrol_new aif1dac_mux =
1524 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1525
1526static const char *aif2dac_text[] = {
1527 "AIF2DACDAT", "AIF3DACDAT",
1528};
1529
1530static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1531 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1532
1533static const struct snd_kcontrol_new aif2dac_mux =
1534 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1535
1536static const char *aif2adc_text[] = {
1537 "AIF2ADCDAT", "AIF3DACDAT",
1538};
1539
1540static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1541 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1542
1543static const struct snd_kcontrol_new aif2adc_mux =
1544 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1545
1546static const char *aif3adc_text[] = {
1547 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1548};
1549
1550static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1551 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1552
1553static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1554 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1555
1556static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1557 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1558
1559static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1560 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1561
1562static const char *mono_pcm_out_text[] = {
1563 "None", "AIF2ADCL", "AIF2ADCR",
1564};
1565
1566static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1567 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1568
1569static const struct snd_kcontrol_new mono_pcm_out_mux =
1570 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1571
1572static const char *aif2dac_src_text[] = {
1573 "AIF2", "AIF3",
1574};
1575
1576/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1577static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1578 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1579
1580static const struct snd_kcontrol_new aif2dacl_src_mux =
1581 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1582
1583static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1584 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1585
1586static const struct snd_kcontrol_new aif2dacr_src_mux =
1587 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1588
1589static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1590SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1591 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1592SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1593 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1594
1595SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1597SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1598 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1599SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1600 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1601SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1602 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1603SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1604 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1605
1606SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1607 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1608 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1609SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1610 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1612SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1613 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1614SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1615 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1616
1617SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1618};
1619
1620static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1621SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1623 SND_SOC_DAPM_PRE_PMD),
1624SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1626 SND_SOC_DAPM_PRE_PMD),
1627SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1628SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1629 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1630SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1631 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1632SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1633SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1634};
1635
1636static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1637SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1638 dac_ev, SND_SOC_DAPM_PRE_PMU),
1639SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1640 dac_ev, SND_SOC_DAPM_PRE_PMU),
1641SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1642 dac_ev, SND_SOC_DAPM_PRE_PMU),
1643SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1644 dac_ev, SND_SOC_DAPM_PRE_PMU),
1645};
1646
1647static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1648SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1649SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1650SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1651SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1652};
1653
1654static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1655SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1656 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1657SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1658 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1659};
1660
1661static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1662SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1663SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1664};
1665
1666static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1667SND_SOC_DAPM_INPUT("DMIC1DAT"),
1668SND_SOC_DAPM_INPUT("DMIC2DAT"),
1669SND_SOC_DAPM_INPUT("Clock"),
1670
1671SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1672 SND_SOC_DAPM_PRE_PMU),
1673SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1674 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1675
1676SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1677 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1678 SND_SOC_DAPM_PRE_PMD),
1679
1680SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1681SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1682SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1683
1684SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1685 0, SND_SOC_NOPM, 9, 0),
1686SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1687 0, SND_SOC_NOPM, 8, 0),
1688SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1689 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1690 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1691SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1692 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1693 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1694
1695SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1696 0, SND_SOC_NOPM, 11, 0),
1697SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1698 0, SND_SOC_NOPM, 10, 0),
1699SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1700 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1701 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1702SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1703 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1704 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1705
1706SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1707 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1708SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1709 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1710
1711SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1712 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1713SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1714 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1715
1716SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1717 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1718SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1719 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1720
1721SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1722SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1723
1724SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1725 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1726SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1727 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1728
1729SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1730 SND_SOC_NOPM, 13, 0),
1731SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1732 SND_SOC_NOPM, 12, 0),
1733SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1734 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1735 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1736SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1737 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1738 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1739
1740SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1743SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1744
1745SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1746SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1747SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1748
1749SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1751
1752SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1753
1754SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1755SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1756SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1757SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1758
1759/* Power is done with the muxes since the ADC power also controls the
1760 * downsampling chain, the chip will automatically manage the analogue
1761 * specific portions.
1762 */
1763SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1764SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1765
1766SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1767SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1768
1769SND_SOC_DAPM_POST("Debug log", post_ev),
1770};
1771
1772static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1773SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1774};
1775
1776static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1777SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1778SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1779SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1780SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1781SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1782};
1783
1784static const struct snd_soc_dapm_route intercon[] = {
1785 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1786 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1787
1788 { "DSP1CLK", NULL, "CLK_SYS" },
1789 { "DSP2CLK", NULL, "CLK_SYS" },
1790 { "DSPINTCLK", NULL, "CLK_SYS" },
1791
1792 { "AIF1ADC1L", NULL, "AIF1CLK" },
1793 { "AIF1ADC1L", NULL, "DSP1CLK" },
1794 { "AIF1ADC1R", NULL, "AIF1CLK" },
1795 { "AIF1ADC1R", NULL, "DSP1CLK" },
1796 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1797
1798 { "AIF1DAC1L", NULL, "AIF1CLK" },
1799 { "AIF1DAC1L", NULL, "DSP1CLK" },
1800 { "AIF1DAC1R", NULL, "AIF1CLK" },
1801 { "AIF1DAC1R", NULL, "DSP1CLK" },
1802 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1803
1804 { "AIF1ADC2L", NULL, "AIF1CLK" },
1805 { "AIF1ADC2L", NULL, "DSP1CLK" },
1806 { "AIF1ADC2R", NULL, "AIF1CLK" },
1807 { "AIF1ADC2R", NULL, "DSP1CLK" },
1808 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1809
1810 { "AIF1DAC2L", NULL, "AIF1CLK" },
1811 { "AIF1DAC2L", NULL, "DSP1CLK" },
1812 { "AIF1DAC2R", NULL, "AIF1CLK" },
1813 { "AIF1DAC2R", NULL, "DSP1CLK" },
1814 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1815
1816 { "AIF2ADCL", NULL, "AIF2CLK" },
1817 { "AIF2ADCL", NULL, "DSP2CLK" },
1818 { "AIF2ADCR", NULL, "AIF2CLK" },
1819 { "AIF2ADCR", NULL, "DSP2CLK" },
1820 { "AIF2ADCR", NULL, "DSPINTCLK" },
1821
1822 { "AIF2DACL", NULL, "AIF2CLK" },
1823 { "AIF2DACL", NULL, "DSP2CLK" },
1824 { "AIF2DACR", NULL, "AIF2CLK" },
1825 { "AIF2DACR", NULL, "DSP2CLK" },
1826 { "AIF2DACR", NULL, "DSPINTCLK" },
1827
1828 { "DMIC1L", NULL, "DMIC1DAT" },
1829 { "DMIC1L", NULL, "CLK_SYS" },
1830 { "DMIC1R", NULL, "DMIC1DAT" },
1831 { "DMIC1R", NULL, "CLK_SYS" },
1832 { "DMIC2L", NULL, "DMIC2DAT" },
1833 { "DMIC2L", NULL, "CLK_SYS" },
1834 { "DMIC2R", NULL, "DMIC2DAT" },
1835 { "DMIC2R", NULL, "CLK_SYS" },
1836
1837 { "ADCL", NULL, "AIF1CLK" },
1838 { "ADCL", NULL, "DSP1CLK" },
1839 { "ADCL", NULL, "DSPINTCLK" },
1840
1841 { "ADCR", NULL, "AIF1CLK" },
1842 { "ADCR", NULL, "DSP1CLK" },
1843 { "ADCR", NULL, "DSPINTCLK" },
1844
1845 { "ADCL Mux", "ADC", "ADCL" },
1846 { "ADCL Mux", "DMIC", "DMIC1L" },
1847 { "ADCR Mux", "ADC", "ADCR" },
1848 { "ADCR Mux", "DMIC", "DMIC1R" },
1849
1850 { "DAC1L", NULL, "AIF1CLK" },
1851 { "DAC1L", NULL, "DSP1CLK" },
1852 { "DAC1L", NULL, "DSPINTCLK" },
1853
1854 { "DAC1R", NULL, "AIF1CLK" },
1855 { "DAC1R", NULL, "DSP1CLK" },
1856 { "DAC1R", NULL, "DSPINTCLK" },
1857
1858 { "DAC2L", NULL, "AIF2CLK" },
1859 { "DAC2L", NULL, "DSP2CLK" },
1860 { "DAC2L", NULL, "DSPINTCLK" },
1861
1862 { "DAC2R", NULL, "AIF2DACR" },
1863 { "DAC2R", NULL, "AIF2CLK" },
1864 { "DAC2R", NULL, "DSP2CLK" },
1865 { "DAC2R", NULL, "DSPINTCLK" },
1866
1867 { "TOCLK", NULL, "CLK_SYS" },
1868
1869 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1870 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1871 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1872
1873 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1874 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1875 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1876
1877 /* AIF1 outputs */
1878 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1879 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1880 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1881
1882 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1883 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1884 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1885
1886 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1887 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1888 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1889
1890 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1891 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1892 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1893
1894 /* Pin level routing for AIF3 */
1895 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1896 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1897 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1898 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1899
1900 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1901 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1902 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1903 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1904 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1905 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1906 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1907
1908 /* DAC1 inputs */
1909 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1910 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1911 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1912 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1913 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1914
1915 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1916 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1917 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1918 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1919 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1920
1921 /* DAC2/AIF2 outputs */
1922 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1923 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1924 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1925 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1926 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1927 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1928
1929 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1930 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1931 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1932 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1933 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1934 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1935
1936 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1937 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1938 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1939 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1940
1941 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1942
1943 /* AIF3 output */
1944 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1945 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1946 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1947 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1948 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1949 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1950 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1951 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1952
1953 /* Loopback */
1954 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1955 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1956 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1957 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1958
1959 /* Sidetone */
1960 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1961 { "Left Sidetone", "DMIC2", "DMIC2L" },
1962 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1963 { "Right Sidetone", "DMIC2", "DMIC2R" },
1964
1965 /* Output stages */
1966 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1967 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1968
1969 { "SPKL", "DAC1 Switch", "DAC1L" },
1970 { "SPKL", "DAC2 Switch", "DAC2L" },
1971
1972 { "SPKR", "DAC1 Switch", "DAC1R" },
1973 { "SPKR", "DAC2 Switch", "DAC2R" },
1974
1975 { "Left Headphone Mux", "DAC", "DAC1L" },
1976 { "Right Headphone Mux", "DAC", "DAC1R" },
1977};
1978
1979static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1980 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1981 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1982 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1983 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1984 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1985 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1986 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1987 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1988};
1989
1990static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1991 { "DAC1L", NULL, "DAC1L Mixer" },
1992 { "DAC1R", NULL, "DAC1R Mixer" },
1993 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1994 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1995};
1996
1997static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1998 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1999 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2000 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2001 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2002 { "MICBIAS1", NULL, "CLK_SYS" },
2003 { "MICBIAS1", NULL, "MICBIAS Supply" },
2004 { "MICBIAS2", NULL, "CLK_SYS" },
2005 { "MICBIAS2", NULL, "MICBIAS Supply" },
2006};
2007
2008static const struct snd_soc_dapm_route wm8994_intercon[] = {
2009 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2010 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2011 { "MICBIAS1", NULL, "VMID" },
2012 { "MICBIAS2", NULL, "VMID" },
2013};
2014
2015static const struct snd_soc_dapm_route wm8958_intercon[] = {
2016 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2017 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2018
2019 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2020 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2021 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2022 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2023
2024 { "AIF3DACDAT", NULL, "AIF3" },
2025 { "AIF3ADCDAT", NULL, "AIF3" },
2026
2027 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2028 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2029
2030 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2031};
2032
2033/* The size in bits of the FLL divide multiplied by 10
2034 * to allow rounding later */
2035#define FIXED_FLL_SIZE ((1 << 16) * 10)
2036
2037struct fll_div {
2038 u16 outdiv;
2039 u16 n;
2040 u16 k;
2041 u16 lambda;
2042 u16 clk_ref_div;
2043 u16 fll_fratio;
2044};
2045
2046static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2047 int freq_in, int freq_out)
2048{
2049 u64 Kpart;
2050 unsigned int K, Ndiv, Nmod, gcd_fll;
2051
2052 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2053
2054 /* Scale the input frequency down to <= 13.5MHz */
2055 fll->clk_ref_div = 0;
2056 while (freq_in > 13500000) {
2057 fll->clk_ref_div++;
2058 freq_in /= 2;
2059
2060 if (fll->clk_ref_div > 3)
2061 return -EINVAL;
2062 }
2063 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2064
2065 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2066 fll->outdiv = 3;
2067 while (freq_out * (fll->outdiv + 1) < 90000000) {
2068 fll->outdiv++;
2069 if (fll->outdiv > 63)
2070 return -EINVAL;
2071 }
2072 freq_out *= fll->outdiv + 1;
2073 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2074
2075 if (freq_in > 1000000) {
2076 fll->fll_fratio = 0;
2077 } else if (freq_in > 256000) {
2078 fll->fll_fratio = 1;
2079 freq_in *= 2;
2080 } else if (freq_in > 128000) {
2081 fll->fll_fratio = 2;
2082 freq_in *= 4;
2083 } else if (freq_in > 64000) {
2084 fll->fll_fratio = 3;
2085 freq_in *= 8;
2086 } else {
2087 fll->fll_fratio = 4;
2088 freq_in *= 16;
2089 }
2090 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2091
2092 /* Now, calculate N.K */
2093 Ndiv = freq_out / freq_in;
2094
2095 fll->n = Ndiv;
2096 Nmod = freq_out % freq_in;
2097 pr_debug("Nmod=%d\n", Nmod);
2098
2099 switch (control->type) {
2100 case WM8994:
2101 /* Calculate fractional part - scale up so we can round. */
2102 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2103
2104 do_div(Kpart, freq_in);
2105
2106 K = Kpart & 0xFFFFFFFF;
2107
2108 if ((K % 10) >= 5)
2109 K += 5;
2110
2111 /* Move down to proper range now rounding is done */
2112 fll->k = K / 10;
2113 fll->lambda = 0;
2114
2115 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2116 break;
2117
2118 default:
2119 gcd_fll = gcd(freq_out, freq_in);
2120
2121 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2122 fll->lambda = freq_in / gcd_fll;
2123
2124 }
2125
2126 return 0;
2127}
2128
2129static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2130 unsigned int freq_in, unsigned int freq_out)
2131{
2132 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2133 struct wm8994 *control = wm8994->wm8994;
2134 int reg_offset, ret;
2135 struct fll_div fll;
2136 u16 reg, clk1, aif_reg, aif_src;
2137 unsigned long timeout;
2138 bool was_enabled;
2139
2140 switch (id) {
2141 case WM8994_FLL1:
2142 reg_offset = 0;
2143 id = 0;
2144 aif_src = 0x10;
2145 break;
2146 case WM8994_FLL2:
2147 reg_offset = 0x20;
2148 id = 1;
2149 aif_src = 0x18;
2150 break;
2151 default:
2152 return -EINVAL;
2153 }
2154
2155 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2156 was_enabled = reg & WM8994_FLL1_ENA;
2157
2158 switch (src) {
2159 case 0:
2160 /* Allow no source specification when stopping */
2161 if (freq_out)
2162 return -EINVAL;
2163 src = wm8994->fll[id].src;
2164 break;
2165 case WM8994_FLL_SRC_MCLK1:
2166 case WM8994_FLL_SRC_MCLK2:
2167 case WM8994_FLL_SRC_LRCLK:
2168 case WM8994_FLL_SRC_BCLK:
2169 break;
2170 case WM8994_FLL_SRC_INTERNAL:
2171 freq_in = 12000000;
2172 freq_out = 12000000;
2173 break;
2174 default:
2175 return -EINVAL;
2176 }
2177
2178 /* Are we changing anything? */
2179 if (wm8994->fll[id].src == src &&
2180 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2181 return 0;
2182
2183 /* If we're stopping the FLL redo the old config - no
2184 * registers will actually be written but we avoid GCC flow
2185 * analysis bugs spewing warnings.
2186 */
2187 if (freq_out)
2188 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2189 else
2190 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2191 wm8994->fll[id].out);
2192 if (ret < 0)
2193 return ret;
2194
2195 /* Make sure that we're not providing SYSCLK right now */
2196 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2197 if (clk1 & WM8994_SYSCLK_SRC)
2198 aif_reg = WM8994_AIF2_CLOCKING_1;
2199 else
2200 aif_reg = WM8994_AIF1_CLOCKING_1;
2201 reg = snd_soc_read(codec, aif_reg);
2202
2203 if ((reg & WM8994_AIF1CLK_ENA) &&
2204 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2205 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2206 id + 1);
2207 return -EBUSY;
2208 }
2209
2210 /* We always need to disable the FLL while reconfiguring */
2211 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2212 WM8994_FLL1_ENA, 0);
2213
2214 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2215 freq_in == freq_out && freq_out) {
2216 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2217 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2218 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2219 goto out;
2220 }
2221
2222 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2223 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2224 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2225 WM8994_FLL1_OUTDIV_MASK |
2226 WM8994_FLL1_FRATIO_MASK, reg);
2227
2228 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2229 WM8994_FLL1_K_MASK, fll.k);
2230
2231 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2232 WM8994_FLL1_N_MASK,
2233 fll.n << WM8994_FLL1_N_SHIFT);
2234
2235 if (fll.lambda) {
2236 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2237 WM8958_FLL1_LAMBDA_MASK,
2238 fll.lambda);
2239 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2240 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2241 } else {
2242 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2243 WM8958_FLL1_EFS_ENA, 0);
2244 }
2245
2246 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2247 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2248 WM8994_FLL1_REFCLK_DIV_MASK |
2249 WM8994_FLL1_REFCLK_SRC_MASK,
2250 ((src == WM8994_FLL_SRC_INTERNAL)
2251 << WM8994_FLL1_FRC_NCO_SHIFT) |
2252 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2253 (src - 1));
2254
2255 /* Clear any pending completion from a previous failure */
2256 try_wait_for_completion(&wm8994->fll_locked[id]);
2257
2258 /* Enable (with fractional mode if required) */
2259 if (freq_out) {
2260 /* Enable VMID if we need it */
2261 if (!was_enabled) {
2262 active_reference(codec);
2263
2264 switch (control->type) {
2265 case WM8994:
2266 vmid_reference(codec);
2267 break;
2268 case WM8958:
2269 if (control->revision < 1)
2270 vmid_reference(codec);
2271 break;
2272 default:
2273 break;
2274 }
2275 }
2276
2277 reg = WM8994_FLL1_ENA;
2278
2279 if (fll.k)
2280 reg |= WM8994_FLL1_FRAC;
2281 if (src == WM8994_FLL_SRC_INTERNAL)
2282 reg |= WM8994_FLL1_OSC_ENA;
2283
2284 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2285 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2286 WM8994_FLL1_FRAC, reg);
2287
2288 if (wm8994->fll_locked_irq) {
2289 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2290 msecs_to_jiffies(10));
2291 if (timeout == 0)
2292 dev_warn(codec->dev,
2293 "Timed out waiting for FLL lock\n");
2294 } else {
2295 msleep(5);
2296 }
2297 } else {
2298 if (was_enabled) {
2299 switch (control->type) {
2300 case WM8994:
2301 vmid_dereference(codec);
2302 break;
2303 case WM8958:
2304 if (control->revision < 1)
2305 vmid_dereference(codec);
2306 break;
2307 default:
2308 break;
2309 }
2310
2311 active_dereference(codec);
2312 }
2313 }
2314
2315out:
2316 wm8994->fll[id].in = freq_in;
2317 wm8994->fll[id].out = freq_out;
2318 wm8994->fll[id].src = src;
2319
2320 configure_clock(codec);
2321
2322 /*
2323 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2324 * for detection.
2325 */
2326 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2327 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2328
2329 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2330 & WM8994_AIF1CLK_RATE_MASK;
2331 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2332 & WM8994_AIF1CLK_RATE_MASK;
2333
2334 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2335 WM8994_AIF1CLK_RATE_MASK, 0x1);
2336 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2337 WM8994_AIF2CLK_RATE_MASK, 0x1);
2338 } else if (wm8994->aifdiv[0]) {
2339 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2340 WM8994_AIF1CLK_RATE_MASK,
2341 wm8994->aifdiv[0]);
2342 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2343 WM8994_AIF2CLK_RATE_MASK,
2344 wm8994->aifdiv[1]);
2345
2346 wm8994->aifdiv[0] = 0;
2347 wm8994->aifdiv[1] = 0;
2348 }
2349
2350 return 0;
2351}
2352
2353static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2354{
2355 struct completion *completion = data;
2356
2357 complete(completion);
2358
2359 return IRQ_HANDLED;
2360}
2361
2362static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2363
2364static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2365 unsigned int freq_in, unsigned int freq_out)
2366{
2367 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2368}
2369
2370static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2371 int clk_id, unsigned int freq, int dir)
2372{
2373 struct snd_soc_codec *codec = dai->codec;
2374 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2375 int i;
2376
2377 switch (dai->id) {
2378 case 1:
2379 case 2:
2380 break;
2381
2382 default:
2383 /* AIF3 shares clocking with AIF1/2 */
2384 return -EINVAL;
2385 }
2386
2387 switch (clk_id) {
2388 case WM8994_SYSCLK_MCLK1:
2389 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2390 wm8994->mclk[0] = freq;
2391 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2392 dai->id, freq);
2393 break;
2394
2395 case WM8994_SYSCLK_MCLK2:
2396 /* TODO: Set GPIO AF */
2397 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2398 wm8994->mclk[1] = freq;
2399 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2400 dai->id, freq);
2401 break;
2402
2403 case WM8994_SYSCLK_FLL1:
2404 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2405 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2406 break;
2407
2408 case WM8994_SYSCLK_FLL2:
2409 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2410 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2411 break;
2412
2413 case WM8994_SYSCLK_OPCLK:
2414 /* Special case - a division (times 10) is given and
2415 * no effect on main clocking.
2416 */
2417 if (freq) {
2418 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2419 if (opclk_divs[i] == freq)
2420 break;
2421 if (i == ARRAY_SIZE(opclk_divs))
2422 return -EINVAL;
2423 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2424 WM8994_OPCLK_DIV_MASK, i);
2425 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2426 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2427 } else {
2428 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2429 WM8994_OPCLK_ENA, 0);
2430 }
2431
2432 default:
2433 return -EINVAL;
2434 }
2435
2436 configure_clock(codec);
2437
2438 /*
2439 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2440 * for detection.
2441 */
2442 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2443 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2444
2445 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2446 & WM8994_AIF1CLK_RATE_MASK;
2447 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2448 & WM8994_AIF1CLK_RATE_MASK;
2449
2450 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2451 WM8994_AIF1CLK_RATE_MASK, 0x1);
2452 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2453 WM8994_AIF2CLK_RATE_MASK, 0x1);
2454 } else if (wm8994->aifdiv[0]) {
2455 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2456 WM8994_AIF1CLK_RATE_MASK,
2457 wm8994->aifdiv[0]);
2458 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2459 WM8994_AIF2CLK_RATE_MASK,
2460 wm8994->aifdiv[1]);
2461
2462 wm8994->aifdiv[0] = 0;
2463 wm8994->aifdiv[1] = 0;
2464 }
2465
2466 return 0;
2467}
2468
2469static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2470 enum snd_soc_bias_level level)
2471{
2472 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2473 struct wm8994 *control = wm8994->wm8994;
2474
2475 wm_hubs_set_bias_level(codec, level);
2476
2477 switch (level) {
2478 case SND_SOC_BIAS_ON:
2479 break;
2480
2481 case SND_SOC_BIAS_PREPARE:
2482 /* MICBIAS into regulating mode */
2483 switch (control->type) {
2484 case WM8958:
2485 case WM1811:
2486 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2487 WM8958_MICB1_MODE, 0);
2488 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2489 WM8958_MICB2_MODE, 0);
2490 break;
2491 default:
2492 break;
2493 }
2494
2495 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2496 active_reference(codec);
2497 break;
2498
2499 case SND_SOC_BIAS_STANDBY:
2500 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2501 switch (control->type) {
2502 case WM8958:
2503 if (control->revision == 0) {
2504 /* Optimise performance for rev A */
2505 snd_soc_update_bits(codec,
2506 WM8958_CHARGE_PUMP_2,
2507 WM8958_CP_DISCH,
2508 WM8958_CP_DISCH);
2509 }
2510 break;
2511
2512 default:
2513 break;
2514 }
2515
2516 /* Discharge LINEOUT1 & 2 */
2517 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2518 WM8994_LINEOUT1_DISCH |
2519 WM8994_LINEOUT2_DISCH,
2520 WM8994_LINEOUT1_DISCH |
2521 WM8994_LINEOUT2_DISCH);
2522 }
2523
2524 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2525 active_dereference(codec);
2526
2527 /* MICBIAS into bypass mode on newer devices */
2528 switch (control->type) {
2529 case WM8958:
2530 case WM1811:
2531 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2532 WM8958_MICB1_MODE,
2533 WM8958_MICB1_MODE);
2534 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2535 WM8958_MICB2_MODE,
2536 WM8958_MICB2_MODE);
2537 break;
2538 default:
2539 break;
2540 }
2541 break;
2542
2543 case SND_SOC_BIAS_OFF:
2544 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2545 wm8994->cur_fw = NULL;
2546 break;
2547 }
2548
2549 codec->dapm.bias_level = level;
2550
2551 return 0;
2552}
2553
2554int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2555{
2556 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2557 struct snd_soc_dapm_context *dapm = &codec->dapm;
2558
2559 switch (mode) {
2560 case WM8994_VMID_NORMAL:
2561 snd_soc_dapm_mutex_lock(dapm);
2562
2563 if (wm8994->hubs.lineout1_se) {
2564 snd_soc_dapm_disable_pin_unlocked(dapm,
2565 "LINEOUT1N Driver");
2566 snd_soc_dapm_disable_pin_unlocked(dapm,
2567 "LINEOUT1P Driver");
2568 }
2569 if (wm8994->hubs.lineout2_se) {
2570 snd_soc_dapm_disable_pin_unlocked(dapm,
2571 "LINEOUT2N Driver");
2572 snd_soc_dapm_disable_pin_unlocked(dapm,
2573 "LINEOUT2P Driver");
2574 }
2575
2576 /* Do the sync with the old mode to allow it to clean up */
2577 snd_soc_dapm_sync_unlocked(dapm);
2578 wm8994->vmid_mode = mode;
2579
2580 snd_soc_dapm_mutex_unlock(dapm);
2581 break;
2582
2583 case WM8994_VMID_FORCE:
2584 snd_soc_dapm_mutex_lock(dapm);
2585
2586 if (wm8994->hubs.lineout1_se) {
2587 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2588 "LINEOUT1N Driver");
2589 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2590 "LINEOUT1P Driver");
2591 }
2592 if (wm8994->hubs.lineout2_se) {
2593 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2594 "LINEOUT2N Driver");
2595 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2596 "LINEOUT2P Driver");
2597 }
2598
2599 wm8994->vmid_mode = mode;
2600 snd_soc_dapm_sync_unlocked(dapm);
2601
2602 snd_soc_dapm_mutex_unlock(dapm);
2603 break;
2604
2605 default:
2606 return -EINVAL;
2607 }
2608
2609 return 0;
2610}
2611
2612static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2613{
2614 struct snd_soc_codec *codec = dai->codec;
2615 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2616 struct wm8994 *control = wm8994->wm8994;
2617 int ms_reg;
2618 int aif1_reg;
2619 int dac_reg;
2620 int adc_reg;
2621 int ms = 0;
2622 int aif1 = 0;
2623 int lrclk = 0;
2624
2625 switch (dai->id) {
2626 case 1:
2627 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2628 aif1_reg = WM8994_AIF1_CONTROL_1;
2629 dac_reg = WM8994_AIF1DAC_LRCLK;
2630 adc_reg = WM8994_AIF1ADC_LRCLK;
2631 break;
2632 case 2:
2633 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2634 aif1_reg = WM8994_AIF2_CONTROL_1;
2635 dac_reg = WM8994_AIF1DAC_LRCLK;
2636 adc_reg = WM8994_AIF1ADC_LRCLK;
2637 break;
2638 default:
2639 return -EINVAL;
2640 }
2641
2642 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2643 case SND_SOC_DAIFMT_CBS_CFS:
2644 break;
2645 case SND_SOC_DAIFMT_CBM_CFM:
2646 ms = WM8994_AIF1_MSTR;
2647 break;
2648 default:
2649 return -EINVAL;
2650 }
2651
2652 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2653 case SND_SOC_DAIFMT_DSP_B:
2654 aif1 |= WM8994_AIF1_LRCLK_INV;
2655 lrclk |= WM8958_AIF1_LRCLK_INV;
2656 case SND_SOC_DAIFMT_DSP_A:
2657 aif1 |= 0x18;
2658 break;
2659 case SND_SOC_DAIFMT_I2S:
2660 aif1 |= 0x10;
2661 break;
2662 case SND_SOC_DAIFMT_RIGHT_J:
2663 break;
2664 case SND_SOC_DAIFMT_LEFT_J:
2665 aif1 |= 0x8;
2666 break;
2667 default:
2668 return -EINVAL;
2669 }
2670
2671 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2672 case SND_SOC_DAIFMT_DSP_A:
2673 case SND_SOC_DAIFMT_DSP_B:
2674 /* frame inversion not valid for DSP modes */
2675 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2676 case SND_SOC_DAIFMT_NB_NF:
2677 break;
2678 case SND_SOC_DAIFMT_IB_NF:
2679 aif1 |= WM8994_AIF1_BCLK_INV;
2680 break;
2681 default:
2682 return -EINVAL;
2683 }
2684 break;
2685
2686 case SND_SOC_DAIFMT_I2S:
2687 case SND_SOC_DAIFMT_RIGHT_J:
2688 case SND_SOC_DAIFMT_LEFT_J:
2689 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2690 case SND_SOC_DAIFMT_NB_NF:
2691 break;
2692 case SND_SOC_DAIFMT_IB_IF:
2693 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2694 lrclk |= WM8958_AIF1_LRCLK_INV;
2695 break;
2696 case SND_SOC_DAIFMT_IB_NF:
2697 aif1 |= WM8994_AIF1_BCLK_INV;
2698 break;
2699 case SND_SOC_DAIFMT_NB_IF:
2700 aif1 |= WM8994_AIF1_LRCLK_INV;
2701 lrclk |= WM8958_AIF1_LRCLK_INV;
2702 break;
2703 default:
2704 return -EINVAL;
2705 }
2706 break;
2707 default:
2708 return -EINVAL;
2709 }
2710
2711 /* The AIF2 format configuration needs to be mirrored to AIF3
2712 * on WM8958 if it's in use so just do it all the time. */
2713 switch (control->type) {
2714 case WM1811:
2715 case WM8958:
2716 if (dai->id == 2)
2717 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2718 WM8994_AIF1_LRCLK_INV |
2719 WM8958_AIF3_FMT_MASK, aif1);
2720 break;
2721
2722 default:
2723 break;
2724 }
2725
2726 snd_soc_update_bits(codec, aif1_reg,
2727 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2728 WM8994_AIF1_FMT_MASK,
2729 aif1);
2730 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2731 ms);
2732 snd_soc_update_bits(codec, dac_reg,
2733 WM8958_AIF1_LRCLK_INV, lrclk);
2734 snd_soc_update_bits(codec, adc_reg,
2735 WM8958_AIF1_LRCLK_INV, lrclk);
2736
2737 return 0;
2738}
2739
2740static struct {
2741 int val, rate;
2742} srs[] = {
2743 { 0, 8000 },
2744 { 1, 11025 },
2745 { 2, 12000 },
2746 { 3, 16000 },
2747 { 4, 22050 },
2748 { 5, 24000 },
2749 { 6, 32000 },
2750 { 7, 44100 },
2751 { 8, 48000 },
2752 { 9, 88200 },
2753 { 10, 96000 },
2754};
2755
2756static int fs_ratios[] = {
2757 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2758};
2759
2760static int bclk_divs[] = {
2761 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2762 640, 880, 960, 1280, 1760, 1920
2763};
2764
2765static int wm8994_hw_params(struct snd_pcm_substream *substream,
2766 struct snd_pcm_hw_params *params,
2767 struct snd_soc_dai *dai)
2768{
2769 struct snd_soc_codec *codec = dai->codec;
2770 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2771 struct wm8994 *control = wm8994->wm8994;
2772 struct wm8994_pdata *pdata = &control->pdata;
2773 int aif1_reg;
2774 int aif2_reg;
2775 int bclk_reg;
2776 int lrclk_reg;
2777 int rate_reg;
2778 int aif1 = 0;
2779 int aif2 = 0;
2780 int bclk = 0;
2781 int lrclk = 0;
2782 int rate_val = 0;
2783 int id = dai->id - 1;
2784
2785 int i, cur_val, best_val, bclk_rate, best;
2786
2787 switch (dai->id) {
2788 case 1:
2789 aif1_reg = WM8994_AIF1_CONTROL_1;
2790 aif2_reg = WM8994_AIF1_CONTROL_2;
2791 bclk_reg = WM8994_AIF1_BCLK;
2792 rate_reg = WM8994_AIF1_RATE;
2793 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2794 wm8994->lrclk_shared[0]) {
2795 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2796 } else {
2797 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2798 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2799 }
2800 break;
2801 case 2:
2802 aif1_reg = WM8994_AIF2_CONTROL_1;
2803 aif2_reg = WM8994_AIF2_CONTROL_2;
2804 bclk_reg = WM8994_AIF2_BCLK;
2805 rate_reg = WM8994_AIF2_RATE;
2806 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2807 wm8994->lrclk_shared[1]) {
2808 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2809 } else {
2810 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2811 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2812 }
2813 break;
2814 default:
2815 return -EINVAL;
2816 }
2817
2818 bclk_rate = params_rate(params);
2819 switch (params_width(params)) {
2820 case 16:
2821 bclk_rate *= 16;
2822 break;
2823 case 20:
2824 bclk_rate *= 20;
2825 aif1 |= 0x20;
2826 break;
2827 case 24:
2828 bclk_rate *= 24;
2829 aif1 |= 0x40;
2830 break;
2831 case 32:
2832 bclk_rate *= 32;
2833 aif1 |= 0x60;
2834 break;
2835 default:
2836 return -EINVAL;
2837 }
2838
2839 wm8994->channels[id] = params_channels(params);
2840 if (pdata->max_channels_clocked[id] &&
2841 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2842 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2843 pdata->max_channels_clocked[id], wm8994->channels[id]);
2844 wm8994->channels[id] = pdata->max_channels_clocked[id];
2845 }
2846
2847 switch (wm8994->channels[id]) {
2848 case 1:
2849 case 2:
2850 bclk_rate *= 2;
2851 break;
2852 default:
2853 bclk_rate *= 4;
2854 break;
2855 }
2856
2857 /* Try to find an appropriate sample rate; look for an exact match. */
2858 for (i = 0; i < ARRAY_SIZE(srs); i++)
2859 if (srs[i].rate == params_rate(params))
2860 break;
2861 if (i == ARRAY_SIZE(srs))
2862 return -EINVAL;
2863 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2864
2865 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2866 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2867 dai->id, wm8994->aifclk[id], bclk_rate);
2868
2869 if (wm8994->channels[id] == 1 &&
2870 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2871 aif2 |= WM8994_AIF1_MONO;
2872
2873 if (wm8994->aifclk[id] == 0) {
2874 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2875 return -EINVAL;
2876 }
2877
2878 /* AIFCLK/fs ratio; look for a close match in either direction */
2879 best = 0;
2880 best_val = abs((fs_ratios[0] * params_rate(params))
2881 - wm8994->aifclk[id]);
2882 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2883 cur_val = abs((fs_ratios[i] * params_rate(params))
2884 - wm8994->aifclk[id]);
2885 if (cur_val >= best_val)
2886 continue;
2887 best = i;
2888 best_val = cur_val;
2889 }
2890 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2891 dai->id, fs_ratios[best]);
2892 rate_val |= best;
2893
2894 /* We may not get quite the right frequency if using
2895 * approximate clocks so look for the closest match that is
2896 * higher than the target (we need to ensure that there enough
2897 * BCLKs to clock out the samples).
2898 */
2899 best = 0;
2900 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2901 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2902 if (cur_val < 0) /* BCLK table is sorted */
2903 break;
2904 best = i;
2905 }
2906 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2907 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2908 bclk_divs[best], bclk_rate);
2909 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2910
2911 lrclk = bclk_rate / params_rate(params);
2912 if (!lrclk) {
2913 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2914 bclk_rate);
2915 return -EINVAL;
2916 }
2917 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2918 lrclk, bclk_rate / lrclk);
2919
2920 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2921 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2922 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2923 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2924 lrclk);
2925 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2926 WM8994_AIF1CLK_RATE_MASK, rate_val);
2927
2928 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2929 switch (dai->id) {
2930 case 1:
2931 wm8994->dac_rates[0] = params_rate(params);
2932 wm8994_set_retune_mobile(codec, 0);
2933 wm8994_set_retune_mobile(codec, 1);
2934 break;
2935 case 2:
2936 wm8994->dac_rates[1] = params_rate(params);
2937 wm8994_set_retune_mobile(codec, 2);
2938 break;
2939 }
2940 }
2941
2942 return 0;
2943}
2944
2945static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2946 struct snd_pcm_hw_params *params,
2947 struct snd_soc_dai *dai)
2948{
2949 struct snd_soc_codec *codec = dai->codec;
2950 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2951 struct wm8994 *control = wm8994->wm8994;
2952 int aif1_reg;
2953 int aif1 = 0;
2954
2955 switch (dai->id) {
2956 case 3:
2957 switch (control->type) {
2958 case WM1811:
2959 case WM8958:
2960 aif1_reg = WM8958_AIF3_CONTROL_1;
2961 break;
2962 default:
2963 return 0;
2964 }
2965 break;
2966 default:
2967 return 0;
2968 }
2969
2970 switch (params_width(params)) {
2971 case 16:
2972 break;
2973 case 20:
2974 aif1 |= 0x20;
2975 break;
2976 case 24:
2977 aif1 |= 0x40;
2978 break;
2979 case 32:
2980 aif1 |= 0x60;
2981 break;
2982 default:
2983 return -EINVAL;
2984 }
2985
2986 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2987}
2988
2989static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2990{
2991 struct snd_soc_codec *codec = codec_dai->codec;
2992 int mute_reg;
2993 int reg;
2994
2995 switch (codec_dai->id) {
2996 case 1:
2997 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2998 break;
2999 case 2:
3000 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3001 break;
3002 default:
3003 return -EINVAL;
3004 }
3005
3006 if (mute)
3007 reg = WM8994_AIF1DAC1_MUTE;
3008 else
3009 reg = 0;
3010
3011 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3012
3013 return 0;
3014}
3015
3016static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3017{
3018 struct snd_soc_codec *codec = codec_dai->codec;
3019 int reg, val, mask;
3020
3021 switch (codec_dai->id) {
3022 case 1:
3023 reg = WM8994_AIF1_MASTER_SLAVE;
3024 mask = WM8994_AIF1_TRI;
3025 break;
3026 case 2:
3027 reg = WM8994_AIF2_MASTER_SLAVE;
3028 mask = WM8994_AIF2_TRI;
3029 break;
3030 default:
3031 return -EINVAL;
3032 }
3033
3034 if (tristate)
3035 val = mask;
3036 else
3037 val = 0;
3038
3039 return snd_soc_update_bits(codec, reg, mask, val);
3040}
3041
3042static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3043{
3044 struct snd_soc_codec *codec = dai->codec;
3045
3046 /* Disable the pulls on the AIF if we're using it to save power. */
3047 snd_soc_update_bits(codec, WM8994_GPIO_3,
3048 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3049 snd_soc_update_bits(codec, WM8994_GPIO_4,
3050 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3051 snd_soc_update_bits(codec, WM8994_GPIO_5,
3052 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3053
3054 return 0;
3055}
3056
3057#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3058
3059#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3060 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3061
3062static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3063 .set_sysclk = wm8994_set_dai_sysclk,
3064 .set_fmt = wm8994_set_dai_fmt,
3065 .hw_params = wm8994_hw_params,
3066 .digital_mute = wm8994_aif_mute,
3067 .set_pll = wm8994_set_fll,
3068 .set_tristate = wm8994_set_tristate,
3069};
3070
3071static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3072 .set_sysclk = wm8994_set_dai_sysclk,
3073 .set_fmt = wm8994_set_dai_fmt,
3074 .hw_params = wm8994_hw_params,
3075 .digital_mute = wm8994_aif_mute,
3076 .set_pll = wm8994_set_fll,
3077 .set_tristate = wm8994_set_tristate,
3078};
3079
3080static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3081 .hw_params = wm8994_aif3_hw_params,
3082};
3083
3084static struct snd_soc_dai_driver wm8994_dai[] = {
3085 {
3086 .name = "wm8994-aif1",
3087 .id = 1,
3088 .playback = {
3089 .stream_name = "AIF1 Playback",
3090 .channels_min = 1,
3091 .channels_max = 2,
3092 .rates = WM8994_RATES,
3093 .formats = WM8994_FORMATS,
3094 .sig_bits = 24,
3095 },
3096 .capture = {
3097 .stream_name = "AIF1 Capture",
3098 .channels_min = 1,
3099 .channels_max = 2,
3100 .rates = WM8994_RATES,
3101 .formats = WM8994_FORMATS,
3102 .sig_bits = 24,
3103 },
3104 .ops = &wm8994_aif1_dai_ops,
3105 },
3106 {
3107 .name = "wm8994-aif2",
3108 .id = 2,
3109 .playback = {
3110 .stream_name = "AIF2 Playback",
3111 .channels_min = 1,
3112 .channels_max = 2,
3113 .rates = WM8994_RATES,
3114 .formats = WM8994_FORMATS,
3115 .sig_bits = 24,
3116 },
3117 .capture = {
3118 .stream_name = "AIF2 Capture",
3119 .channels_min = 1,
3120 .channels_max = 2,
3121 .rates = WM8994_RATES,
3122 .formats = WM8994_FORMATS,
3123 .sig_bits = 24,
3124 },
3125 .probe = wm8994_aif2_probe,
3126 .ops = &wm8994_aif2_dai_ops,
3127 },
3128 {
3129 .name = "wm8994-aif3",
3130 .id = 3,
3131 .playback = {
3132 .stream_name = "AIF3 Playback",
3133 .channels_min = 1,
3134 .channels_max = 2,
3135 .rates = WM8994_RATES,
3136 .formats = WM8994_FORMATS,
3137 .sig_bits = 24,
3138 },
3139 .capture = {
3140 .stream_name = "AIF3 Capture",
3141 .channels_min = 1,
3142 .channels_max = 2,
3143 .rates = WM8994_RATES,
3144 .formats = WM8994_FORMATS,
3145 .sig_bits = 24,
3146 },
3147 .ops = &wm8994_aif3_dai_ops,
3148 }
3149};
3150
3151#ifdef CONFIG_PM
3152static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3153{
3154 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3155 int i, ret;
3156
3157 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3158 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3159 sizeof(struct wm8994_fll_config));
3160 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3161 if (ret < 0)
3162 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3163 i + 1, ret);
3164 }
3165
3166 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3167
3168 return 0;
3169}
3170
3171static int wm8994_codec_resume(struct snd_soc_codec *codec)
3172{
3173 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3174 int i, ret;
3175
3176 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3177 if (!wm8994->fll_suspend[i].out)
3178 continue;
3179
3180 ret = _wm8994_set_fll(codec, i + 1,
3181 wm8994->fll_suspend[i].src,
3182 wm8994->fll_suspend[i].in,
3183 wm8994->fll_suspend[i].out);
3184 if (ret < 0)
3185 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3186 i + 1, ret);
3187 }
3188
3189 return 0;
3190}
3191#else
3192#define wm8994_codec_suspend NULL
3193#define wm8994_codec_resume NULL
3194#endif
3195
3196static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3197{
3198 struct snd_soc_codec *codec = wm8994->hubs.codec;
3199 struct wm8994 *control = wm8994->wm8994;
3200 struct wm8994_pdata *pdata = &control->pdata;
3201 struct snd_kcontrol_new controls[] = {
3202 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3203 wm8994->retune_mobile_enum,
3204 wm8994_get_retune_mobile_enum,
3205 wm8994_put_retune_mobile_enum),
3206 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3207 wm8994->retune_mobile_enum,
3208 wm8994_get_retune_mobile_enum,
3209 wm8994_put_retune_mobile_enum),
3210 SOC_ENUM_EXT("AIF2 EQ Mode",
3211 wm8994->retune_mobile_enum,
3212 wm8994_get_retune_mobile_enum,
3213 wm8994_put_retune_mobile_enum),
3214 };
3215 int ret, i, j;
3216 const char **t;
3217
3218 /* We need an array of texts for the enum API but the number
3219 * of texts is likely to be less than the number of
3220 * configurations due to the sample rate dependency of the
3221 * configurations. */
3222 wm8994->num_retune_mobile_texts = 0;
3223 wm8994->retune_mobile_texts = NULL;
3224 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3225 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3226 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3227 wm8994->retune_mobile_texts[j]) == 0)
3228 break;
3229 }
3230
3231 if (j != wm8994->num_retune_mobile_texts)
3232 continue;
3233
3234 /* Expand the array... */
3235 t = krealloc(wm8994->retune_mobile_texts,
3236 sizeof(char *) *
3237 (wm8994->num_retune_mobile_texts + 1),
3238 GFP_KERNEL);
3239 if (t == NULL)
3240 continue;
3241
3242 /* ...store the new entry... */
3243 t[wm8994->num_retune_mobile_texts] =
3244 pdata->retune_mobile_cfgs[i].name;
3245
3246 /* ...and remember the new version. */
3247 wm8994->num_retune_mobile_texts++;
3248 wm8994->retune_mobile_texts = t;
3249 }
3250
3251 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3252 wm8994->num_retune_mobile_texts);
3253
3254 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3255 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3256
3257 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3258 ARRAY_SIZE(controls));
3259 if (ret != 0)
3260 dev_err(wm8994->hubs.codec->dev,
3261 "Failed to add ReTune Mobile controls: %d\n", ret);
3262}
3263
3264static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3265{
3266 struct snd_soc_codec *codec = wm8994->hubs.codec;
3267 struct wm8994 *control = wm8994->wm8994;
3268 struct wm8994_pdata *pdata = &control->pdata;
3269 int ret, i;
3270
3271 if (!pdata)
3272 return;
3273
3274 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3275 pdata->lineout2_diff,
3276 pdata->lineout1fb,
3277 pdata->lineout2fb,
3278 pdata->jd_scthr,
3279 pdata->jd_thr,
3280 pdata->micb1_delay,
3281 pdata->micb2_delay,
3282 pdata->micbias1_lvl,
3283 pdata->micbias2_lvl);
3284
3285 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3286
3287 if (pdata->num_drc_cfgs) {
3288 struct snd_kcontrol_new controls[] = {
3289 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3290 wm8994_get_drc_enum, wm8994_put_drc_enum),
3291 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3292 wm8994_get_drc_enum, wm8994_put_drc_enum),
3293 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3294 wm8994_get_drc_enum, wm8994_put_drc_enum),
3295 };
3296
3297 /* We need an array of texts for the enum API */
3298 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3299 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3300 if (!wm8994->drc_texts)
3301 return;
3302
3303 for (i = 0; i < pdata->num_drc_cfgs; i++)
3304 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3305
3306 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3307 wm8994->drc_enum.texts = wm8994->drc_texts;
3308
3309 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3310 ARRAY_SIZE(controls));
3311 for (i = 0; i < WM8994_NUM_DRC; i++)
3312 wm8994_set_drc(codec, i);
3313 } else {
3314 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3315 wm8994_drc_controls,
3316 ARRAY_SIZE(wm8994_drc_controls));
3317 }
3318
3319 if (ret != 0)
3320 dev_err(wm8994->hubs.codec->dev,
3321 "Failed to add DRC mode controls: %d\n", ret);
3322
3323
3324 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3325 pdata->num_retune_mobile_cfgs);
3326
3327 if (pdata->num_retune_mobile_cfgs)
3328 wm8994_handle_retune_mobile_pdata(wm8994);
3329 else
3330 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3331 ARRAY_SIZE(wm8994_eq_controls));
3332
3333 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3334 if (pdata->micbias[i]) {
3335 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3336 pdata->micbias[i] & 0xffff);
3337 }
3338 }
3339}
3340
3341/**
3342 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3343 *
3344 * @codec: WM8994 codec
3345 * @jack: jack to report detection events on
3346 * @micbias: microphone bias to detect on
3347 *
3348 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3349 * being used to bring out signals to the processor then only platform
3350 * data configuration is needed for WM8994 and processor GPIOs should
3351 * be configured using snd_soc_jack_add_gpios() instead.
3352 *
3353 * Configuration of detection levels is available via the micbias1_lvl
3354 * and micbias2_lvl platform data members.
3355 */
3356int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3357 int micbias)
3358{
3359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3360 struct wm8994_micdet *micdet;
3361 struct wm8994 *control = wm8994->wm8994;
3362 int reg, ret;
3363
3364 if (control->type != WM8994) {
3365 dev_warn(codec->dev, "Not a WM8994\n");
3366 return -EINVAL;
3367 }
3368
3369 switch (micbias) {
3370 case 1:
3371 micdet = &wm8994->micdet[0];
3372 if (jack)
3373 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3374 "MICBIAS1");
3375 else
3376 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3377 "MICBIAS1");
3378 break;
3379 case 2:
3380 micdet = &wm8994->micdet[1];
3381 if (jack)
3382 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3383 "MICBIAS1");
3384 else
3385 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3386 "MICBIAS1");
3387 break;
3388 default:
3389 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3390 return -EINVAL;
3391 }
3392
3393 if (ret != 0)
3394 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3395 micbias, ret);
3396
3397 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3398 micbias, jack);
3399
3400 /* Store the configuration */
3401 micdet->jack = jack;
3402 micdet->detecting = true;
3403
3404 /* If either of the jacks is set up then enable detection */
3405 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3406 reg = WM8994_MICD_ENA;
3407 else
3408 reg = 0;
3409
3410 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3411
3412 /* enable MICDET and MICSHRT deboune */
3413 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3414 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3415 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3416 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3417
3418 snd_soc_dapm_sync(&codec->dapm);
3419
3420 return 0;
3421}
3422EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3423
3424static void wm8994_mic_work(struct work_struct *work)
3425{
3426 struct wm8994_priv *priv = container_of(work,
3427 struct wm8994_priv,
3428 mic_work.work);
3429 struct regmap *regmap = priv->wm8994->regmap;
3430 struct device *dev = priv->wm8994->dev;
3431 unsigned int reg;
3432 int ret;
3433 int report;
3434
3435 pm_runtime_get_sync(dev);
3436
3437 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3438 if (ret < 0) {
3439 dev_err(dev, "Failed to read microphone status: %d\n",
3440 ret);
3441 pm_runtime_put(dev);
3442 return;
3443 }
3444
3445 dev_dbg(dev, "Microphone status: %x\n", reg);
3446
3447 report = 0;
3448 if (reg & WM8994_MIC1_DET_STS) {
3449 if (priv->micdet[0].detecting)
3450 report = SND_JACK_HEADSET;
3451 }
3452 if (reg & WM8994_MIC1_SHRT_STS) {
3453 if (priv->micdet[0].detecting)
3454 report = SND_JACK_HEADPHONE;
3455 else
3456 report |= SND_JACK_BTN_0;
3457 }
3458 if (report)
3459 priv->micdet[0].detecting = false;
3460 else
3461 priv->micdet[0].detecting = true;
3462
3463 snd_soc_jack_report(priv->micdet[0].jack, report,
3464 SND_JACK_HEADSET | SND_JACK_BTN_0);
3465
3466 report = 0;
3467 if (reg & WM8994_MIC2_DET_STS) {
3468 if (priv->micdet[1].detecting)
3469 report = SND_JACK_HEADSET;
3470 }
3471 if (reg & WM8994_MIC2_SHRT_STS) {
3472 if (priv->micdet[1].detecting)
3473 report = SND_JACK_HEADPHONE;
3474 else
3475 report |= SND_JACK_BTN_0;
3476 }
3477 if (report)
3478 priv->micdet[1].detecting = false;
3479 else
3480 priv->micdet[1].detecting = true;
3481
3482 snd_soc_jack_report(priv->micdet[1].jack, report,
3483 SND_JACK_HEADSET | SND_JACK_BTN_0);
3484
3485 pm_runtime_put(dev);
3486}
3487
3488static irqreturn_t wm8994_mic_irq(int irq, void *data)
3489{
3490 struct wm8994_priv *priv = data;
3491 struct snd_soc_codec *codec = priv->hubs.codec;
3492
3493#ifndef CONFIG_SND_SOC_WM8994_MODULE
3494 trace_snd_soc_jack_irq(dev_name(codec->dev));
3495#endif
3496
3497 pm_wakeup_event(codec->dev, 300);
3498
3499 queue_delayed_work(system_power_efficient_wq,
3500 &priv->mic_work, msecs_to_jiffies(250));
3501
3502 return IRQ_HANDLED;
3503}
3504
3505/* Should be called with accdet_lock held */
3506static void wm1811_micd_stop(struct snd_soc_codec *codec)
3507{
3508 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3509
3510 if (!wm8994->jackdet)
3511 return;
3512
3513 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3514
3515 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3516
3517 if (wm8994->wm8994->pdata.jd_ext_cap)
3518 snd_soc_dapm_disable_pin(&codec->dapm,
3519 "MICBIAS2");
3520}
3521
3522static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3523{
3524 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3525 int report;
3526
3527 report = 0;
3528 if (status & 0x4)
3529 report |= SND_JACK_BTN_0;
3530
3531 if (status & 0x8)
3532 report |= SND_JACK_BTN_1;
3533
3534 if (status & 0x10)
3535 report |= SND_JACK_BTN_2;
3536
3537 if (status & 0x20)
3538 report |= SND_JACK_BTN_3;
3539
3540 if (status & 0x40)
3541 report |= SND_JACK_BTN_4;
3542
3543 if (status & 0x80)
3544 report |= SND_JACK_BTN_5;
3545
3546 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3547 wm8994->btn_mask);
3548}
3549
3550static void wm8958_open_circuit_work(struct work_struct *work)
3551{
3552 struct wm8994_priv *wm8994 = container_of(work,
3553 struct wm8994_priv,
3554 open_circuit_work.work);
3555 struct device *dev = wm8994->wm8994->dev;
3556
3557 mutex_lock(&wm8994->accdet_lock);
3558
3559 wm1811_micd_stop(wm8994->hubs.codec);
3560
3561 dev_dbg(dev, "Reporting open circuit\n");
3562
3563 wm8994->jack_mic = false;
3564 wm8994->mic_detecting = true;
3565
3566 wm8958_micd_set_rate(wm8994->hubs.codec);
3567
3568 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3569 wm8994->btn_mask |
3570 SND_JACK_HEADSET);
3571
3572 mutex_unlock(&wm8994->accdet_lock);
3573}
3574
3575static void wm8958_mic_id(void *data, u16 status)
3576{
3577 struct snd_soc_codec *codec = data;
3578 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3579
3580 /* Either nothing present or just starting detection */
3581 if (!(status & WM8958_MICD_STS)) {
3582 /* If nothing present then clear our statuses */
3583 dev_dbg(codec->dev, "Detected open circuit\n");
3584
3585 queue_delayed_work(system_power_efficient_wq,
3586 &wm8994->open_circuit_work,
3587 msecs_to_jiffies(2500));
3588 return;
3589 }
3590
3591 /* If the measurement is showing a high impedence we've got a
3592 * microphone.
3593 */
3594 if (status & 0x600) {
3595 dev_dbg(codec->dev, "Detected microphone\n");
3596
3597 wm8994->mic_detecting = false;
3598 wm8994->jack_mic = true;
3599
3600 wm8958_micd_set_rate(codec);
3601
3602 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3603 SND_JACK_HEADSET);
3604 }
3605
3606
3607 if (status & 0xfc) {
3608 dev_dbg(codec->dev, "Detected headphone\n");
3609 wm8994->mic_detecting = false;
3610
3611 wm8958_micd_set_rate(codec);
3612
3613 /* If we have jackdet that will detect removal */
3614 wm1811_micd_stop(codec);
3615
3616 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3617 SND_JACK_HEADSET);
3618 }
3619}
3620
3621/* Deferred mic detection to allow for extra settling time */
3622static void wm1811_mic_work(struct work_struct *work)
3623{
3624 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3625 mic_work.work);
3626 struct wm8994 *control = wm8994->wm8994;
3627 struct snd_soc_codec *codec = wm8994->hubs.codec;
3628
3629 pm_runtime_get_sync(codec->dev);
3630
3631 /* If required for an external cap force MICBIAS on */
3632 if (control->pdata.jd_ext_cap) {
3633 snd_soc_dapm_force_enable_pin(&codec->dapm,
3634 "MICBIAS2");
3635 snd_soc_dapm_sync(&codec->dapm);
3636 }
3637
3638 mutex_lock(&wm8994->accdet_lock);
3639
3640 dev_dbg(codec->dev, "Starting mic detection\n");
3641
3642 /* Use a user-supplied callback if we have one */
3643 if (wm8994->micd_cb) {
3644 wm8994->micd_cb(wm8994->micd_cb_data);
3645 } else {
3646 /*
3647 * Start off measument of microphone impedence to find out
3648 * what's actually there.
3649 */
3650 wm8994->mic_detecting = true;
3651 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3652
3653 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3654 WM8958_MICD_ENA, WM8958_MICD_ENA);
3655 }
3656
3657 mutex_unlock(&wm8994->accdet_lock);
3658
3659 pm_runtime_put(codec->dev);
3660}
3661
3662static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3663{
3664 struct wm8994_priv *wm8994 = data;
3665 struct wm8994 *control = wm8994->wm8994;
3666 struct snd_soc_codec *codec = wm8994->hubs.codec;
3667 int reg, delay;
3668 bool present;
3669
3670 pm_runtime_get_sync(codec->dev);
3671
3672 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3673
3674 mutex_lock(&wm8994->accdet_lock);
3675
3676 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3677 if (reg < 0) {
3678 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3679 mutex_unlock(&wm8994->accdet_lock);
3680 pm_runtime_put(codec->dev);
3681 return IRQ_NONE;
3682 }
3683
3684 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3685
3686 present = reg & WM1811_JACKDET_LVL;
3687
3688 if (present) {
3689 dev_dbg(codec->dev, "Jack detected\n");
3690
3691 wm8958_micd_set_rate(codec);
3692
3693 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3694 WM8958_MICB2_DISCH, 0);
3695
3696 /* Disable debounce while inserted */
3697 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3698 WM1811_JACKDET_DB, 0);
3699
3700 delay = control->pdata.micdet_delay;
3701 queue_delayed_work(system_power_efficient_wq,
3702 &wm8994->mic_work,
3703 msecs_to_jiffies(delay));
3704 } else {
3705 dev_dbg(codec->dev, "Jack not detected\n");
3706
3707 cancel_delayed_work_sync(&wm8994->mic_work);
3708
3709 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3710 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3711
3712 /* Enable debounce while removed */
3713 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3714 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3715
3716 wm8994->mic_detecting = false;
3717 wm8994->jack_mic = false;
3718 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3719 WM8958_MICD_ENA, 0);
3720 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3721 }
3722
3723 mutex_unlock(&wm8994->accdet_lock);
3724
3725 /* Turn off MICBIAS if it was on for an external cap */
3726 if (control->pdata.jd_ext_cap && !present)
3727 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3728
3729 if (present)
3730 snd_soc_jack_report(wm8994->micdet[0].jack,
3731 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3732 else
3733 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3734 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3735 wm8994->btn_mask);
3736
3737 /* Since we only report deltas force an update, ensures we
3738 * avoid bootstrapping issues with the core. */
3739 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3740
3741 pm_runtime_put(codec->dev);
3742 return IRQ_HANDLED;
3743}
3744
3745static void wm1811_jackdet_bootstrap(struct work_struct *work)
3746{
3747 struct wm8994_priv *wm8994 = container_of(work,
3748 struct wm8994_priv,
3749 jackdet_bootstrap.work);
3750 wm1811_jackdet_irq(0, wm8994);
3751}
3752
3753/**
3754 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3755 *
3756 * @codec: WM8958 codec
3757 * @jack: jack to report detection events on
3758 *
3759 * Enable microphone detection functionality for the WM8958. By
3760 * default simple detection which supports the detection of up to 6
3761 * buttons plus video and microphone functionality is supported.
3762 *
3763 * The WM8958 has an advanced jack detection facility which is able to
3764 * support complex accessory detection, especially when used in
3765 * conjunction with external circuitry. In order to provide maximum
3766 * flexiblity a callback is provided which allows a completely custom
3767 * detection algorithm.
3768 */
3769int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3770 wm1811_micdet_cb det_cb, void *det_cb_data,
3771 wm1811_mic_id_cb id_cb, void *id_cb_data)
3772{
3773 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3774 struct wm8994 *control = wm8994->wm8994;
3775 u16 micd_lvl_sel;
3776
3777 switch (control->type) {
3778 case WM1811:
3779 case WM8958:
3780 break;
3781 default:
3782 return -EINVAL;
3783 }
3784
3785 if (jack) {
3786 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3787 snd_soc_dapm_sync(&codec->dapm);
3788
3789 wm8994->micdet[0].jack = jack;
3790
3791 if (det_cb) {
3792 wm8994->micd_cb = det_cb;
3793 wm8994->micd_cb_data = det_cb_data;
3794 } else {
3795 wm8994->mic_detecting = true;
3796 wm8994->jack_mic = false;
3797 }
3798
3799 if (id_cb) {
3800 wm8994->mic_id_cb = id_cb;
3801 wm8994->mic_id_cb_data = id_cb_data;
3802 } else {
3803 wm8994->mic_id_cb = wm8958_mic_id;
3804 wm8994->mic_id_cb_data = codec;
3805 }
3806
3807 wm8958_micd_set_rate(codec);
3808
3809 /* Detect microphones and short circuits by default */
3810 if (control->pdata.micd_lvl_sel)
3811 micd_lvl_sel = control->pdata.micd_lvl_sel;
3812 else
3813 micd_lvl_sel = 0x41;
3814
3815 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3816 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3817 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3818
3819 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3820 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3821
3822 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3823
3824 /*
3825 * If we can use jack detection start off with that,
3826 * otherwise jump straight to microphone detection.
3827 */
3828 if (wm8994->jackdet) {
3829 /* Disable debounce for the initial detect */
3830 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3831 WM1811_JACKDET_DB, 0);
3832
3833 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3834 WM8958_MICB2_DISCH,
3835 WM8958_MICB2_DISCH);
3836 snd_soc_update_bits(codec, WM8994_LDO_1,
3837 WM8994_LDO1_DISCH, 0);
3838 wm1811_jackdet_set_mode(codec,
3839 WM1811_JACKDET_MODE_JACK);
3840 } else {
3841 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3842 WM8958_MICD_ENA, WM8958_MICD_ENA);
3843 }
3844
3845 } else {
3846 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3847 WM8958_MICD_ENA, 0);
3848 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3849 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3850 snd_soc_dapm_sync(&codec->dapm);
3851 }
3852
3853 return 0;
3854}
3855EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3856
3857static void wm8958_mic_work(struct work_struct *work)
3858{
3859 struct wm8994_priv *wm8994 = container_of(work,
3860 struct wm8994_priv,
3861 mic_complete_work.work);
3862 struct snd_soc_codec *codec = wm8994->hubs.codec;
3863
3864 pm_runtime_get_sync(codec->dev);
3865
3866 mutex_lock(&wm8994->accdet_lock);
3867
3868 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3869
3870 mutex_unlock(&wm8994->accdet_lock);
3871
3872 pm_runtime_put(codec->dev);
3873}
3874
3875static irqreturn_t wm8958_mic_irq(int irq, void *data)
3876{
3877 struct wm8994_priv *wm8994 = data;
3878 struct snd_soc_codec *codec = wm8994->hubs.codec;
3879 int reg, count, ret, id_delay;
3880
3881 /*
3882 * Jack detection may have detected a removal simulataneously
3883 * with an update of the MICDET status; if so it will have
3884 * stopped detection and we can ignore this interrupt.
3885 */
3886 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3887 return IRQ_HANDLED;
3888
3889 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3890 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3891
3892 pm_runtime_get_sync(codec->dev);
3893
3894 /* We may occasionally read a detection without an impedence
3895 * range being provided - if that happens loop again.
3896 */
3897 count = 10;
3898 do {
3899 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3900 if (reg < 0) {
3901 dev_err(codec->dev,
3902 "Failed to read mic detect status: %d\n",
3903 reg);
3904 pm_runtime_put(codec->dev);
3905 return IRQ_NONE;
3906 }
3907
3908 if (!(reg & WM8958_MICD_VALID)) {
3909 dev_dbg(codec->dev, "Mic detect data not valid\n");
3910 goto out;
3911 }
3912
3913 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3914 break;
3915
3916 msleep(1);
3917 } while (count--);
3918
3919 if (count == 0)
3920 dev_warn(codec->dev, "No impedance range reported for jack\n");
3921
3922#ifndef CONFIG_SND_SOC_WM8994_MODULE
3923 trace_snd_soc_jack_irq(dev_name(codec->dev));
3924#endif
3925
3926 /* Avoid a transient report when the accessory is being removed */
3927 if (wm8994->jackdet) {
3928 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3929 if (ret < 0) {
3930 dev_err(codec->dev, "Failed to read jack status: %d\n",
3931 ret);
3932 } else if (!(ret & WM1811_JACKDET_LVL)) {
3933 dev_dbg(codec->dev, "Ignoring removed jack\n");
3934 goto out;
3935 }
3936 } else if (!(reg & WM8958_MICD_STS)) {
3937 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3938 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3939 wm8994->btn_mask);
3940 wm8994->mic_detecting = true;
3941 goto out;
3942 }
3943
3944 wm8994->mic_status = reg;
3945 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3946
3947 if (wm8994->mic_detecting)
3948 queue_delayed_work(system_power_efficient_wq,
3949 &wm8994->mic_complete_work,
3950 msecs_to_jiffies(id_delay));
3951 else
3952 wm8958_button_det(codec, reg);
3953
3954out:
3955 pm_runtime_put(codec->dev);
3956 return IRQ_HANDLED;
3957}
3958
3959static irqreturn_t wm8994_fifo_error(int irq, void *data)
3960{
3961 struct snd_soc_codec *codec = data;
3962
3963 dev_err(codec->dev, "FIFO error\n");
3964
3965 return IRQ_HANDLED;
3966}
3967
3968static irqreturn_t wm8994_temp_warn(int irq, void *data)
3969{
3970 struct snd_soc_codec *codec = data;
3971
3972 dev_err(codec->dev, "Thermal warning\n");
3973
3974 return IRQ_HANDLED;
3975}
3976
3977static irqreturn_t wm8994_temp_shut(int irq, void *data)
3978{
3979 struct snd_soc_codec *codec = data;
3980
3981 dev_crit(codec->dev, "Thermal shutdown\n");
3982
3983 return IRQ_HANDLED;
3984}
3985
3986static int wm8994_codec_probe(struct snd_soc_codec *codec)
3987{
3988 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3989 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3990 struct snd_soc_dapm_context *dapm = &codec->dapm;
3991 unsigned int reg;
3992 int ret, i;
3993
3994 wm8994->hubs.codec = codec;
3995
3996 mutex_init(&wm8994->accdet_lock);
3997 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3998 wm1811_jackdet_bootstrap);
3999 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4000 wm8958_open_circuit_work);
4001
4002 switch (control->type) {
4003 case WM8994:
4004 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4005 break;
4006 case WM1811:
4007 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4008 break;
4009 default:
4010 break;
4011 }
4012
4013 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4014
4015 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4016 init_completion(&wm8994->fll_locked[i]);
4017
4018 wm8994->micdet_irq = control->pdata.micdet_irq;
4019
4020 /* By default use idle_bias_off, will override for WM8994 */
4021 codec->dapm.idle_bias_off = 1;
4022
4023 /* Set revision-specific configuration */
4024 switch (control->type) {
4025 case WM8994:
4026 /* Single ended line outputs should have VMID on. */
4027 if (!control->pdata.lineout1_diff ||
4028 !control->pdata.lineout2_diff)
4029 codec->dapm.idle_bias_off = 0;
4030
4031 switch (control->revision) {
4032 case 2:
4033 case 3:
4034 wm8994->hubs.dcs_codes_l = -5;
4035 wm8994->hubs.dcs_codes_r = -5;
4036 wm8994->hubs.hp_startup_mode = 1;
4037 wm8994->hubs.dcs_readback_mode = 1;
4038 wm8994->hubs.series_startup = 1;
4039 break;
4040 default:
4041 wm8994->hubs.dcs_readback_mode = 2;
4042 break;
4043 }
4044 break;
4045
4046 case WM8958:
4047 wm8994->hubs.dcs_readback_mode = 1;
4048 wm8994->hubs.hp_startup_mode = 1;
4049
4050 switch (control->revision) {
4051 case 0:
4052 break;
4053 default:
4054 wm8994->fll_byp = true;
4055 break;
4056 }
4057 break;
4058
4059 case WM1811:
4060 wm8994->hubs.dcs_readback_mode = 2;
4061 wm8994->hubs.no_series_update = 1;
4062 wm8994->hubs.hp_startup_mode = 1;
4063 wm8994->hubs.no_cache_dac_hp_direct = true;
4064 wm8994->fll_byp = true;
4065
4066 wm8994->hubs.dcs_codes_l = -9;
4067 wm8994->hubs.dcs_codes_r = -7;
4068
4069 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4070 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4071 break;
4072
4073 default:
4074 break;
4075 }
4076
4077 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4078 wm8994_fifo_error, "FIFO error", codec);
4079 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4080 wm8994_temp_warn, "Thermal warning", codec);
4081 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4082 wm8994_temp_shut, "Thermal shutdown", codec);
4083
4084 switch (control->type) {
4085 case WM8994:
4086 if (wm8994->micdet_irq)
4087 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4088 wm8994_mic_irq,
4089 IRQF_TRIGGER_RISING,
4090 "Mic1 detect",
4091 wm8994);
4092 else
4093 ret = wm8994_request_irq(wm8994->wm8994,
4094 WM8994_IRQ_MIC1_DET,
4095 wm8994_mic_irq, "Mic 1 detect",
4096 wm8994);
4097
4098 if (ret != 0)
4099 dev_warn(codec->dev,
4100 "Failed to request Mic1 detect IRQ: %d\n",
4101 ret);
4102
4103
4104 ret = wm8994_request_irq(wm8994->wm8994,
4105 WM8994_IRQ_MIC1_SHRT,
4106 wm8994_mic_irq, "Mic 1 short",
4107 wm8994);
4108 if (ret != 0)
4109 dev_warn(codec->dev,
4110 "Failed to request Mic1 short IRQ: %d\n",
4111 ret);
4112
4113 ret = wm8994_request_irq(wm8994->wm8994,
4114 WM8994_IRQ_MIC2_DET,
4115 wm8994_mic_irq, "Mic 2 detect",
4116 wm8994);
4117 if (ret != 0)
4118 dev_warn(codec->dev,
4119 "Failed to request Mic2 detect IRQ: %d\n",
4120 ret);
4121
4122 ret = wm8994_request_irq(wm8994->wm8994,
4123 WM8994_IRQ_MIC2_SHRT,
4124 wm8994_mic_irq, "Mic 2 short",
4125 wm8994);
4126 if (ret != 0)
4127 dev_warn(codec->dev,
4128 "Failed to request Mic2 short IRQ: %d\n",
4129 ret);
4130 break;
4131
4132 case WM8958:
4133 case WM1811:
4134 if (wm8994->micdet_irq) {
4135 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4136 wm8958_mic_irq,
4137 IRQF_TRIGGER_RISING,
4138 "Mic detect",
4139 wm8994);
4140 if (ret != 0)
4141 dev_warn(codec->dev,
4142 "Failed to request Mic detect IRQ: %d\n",
4143 ret);
4144 } else {
4145 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4146 wm8958_mic_irq, "Mic detect",
4147 wm8994);
4148 }
4149 }
4150
4151 switch (control->type) {
4152 case WM1811:
4153 if (control->cust_id > 1 || control->revision > 1) {
4154 ret = wm8994_request_irq(wm8994->wm8994,
4155 WM8994_IRQ_GPIO(6),
4156 wm1811_jackdet_irq, "JACKDET",
4157 wm8994);
4158 if (ret == 0)
4159 wm8994->jackdet = true;
4160 }
4161 break;
4162 default:
4163 break;
4164 }
4165
4166 wm8994->fll_locked_irq = true;
4167 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4168 ret = wm8994_request_irq(wm8994->wm8994,
4169 WM8994_IRQ_FLL1_LOCK + i,
4170 wm8994_fll_locked_irq, "FLL lock",
4171 &wm8994->fll_locked[i]);
4172 if (ret != 0)
4173 wm8994->fll_locked_irq = false;
4174 }
4175
4176 /* Make sure we can read from the GPIOs if they're inputs */
4177 pm_runtime_get_sync(codec->dev);
4178
4179 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4180 * configured on init - if a system wants to do this dynamically
4181 * at runtime we can deal with that then.
4182 */
4183 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4184 if (ret < 0) {
4185 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4186 goto err_irq;
4187 }
4188 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4189 wm8994->lrclk_shared[0] = 1;
4190 wm8994_dai[0].symmetric_rates = 1;
4191 } else {
4192 wm8994->lrclk_shared[0] = 0;
4193 }
4194
4195 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4196 if (ret < 0) {
4197 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4198 goto err_irq;
4199 }
4200 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4201 wm8994->lrclk_shared[1] = 1;
4202 wm8994_dai[1].symmetric_rates = 1;
4203 } else {
4204 wm8994->lrclk_shared[1] = 0;
4205 }
4206
4207 pm_runtime_put(codec->dev);
4208
4209 /* Latch volume update bits */
4210 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4211 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4212 wm8994_vu_bits[i].mask,
4213 wm8994_vu_bits[i].mask);
4214
4215 /* Set the low bit of the 3D stereo depth so TLV matches */
4216 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4217 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4218 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4219 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4220 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4221 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4222 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4223 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4224 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4225
4226 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4227 * use this; it only affects behaviour on idle TDM clock
4228 * cycles. */
4229 switch (control->type) {
4230 case WM8994:
4231 case WM8958:
4232 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4233 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4234 break;
4235 default:
4236 break;
4237 }
4238
4239 /* Put MICBIAS into bypass mode by default on newer devices */
4240 switch (control->type) {
4241 case WM8958:
4242 case WM1811:
4243 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4244 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4245 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4246 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4247 break;
4248 default:
4249 break;
4250 }
4251
4252 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4253 wm_hubs_update_class_w(codec);
4254
4255 wm8994_handle_pdata(wm8994);
4256
4257 wm_hubs_add_analogue_controls(codec);
4258 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4259 ARRAY_SIZE(wm8994_snd_controls));
4260 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4261 ARRAY_SIZE(wm8994_dapm_widgets));
4262
4263 switch (control->type) {
4264 case WM8994:
4265 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4266 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4267 if (control->revision < 4) {
4268 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4269 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4270 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4271 ARRAY_SIZE(wm8994_adc_revd_widgets));
4272 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4273 ARRAY_SIZE(wm8994_dac_revd_widgets));
4274 } else {
4275 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4276 ARRAY_SIZE(wm8994_lateclk_widgets));
4277 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4278 ARRAY_SIZE(wm8994_adc_widgets));
4279 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4280 ARRAY_SIZE(wm8994_dac_widgets));
4281 }
4282 break;
4283 case WM8958:
4284 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4285 ARRAY_SIZE(wm8958_snd_controls));
4286 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4287 ARRAY_SIZE(wm8958_dapm_widgets));
4288 if (control->revision < 1) {
4289 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4290 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4291 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4292 ARRAY_SIZE(wm8994_adc_revd_widgets));
4293 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4294 ARRAY_SIZE(wm8994_dac_revd_widgets));
4295 } else {
4296 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4297 ARRAY_SIZE(wm8994_lateclk_widgets));
4298 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4299 ARRAY_SIZE(wm8994_adc_widgets));
4300 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4301 ARRAY_SIZE(wm8994_dac_widgets));
4302 }
4303 break;
4304
4305 case WM1811:
4306 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4307 ARRAY_SIZE(wm8958_snd_controls));
4308 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4309 ARRAY_SIZE(wm8958_dapm_widgets));
4310 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4311 ARRAY_SIZE(wm8994_lateclk_widgets));
4312 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4313 ARRAY_SIZE(wm8994_adc_widgets));
4314 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4315 ARRAY_SIZE(wm8994_dac_widgets));
4316 break;
4317 }
4318
4319 wm_hubs_add_analogue_routes(codec, 0, 0);
4320 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4321 wm_hubs_dcs_done, "DC servo done",
4322 &wm8994->hubs);
4323 if (ret == 0)
4324 wm8994->hubs.dcs_done_irq = true;
4325 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4326
4327 switch (control->type) {
4328 case WM8994:
4329 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4330 ARRAY_SIZE(wm8994_intercon));
4331
4332 if (control->revision < 4) {
4333 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4334 ARRAY_SIZE(wm8994_revd_intercon));
4335 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4336 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4337 } else {
4338 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4339 ARRAY_SIZE(wm8994_lateclk_intercon));
4340 }
4341 break;
4342 case WM8958:
4343 if (control->revision < 1) {
4344 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4345 ARRAY_SIZE(wm8994_intercon));
4346 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4347 ARRAY_SIZE(wm8994_revd_intercon));
4348 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4349 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4350 } else {
4351 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4352 ARRAY_SIZE(wm8994_lateclk_intercon));
4353 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4354 ARRAY_SIZE(wm8958_intercon));
4355 }
4356
4357 wm8958_dsp2_init(codec);
4358 break;
4359 case WM1811:
4360 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4361 ARRAY_SIZE(wm8994_lateclk_intercon));
4362 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4363 ARRAY_SIZE(wm8958_intercon));
4364 break;
4365 }
4366
4367 return 0;
4368
4369err_irq:
4370 if (wm8994->jackdet)
4371 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4372 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4374 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4375 if (wm8994->micdet_irq)
4376 free_irq(wm8994->micdet_irq, wm8994);
4377 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4378 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4379 &wm8994->fll_locked[i]);
4380 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4381 &wm8994->hubs);
4382 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4383 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4384 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4385
4386 return ret;
4387}
4388
4389static int wm8994_codec_remove(struct snd_soc_codec *codec)
4390{
4391 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4392 struct wm8994 *control = wm8994->wm8994;
4393 int i;
4394
4395 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4396 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4397 &wm8994->fll_locked[i]);
4398
4399 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4400 &wm8994->hubs);
4401 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4402 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4403 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4404
4405 if (wm8994->jackdet)
4406 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4407
4408 switch (control->type) {
4409 case WM8994:
4410 if (wm8994->micdet_irq)
4411 free_irq(wm8994->micdet_irq, wm8994);
4412 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4413 wm8994);
4414 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4415 wm8994);
4416 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4417 wm8994);
4418 break;
4419
4420 case WM1811:
4421 case WM8958:
4422 if (wm8994->micdet_irq)
4423 free_irq(wm8994->micdet_irq, wm8994);
4424 break;
4425 }
4426 release_firmware(wm8994->mbc);
4427 release_firmware(wm8994->mbc_vss);
4428 release_firmware(wm8994->enh_eq);
4429 kfree(wm8994->retune_mobile_texts);
4430 return 0;
4431}
4432
4433static struct regmap *wm8994_get_regmap(struct device *dev)
4434{
4435 struct wm8994 *control = dev_get_drvdata(dev->parent);
4436
4437 return control->regmap;
4438}
4439
4440static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4441 .probe = wm8994_codec_probe,
4442 .remove = wm8994_codec_remove,
4443 .suspend = wm8994_codec_suspend,
4444 .resume = wm8994_codec_resume,
4445 .get_regmap = wm8994_get_regmap,
4446 .set_bias_level = wm8994_set_bias_level,
4447};
4448
4449static int wm8994_probe(struct platform_device *pdev)
4450{
4451 struct wm8994_priv *wm8994;
4452
4453 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4454 GFP_KERNEL);
4455 if (wm8994 == NULL)
4456 return -ENOMEM;
4457 platform_set_drvdata(pdev, wm8994);
4458
4459 mutex_init(&wm8994->fw_lock);
4460
4461 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4462
4463 pm_runtime_enable(&pdev->dev);
4464 pm_runtime_idle(&pdev->dev);
4465
4466 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4467 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4468}
4469
4470static int wm8994_remove(struct platform_device *pdev)
4471{
4472 snd_soc_unregister_codec(&pdev->dev);
4473 pm_runtime_disable(&pdev->dev);
4474
4475 return 0;
4476}
4477
4478#ifdef CONFIG_PM_SLEEP
4479static int wm8994_suspend(struct device *dev)
4480{
4481 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4482
4483 /* Drop down to power saving mode when system is suspended */
4484 if (wm8994->jackdet && !wm8994->active_refcount)
4485 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4486 WM1811_JACKDET_MODE_MASK,
4487 wm8994->jackdet_mode);
4488
4489 return 0;
4490}
4491
4492static int wm8994_resume(struct device *dev)
4493{
4494 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4495
4496 if (wm8994->jackdet && wm8994->jackdet_mode)
4497 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4498 WM1811_JACKDET_MODE_MASK,
4499 WM1811_JACKDET_MODE_AUDIO);
4500
4501 return 0;
4502}
4503#endif
4504
4505static const struct dev_pm_ops wm8994_pm_ops = {
4506 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4507};
4508
4509static struct platform_driver wm8994_codec_driver = {
4510 .driver = {
4511 .name = "wm8994-codec",
4512 .pm = &wm8994_pm_ops,
4513 },
4514 .probe = wm8994_probe,
4515 .remove = wm8994_remove,
4516};
4517
4518module_platform_driver(wm8994_codec_driver);
4519
4520MODULE_DESCRIPTION("ASoC WM8994 driver");
4521MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4522MODULE_LICENSE("GPL");
4523MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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