| 1 | /* |
| 2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver |
| 3 | * |
| 4 | * Author: Timur Tabi <timur@freescale.com> |
| 5 | * |
| 6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
| 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public License |
| 9 | * version 2. This program is licensed "as is" without any warranty of any |
| 10 | * kind, whether express or implied. |
| 11 | * |
| 12 | * |
| 13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: |
| 14 | * |
| 15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most |
| 16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only |
| 17 | * one FIFO which combines all valid receive slots. We cannot even select |
| 18 | * which slots we want to receive. The WM9712 with which this driver |
| 19 | * was developed with always sends GPIO status data in slot 12 which |
| 20 | * we receive in our (PCM-) data stream. The only chance we have is to |
| 21 | * manually skip this data in the FIQ handler. With sampling rates different |
| 22 | * from 48000Hz not every frame has valid receive data, so the ratio |
| 23 | * between pcm data and GPIO status data changes. Our FIQ handler is not |
| 24 | * able to handle this, hence this driver only works with 48000Hz sampling |
| 25 | * rate. |
| 26 | * Reading and writing AC97 registers is another challenge. The core |
| 27 | * provides us status bits when the read register is updated with *another* |
| 28 | * value. When we read the same register two times (and the register still |
| 29 | * contains the same value) these status bits are not set. We work |
| 30 | * around this by not polling these bits but only wait a fixed delay. |
| 31 | */ |
| 32 | |
| 33 | #include <linux/init.h> |
| 34 | #include <linux/io.h> |
| 35 | #include <linux/module.h> |
| 36 | #include <linux/interrupt.h> |
| 37 | #include <linux/clk.h> |
| 38 | #include <linux/device.h> |
| 39 | #include <linux/delay.h> |
| 40 | #include <linux/slab.h> |
| 41 | #include <linux/spinlock.h> |
| 42 | #include <linux/of_address.h> |
| 43 | #include <linux/of_irq.h> |
| 44 | #include <linux/of_platform.h> |
| 45 | |
| 46 | #include <sound/core.h> |
| 47 | #include <sound/pcm.h> |
| 48 | #include <sound/pcm_params.h> |
| 49 | #include <sound/initval.h> |
| 50 | #include <sound/soc.h> |
| 51 | #include <sound/dmaengine_pcm.h> |
| 52 | |
| 53 | #include "fsl_ssi.h" |
| 54 | #include "imx-pcm.h" |
| 55 | |
| 56 | #ifdef PPC |
| 57 | #define read_ssi(addr) in_be32(addr) |
| 58 | #define write_ssi(val, addr) out_be32(addr, val) |
| 59 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) |
| 60 | #else |
| 61 | #define read_ssi(addr) readl(addr) |
| 62 | #define write_ssi(val, addr) writel(val, addr) |
| 63 | /* |
| 64 | * FIXME: Proper locking should be added at write_ssi_mask caller level |
| 65 | * to ensure this register read/modify/write sequence is race free. |
| 66 | */ |
| 67 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) |
| 68 | { |
| 69 | u32 val = readl(addr); |
| 70 | val = (val & ~clear) | set; |
| 71 | writel(val, addr); |
| 72 | } |
| 73 | #endif |
| 74 | |
| 75 | /** |
| 76 | * FSLSSI_I2S_RATES: sample rates supported by the I2S |
| 77 | * |
| 78 | * This driver currently only supports the SSI running in I2S slave mode, |
| 79 | * which means the codec determines the sample rate. Therefore, we tell |
| 80 | * ALSA that we support all rates and let the codec driver decide what rates |
| 81 | * are really supported. |
| 82 | */ |
| 83 | #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS |
| 84 | |
| 85 | /** |
| 86 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI |
| 87 | * |
| 88 | * This driver currently only supports the SSI running in I2S slave mode. |
| 89 | * |
| 90 | * The SSI has a limitation in that the samples must be in the same byte |
| 91 | * order as the host CPU. This is because when multiple bytes are written |
| 92 | * to the STX register, the bytes and bits must be written in the same |
| 93 | * order. The STX is a shift register, so all the bits need to be aligned |
| 94 | * (bit-endianness must match byte-endianness). Processors typically write |
| 95 | * the bits within a byte in the same order that the bytes of a word are |
| 96 | * written in. So if the host CPU is big-endian, then only big-endian |
| 97 | * samples will be written to STX properly. |
| 98 | */ |
| 99 | #ifdef __BIG_ENDIAN |
| 100 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ |
| 101 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ |
| 102 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) |
| 103 | #else |
| 104 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ |
| 105 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 106 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) |
| 107 | #endif |
| 108 | |
| 109 | #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ |
| 110 | CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ |
| 111 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) |
| 112 | #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ |
| 113 | CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ |
| 114 | CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) |
| 115 | |
| 116 | enum fsl_ssi_type { |
| 117 | FSL_SSI_MCP8610, |
| 118 | FSL_SSI_MX21, |
| 119 | FSL_SSI_MX35, |
| 120 | FSL_SSI_MX51, |
| 121 | }; |
| 122 | |
| 123 | struct fsl_ssi_reg_val { |
| 124 | u32 sier; |
| 125 | u32 srcr; |
| 126 | u32 stcr; |
| 127 | u32 scr; |
| 128 | }; |
| 129 | |
| 130 | struct fsl_ssi_rxtx_reg_val { |
| 131 | struct fsl_ssi_reg_val rx; |
| 132 | struct fsl_ssi_reg_val tx; |
| 133 | }; |
| 134 | |
| 135 | struct fsl_ssi_soc_data { |
| 136 | bool imx; |
| 137 | bool offline_config; |
| 138 | u32 sisr_write_mask; |
| 139 | }; |
| 140 | |
| 141 | /** |
| 142 | * fsl_ssi_private: per-SSI private data |
| 143 | * |
| 144 | * @ssi: pointer to the SSI's registers |
| 145 | * @ssi_phys: physical address of the SSI registers |
| 146 | * @irq: IRQ of this SSI |
| 147 | * @playback: the number of playback streams opened |
| 148 | * @capture: the number of capture streams opened |
| 149 | * @cpu_dai: the CPU DAI for this device |
| 150 | * @dev_attr: the sysfs device attribute structure |
| 151 | * @stats: SSI statistics |
| 152 | */ |
| 153 | struct fsl_ssi_private { |
| 154 | struct ccsr_ssi __iomem *ssi; |
| 155 | dma_addr_t ssi_phys; |
| 156 | unsigned int irq; |
| 157 | unsigned int fifo_depth; |
| 158 | struct snd_soc_dai_driver cpu_dai_drv; |
| 159 | struct platform_device *pdev; |
| 160 | unsigned int dai_fmt; |
| 161 | |
| 162 | bool use_dma; |
| 163 | bool use_dual_fifo; |
| 164 | u8 i2s_mode; |
| 165 | struct clk *baudclk; |
| 166 | struct clk *clk; |
| 167 | unsigned int baudclk_streams; |
| 168 | unsigned int bitclk_freq; |
| 169 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
| 170 | struct snd_dmaengine_dai_dma_data dma_params_rx; |
| 171 | struct imx_pcm_fiq_params fiq_params; |
| 172 | /* Register values for rx/tx configuration */ |
| 173 | struct fsl_ssi_rxtx_reg_val rxtx_reg_val; |
| 174 | |
| 175 | struct fsl_ssi_dbg dbg_stats; |
| 176 | |
| 177 | const struct fsl_ssi_soc_data *soc; |
| 178 | }; |
| 179 | |
| 180 | /* |
| 181 | * imx51 and later SoCs have a slightly different IP that allows the |
| 182 | * SSI configuration while the SSI unit is running. |
| 183 | * |
| 184 | * More important, it is necessary on those SoCs to configure the |
| 185 | * sperate TX/RX DMA bits just before starting the stream |
| 186 | * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi |
| 187 | * sends any DMA requests to the SDMA unit, otherwise it is not defined |
| 188 | * how the SDMA unit handles the DMA request. |
| 189 | * |
| 190 | * SDMA units are present on devices starting at imx35 but the imx35 |
| 191 | * reference manual states that the DMA bits should not be changed |
| 192 | * while the SSI unit is running (SSIEN). So we support the necessary |
| 193 | * online configuration of fsl-ssi starting at imx51. |
| 194 | */ |
| 195 | |
| 196 | static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { |
| 197 | .imx = false, |
| 198 | .offline_config = true, |
| 199 | .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | |
| 200 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | |
| 201 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, |
| 202 | }; |
| 203 | |
| 204 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { |
| 205 | .imx = true, |
| 206 | .offline_config = true, |
| 207 | .sisr_write_mask = 0, |
| 208 | }; |
| 209 | |
| 210 | static struct fsl_ssi_soc_data fsl_ssi_imx35 = { |
| 211 | .imx = true, |
| 212 | .offline_config = true, |
| 213 | .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | |
| 214 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | |
| 215 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, |
| 216 | }; |
| 217 | |
| 218 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { |
| 219 | .imx = true, |
| 220 | .offline_config = false, |
| 221 | .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | |
| 222 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, |
| 223 | }; |
| 224 | |
| 225 | static const struct of_device_id fsl_ssi_ids[] = { |
| 226 | { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, |
| 227 | { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, |
| 228 | { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, |
| 229 | { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, |
| 230 | {} |
| 231 | }; |
| 232 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); |
| 233 | |
| 234 | static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) |
| 235 | { |
| 236 | return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97); |
| 237 | } |
| 238 | |
| 239 | static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) |
| 240 | { |
| 241 | return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == |
| 242 | SND_SOC_DAIFMT_CBS_CFS; |
| 243 | } |
| 244 | |
| 245 | /** |
| 246 | * fsl_ssi_isr: SSI interrupt handler |
| 247 | * |
| 248 | * Although it's possible to use the interrupt handler to send and receive |
| 249 | * data to/from the SSI, we use the DMA instead. Programming is more |
| 250 | * complicated, but the performance is much better. |
| 251 | * |
| 252 | * This interrupt handler is used only to gather statistics. |
| 253 | * |
| 254 | * @irq: IRQ of the SSI device |
| 255 | * @dev_id: pointer to the ssi_private structure for this SSI device |
| 256 | */ |
| 257 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) |
| 258 | { |
| 259 | struct fsl_ssi_private *ssi_private = dev_id; |
| 260 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 261 | __be32 sisr; |
| 262 | __be32 sisr2; |
| 263 | |
| 264 | /* We got an interrupt, so read the status register to see what we |
| 265 | were interrupted for. We mask it with the Interrupt Enable register |
| 266 | so that we only check for events that we're interested in. |
| 267 | */ |
| 268 | sisr = read_ssi(&ssi->sisr); |
| 269 | |
| 270 | sisr2 = sisr & ssi_private->soc->sisr_write_mask; |
| 271 | /* Clear the bits that we set */ |
| 272 | if (sisr2) |
| 273 | write_ssi(sisr2, &ssi->sisr); |
| 274 | |
| 275 | fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); |
| 276 | |
| 277 | return IRQ_HANDLED; |
| 278 | } |
| 279 | |
| 280 | /* |
| 281 | * Enable/Disable all rx/tx config flags at once. |
| 282 | */ |
| 283 | static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, |
| 284 | bool enable) |
| 285 | { |
| 286 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 287 | struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; |
| 288 | |
| 289 | if (enable) { |
| 290 | write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier); |
| 291 | write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr); |
| 292 | write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr); |
| 293 | } else { |
| 294 | write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0); |
| 295 | write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0); |
| 296 | write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0); |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | /* |
| 301 | * Calculate the bits that have to be disabled for the current stream that is |
| 302 | * getting disabled. This keeps the bits enabled that are necessary for the |
| 303 | * second stream to work if 'stream_active' is true. |
| 304 | * |
| 305 | * Detailed calculation: |
| 306 | * These are the values that need to be active after disabling. For non-active |
| 307 | * second stream, this is 0: |
| 308 | * vals_stream * !!stream_active |
| 309 | * |
| 310 | * The following computes the overall differences between the setup for the |
| 311 | * to-disable stream and the active stream, a simple XOR: |
| 312 | * vals_disable ^ (vals_stream * !!(stream_active)) |
| 313 | * |
| 314 | * The full expression adds a mask on all values we care about |
| 315 | */ |
| 316 | #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ |
| 317 | ((vals_disable) & \ |
| 318 | ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) |
| 319 | |
| 320 | /* |
| 321 | * Enable/Disable a ssi configuration. You have to pass either |
| 322 | * ssi_private->rxtx_reg_val.rx or tx as vals parameter. |
| 323 | */ |
| 324 | static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, |
| 325 | struct fsl_ssi_reg_val *vals) |
| 326 | { |
| 327 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 328 | struct fsl_ssi_reg_val *avals; |
| 329 | u32 scr_val = read_ssi(&ssi->scr); |
| 330 | int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + |
| 331 | !!(scr_val & CCSR_SSI_SCR_RE); |
| 332 | int keep_active; |
| 333 | |
| 334 | if (nr_active_streams - 1 > 0) |
| 335 | keep_active = 1; |
| 336 | else |
| 337 | keep_active = 0; |
| 338 | |
| 339 | /* Find the other direction values rx or tx which we do not want to |
| 340 | * modify */ |
| 341 | if (&ssi_private->rxtx_reg_val.rx == vals) |
| 342 | avals = &ssi_private->rxtx_reg_val.tx; |
| 343 | else |
| 344 | avals = &ssi_private->rxtx_reg_val.rx; |
| 345 | |
| 346 | /* If vals should be disabled, start with disabling the unit */ |
| 347 | if (!enable) { |
| 348 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, |
| 349 | keep_active); |
| 350 | write_ssi_mask(&ssi->scr, scr, 0); |
| 351 | } |
| 352 | |
| 353 | /* |
| 354 | * We are running on a SoC which does not support online SSI |
| 355 | * reconfiguration, so we have to enable all necessary flags at once |
| 356 | * even if we do not use them later (capture and playback configuration) |
| 357 | */ |
| 358 | if (ssi_private->soc->offline_config) { |
| 359 | if ((enable && !nr_active_streams) || |
| 360 | (!enable && !keep_active)) |
| 361 | fsl_ssi_rxtx_config(ssi_private, enable); |
| 362 | |
| 363 | goto config_done; |
| 364 | } |
| 365 | |
| 366 | /* |
| 367 | * Configure single direction units while the SSI unit is running |
| 368 | * (online configuration) |
| 369 | */ |
| 370 | if (enable) { |
| 371 | write_ssi_mask(&ssi->sier, 0, vals->sier); |
| 372 | write_ssi_mask(&ssi->srcr, 0, vals->srcr); |
| 373 | write_ssi_mask(&ssi->stcr, 0, vals->stcr); |
| 374 | } else { |
| 375 | u32 sier; |
| 376 | u32 srcr; |
| 377 | u32 stcr; |
| 378 | |
| 379 | /* |
| 380 | * Disabling the necessary flags for one of rx/tx while the |
| 381 | * other stream is active is a little bit more difficult. We |
| 382 | * have to disable only those flags that differ between both |
| 383 | * streams (rx XOR tx) and that are set in the stream that is |
| 384 | * disabled now. Otherwise we could alter flags of the other |
| 385 | * stream |
| 386 | */ |
| 387 | |
| 388 | /* These assignments are simply vals without bits set in avals*/ |
| 389 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, |
| 390 | keep_active); |
| 391 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, |
| 392 | keep_active); |
| 393 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, |
| 394 | keep_active); |
| 395 | |
| 396 | write_ssi_mask(&ssi->srcr, srcr, 0); |
| 397 | write_ssi_mask(&ssi->stcr, stcr, 0); |
| 398 | write_ssi_mask(&ssi->sier, sier, 0); |
| 399 | } |
| 400 | |
| 401 | config_done: |
| 402 | /* Enabling of subunits is done after configuration */ |
| 403 | if (enable) |
| 404 | write_ssi_mask(&ssi->scr, 0, vals->scr); |
| 405 | } |
| 406 | |
| 407 | |
| 408 | static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) |
| 409 | { |
| 410 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); |
| 411 | } |
| 412 | |
| 413 | static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) |
| 414 | { |
| 415 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); |
| 416 | } |
| 417 | |
| 418 | /* |
| 419 | * Setup rx/tx register values used to enable/disable the streams. These will |
| 420 | * be used later in fsl_ssi_config to setup the streams without the need to |
| 421 | * check for all different SSI modes. |
| 422 | */ |
| 423 | static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) |
| 424 | { |
| 425 | struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; |
| 426 | |
| 427 | reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; |
| 428 | reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; |
| 429 | reg->rx.scr = 0; |
| 430 | reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; |
| 431 | reg->tx.stcr = CCSR_SSI_STCR_TFEN0; |
| 432 | reg->tx.scr = 0; |
| 433 | |
| 434 | if (!fsl_ssi_is_ac97(ssi_private)) { |
| 435 | reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; |
| 436 | reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; |
| 437 | reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; |
| 438 | reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; |
| 439 | } |
| 440 | |
| 441 | if (ssi_private->use_dma) { |
| 442 | reg->rx.sier |= CCSR_SSI_SIER_RDMAE; |
| 443 | reg->tx.sier |= CCSR_SSI_SIER_TDMAE; |
| 444 | } else { |
| 445 | reg->rx.sier |= CCSR_SSI_SIER_RIE; |
| 446 | reg->tx.sier |= CCSR_SSI_SIER_TIE; |
| 447 | } |
| 448 | |
| 449 | reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; |
| 450 | reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; |
| 451 | } |
| 452 | |
| 453 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
| 454 | { |
| 455 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 456 | |
| 457 | /* |
| 458 | * Setup the clock control register |
| 459 | */ |
| 460 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), |
| 461 | &ssi->stccr); |
| 462 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), |
| 463 | &ssi->srccr); |
| 464 | |
| 465 | /* |
| 466 | * Enable AC97 mode and startup the SSI |
| 467 | */ |
| 468 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, |
| 469 | &ssi->sacnt); |
| 470 | write_ssi(0xff, &ssi->saccdis); |
| 471 | write_ssi(0x300, &ssi->saccen); |
| 472 | |
| 473 | /* |
| 474 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the |
| 475 | * codec before a stream is started. |
| 476 | */ |
| 477 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | |
| 478 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); |
| 479 | |
| 480 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); |
| 481 | } |
| 482 | |
| 483 | /** |
| 484 | * fsl_ssi_startup: create a new substream |
| 485 | * |
| 486 | * This is the first function called when a stream is opened. |
| 487 | * |
| 488 | * If this is the first stream open, then grab the IRQ and program most of |
| 489 | * the SSI registers. |
| 490 | */ |
| 491 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
| 492 | struct snd_soc_dai *dai) |
| 493 | { |
| 494 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 495 | struct fsl_ssi_private *ssi_private = |
| 496 | snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 497 | |
| 498 | /* When using dual fifo mode, it is safer to ensure an even period |
| 499 | * size. If appearing to an odd number while DMA always starts its |
| 500 | * task from fifo0, fifo1 would be neglected at the end of each |
| 501 | * period. But SSI would still access fifo1 with an invalid data. |
| 502 | */ |
| 503 | if (ssi_private->use_dual_fifo) |
| 504 | snd_pcm_hw_constraint_step(substream->runtime, 0, |
| 505 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | /** |
| 511 | * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock |
| 512 | * |
| 513 | * Note: This function can be only called when using SSI as DAI master |
| 514 | * |
| 515 | * Quick instruction for parameters: |
| 516 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels |
| 517 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. |
| 518 | */ |
| 519 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, |
| 520 | struct snd_soc_dai *cpu_dai, |
| 521 | struct snd_pcm_hw_params *hw_params) |
| 522 | { |
| 523 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
| 524 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 525 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; |
| 526 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; |
| 527 | unsigned long clkrate, baudrate, tmprate; |
| 528 | u64 sub, savesub = 100000; |
| 529 | unsigned int freq; |
| 530 | bool baudclk_is_used; |
| 531 | |
| 532 | /* Prefer the explicitly set bitclock frequency */ |
| 533 | if (ssi_private->bitclk_freq) |
| 534 | freq = ssi_private->bitclk_freq; |
| 535 | else |
| 536 | freq = params_channels(hw_params) * 32 * params_rate(hw_params); |
| 537 | |
| 538 | /* Don't apply it to any non-baudclk circumstance */ |
| 539 | if (IS_ERR(ssi_private->baudclk)) |
| 540 | return -EINVAL; |
| 541 | |
| 542 | baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); |
| 543 | |
| 544 | /* It should be already enough to divide clock by setting pm alone */ |
| 545 | psr = 0; |
| 546 | div2 = 0; |
| 547 | |
| 548 | factor = (div2 + 1) * (7 * psr + 1) * 2; |
| 549 | |
| 550 | for (i = 0; i < 255; i++) { |
| 551 | /* The bclk rate must be smaller than 1/5 sysclk rate */ |
| 552 | if (factor * (i + 1) < 5) |
| 553 | continue; |
| 554 | |
| 555 | tmprate = freq * factor * (i + 2); |
| 556 | |
| 557 | if (baudclk_is_used) |
| 558 | clkrate = clk_get_rate(ssi_private->baudclk); |
| 559 | else |
| 560 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); |
| 561 | |
| 562 | do_div(clkrate, factor); |
| 563 | afreq = (u32)clkrate / (i + 1); |
| 564 | |
| 565 | if (freq == afreq) |
| 566 | sub = 0; |
| 567 | else if (freq / afreq == 1) |
| 568 | sub = freq - afreq; |
| 569 | else if (afreq / freq == 1) |
| 570 | sub = afreq - freq; |
| 571 | else |
| 572 | continue; |
| 573 | |
| 574 | /* Calculate the fraction */ |
| 575 | sub *= 100000; |
| 576 | do_div(sub, freq); |
| 577 | |
| 578 | if (sub < savesub) { |
| 579 | baudrate = tmprate; |
| 580 | savesub = sub; |
| 581 | pm = i; |
| 582 | } |
| 583 | |
| 584 | /* We are lucky */ |
| 585 | if (savesub == 0) |
| 586 | break; |
| 587 | } |
| 588 | |
| 589 | /* No proper pm found if it is still remaining the initial value */ |
| 590 | if (pm == 999) { |
| 591 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); |
| 592 | return -EINVAL; |
| 593 | } |
| 594 | |
| 595 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | |
| 596 | (psr ? CCSR_SSI_SxCCR_PSR : 0); |
| 597 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | |
| 598 | CCSR_SSI_SxCCR_PSR; |
| 599 | |
| 600 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) |
| 601 | write_ssi_mask(&ssi->stccr, mask, stccr); |
| 602 | else |
| 603 | write_ssi_mask(&ssi->srccr, mask, stccr); |
| 604 | |
| 605 | if (!baudclk_is_used) { |
| 606 | ret = clk_set_rate(ssi_private->baudclk, baudrate); |
| 607 | if (ret) { |
| 608 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); |
| 609 | return -EINVAL; |
| 610 | } |
| 611 | } |
| 612 | |
| 613 | return 0; |
| 614 | } |
| 615 | |
| 616 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
| 617 | int clk_id, unsigned int freq, int dir) |
| 618 | { |
| 619 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
| 620 | |
| 621 | ssi_private->bitclk_freq = freq; |
| 622 | |
| 623 | return 0; |
| 624 | } |
| 625 | |
| 626 | /** |
| 627 | * fsl_ssi_hw_params - program the sample size |
| 628 | * |
| 629 | * Most of the SSI registers have been programmed in the startup function, |
| 630 | * but the word length must be programmed here. Unfortunately, programming |
| 631 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can |
| 632 | * cause a problem with supporting simultaneous playback and capture. If |
| 633 | * the SSI is already playing a stream, then that stream may be temporarily |
| 634 | * stopped when you start capture. |
| 635 | * |
| 636 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the |
| 637 | * clock master. |
| 638 | */ |
| 639 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
| 640 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) |
| 641 | { |
| 642 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
| 643 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 644 | unsigned int channels = params_channels(hw_params); |
| 645 | unsigned int sample_size = |
| 646 | snd_pcm_format_width(params_format(hw_params)); |
| 647 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); |
| 648 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
| 649 | int ret; |
| 650 | |
| 651 | /* |
| 652 | * If we're in synchronous mode, and the SSI is already enabled, |
| 653 | * then STCCR is already set properly. |
| 654 | */ |
| 655 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) |
| 656 | return 0; |
| 657 | |
| 658 | if (fsl_ssi_is_i2s_master(ssi_private)) { |
| 659 | ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); |
| 660 | if (ret) |
| 661 | return ret; |
| 662 | |
| 663 | /* Do not enable the clock if it is already enabled */ |
| 664 | if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { |
| 665 | ret = clk_prepare_enable(ssi_private->baudclk); |
| 666 | if (ret) |
| 667 | return ret; |
| 668 | |
| 669 | ssi_private->baudclk_streams |= BIT(substream->stream); |
| 670 | } |
| 671 | } |
| 672 | |
| 673 | /* |
| 674 | * FIXME: The documentation says that SxCCR[WL] should not be |
| 675 | * modified while the SSI is enabled. The only time this can |
| 676 | * happen is if we're trying to do simultaneous playback and |
| 677 | * capture in asynchronous mode. Unfortunately, I have been enable |
| 678 | * to get that to work at all on the P1022DS. Therefore, we don't |
| 679 | * bother to disable/enable the SSI when setting SxCCR[WL], because |
| 680 | * the SSI will stop anyway. Maybe one day, this will get fixed. |
| 681 | */ |
| 682 | |
| 683 | /* In synchronous mode, the SSI uses STCCR for capture */ |
| 684 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || |
| 685 | ssi_private->cpu_dai_drv.symmetric_rates) |
| 686 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
| 687 | else |
| 688 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
| 689 | |
| 690 | if (!fsl_ssi_is_ac97(ssi_private)) |
| 691 | write_ssi_mask(&ssi->scr, |
| 692 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, |
| 693 | channels == 1 ? 0 : ssi_private->i2s_mode); |
| 694 | |
| 695 | return 0; |
| 696 | } |
| 697 | |
| 698 | static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, |
| 699 | struct snd_soc_dai *cpu_dai) |
| 700 | { |
| 701 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 702 | struct fsl_ssi_private *ssi_private = |
| 703 | snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 704 | |
| 705 | if (fsl_ssi_is_i2s_master(ssi_private) && |
| 706 | ssi_private->baudclk_streams & BIT(substream->stream)) { |
| 707 | clk_disable_unprepare(ssi_private->baudclk); |
| 708 | ssi_private->baudclk_streams &= ~BIT(substream->stream); |
| 709 | } |
| 710 | |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private, |
| 715 | unsigned int fmt) |
| 716 | { |
| 717 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 718 | u32 strcr = 0, stcr, srcr, scr, mask; |
| 719 | u8 wm; |
| 720 | |
| 721 | ssi_private->dai_fmt = fmt; |
| 722 | |
| 723 | if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { |
| 724 | dev_err(&ssi_private->pdev->dev, "baudclk is missing which is necessary for master mode\n"); |
| 725 | return -EINVAL; |
| 726 | } |
| 727 | |
| 728 | fsl_ssi_setup_reg_vals(ssi_private); |
| 729 | |
| 730 | scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); |
| 731 | scr |= CCSR_SSI_SCR_SYNC_TX_FS; |
| 732 | |
| 733 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | |
| 734 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | |
| 735 | CCSR_SSI_STCR_TEFS; |
| 736 | stcr = read_ssi(&ssi->stcr) & ~mask; |
| 737 | srcr = read_ssi(&ssi->srcr) & ~mask; |
| 738 | |
| 739 | ssi_private->i2s_mode = CCSR_SSI_SCR_NET; |
| 740 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 741 | case SND_SOC_DAIFMT_I2S: |
| 742 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 743 | case SND_SOC_DAIFMT_CBS_CFS: |
| 744 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; |
| 745 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, |
| 746 | CCSR_SSI_SxCCR_DC(2)); |
| 747 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, |
| 748 | CCSR_SSI_SxCCR_DC(2)); |
| 749 | break; |
| 750 | case SND_SOC_DAIFMT_CBM_CFM: |
| 751 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; |
| 752 | break; |
| 753 | default: |
| 754 | return -EINVAL; |
| 755 | } |
| 756 | |
| 757 | /* Data on rising edge of bclk, frame low, 1clk before data */ |
| 758 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | |
| 759 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; |
| 760 | break; |
| 761 | case SND_SOC_DAIFMT_LEFT_J: |
| 762 | /* Data on rising edge of bclk, frame high */ |
| 763 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; |
| 764 | break; |
| 765 | case SND_SOC_DAIFMT_DSP_A: |
| 766 | /* Data on rising edge of bclk, frame high, 1clk before data */ |
| 767 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | |
| 768 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; |
| 769 | break; |
| 770 | case SND_SOC_DAIFMT_DSP_B: |
| 771 | /* Data on rising edge of bclk, frame high */ |
| 772 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | |
| 773 | CCSR_SSI_STCR_TXBIT0; |
| 774 | break; |
| 775 | case SND_SOC_DAIFMT_AC97: |
| 776 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; |
| 777 | break; |
| 778 | default: |
| 779 | return -EINVAL; |
| 780 | } |
| 781 | scr |= ssi_private->i2s_mode; |
| 782 | |
| 783 | /* DAI clock inversion */ |
| 784 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 785 | case SND_SOC_DAIFMT_NB_NF: |
| 786 | /* Nothing to do for both normal cases */ |
| 787 | break; |
| 788 | case SND_SOC_DAIFMT_IB_NF: |
| 789 | /* Invert bit clock */ |
| 790 | strcr ^= CCSR_SSI_STCR_TSCKP; |
| 791 | break; |
| 792 | case SND_SOC_DAIFMT_NB_IF: |
| 793 | /* Invert frame clock */ |
| 794 | strcr ^= CCSR_SSI_STCR_TFSI; |
| 795 | break; |
| 796 | case SND_SOC_DAIFMT_IB_IF: |
| 797 | /* Invert both clocks */ |
| 798 | strcr ^= CCSR_SSI_STCR_TSCKP; |
| 799 | strcr ^= CCSR_SSI_STCR_TFSI; |
| 800 | break; |
| 801 | default: |
| 802 | return -EINVAL; |
| 803 | } |
| 804 | |
| 805 | /* DAI clock master masks */ |
| 806 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 807 | case SND_SOC_DAIFMT_CBS_CFS: |
| 808 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; |
| 809 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; |
| 810 | break; |
| 811 | case SND_SOC_DAIFMT_CBM_CFM: |
| 812 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; |
| 813 | break; |
| 814 | default: |
| 815 | return -EINVAL; |
| 816 | } |
| 817 | |
| 818 | stcr |= strcr; |
| 819 | srcr |= strcr; |
| 820 | |
| 821 | if (ssi_private->cpu_dai_drv.symmetric_rates) { |
| 822 | /* Need to clear RXDIR when using SYNC mode */ |
| 823 | srcr &= ~CCSR_SSI_SRCR_RXDIR; |
| 824 | scr |= CCSR_SSI_SCR_SYN; |
| 825 | } |
| 826 | |
| 827 | write_ssi(stcr, &ssi->stcr); |
| 828 | write_ssi(srcr, &ssi->srcr); |
| 829 | write_ssi(scr, &ssi->scr); |
| 830 | |
| 831 | /* |
| 832 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't |
| 833 | * use FIFO 1. We program the transmit water to signal a DMA transfer |
| 834 | * if there are only two (or fewer) elements left in the FIFO. Two |
| 835 | * elements equals one frame (left channel, right channel). This value, |
| 836 | * however, depends on the depth of the transmit buffer. |
| 837 | * |
| 838 | * We set the watermark on the same level as the DMA burstsize. For |
| 839 | * fiq it is probably better to use the biggest possible watermark |
| 840 | * size. |
| 841 | */ |
| 842 | if (ssi_private->use_dma) |
| 843 | wm = ssi_private->fifo_depth - 2; |
| 844 | else |
| 845 | wm = ssi_private->fifo_depth; |
| 846 | |
| 847 | write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | |
| 848 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), |
| 849 | &ssi->sfcsr); |
| 850 | |
| 851 | if (ssi_private->use_dual_fifo) { |
| 852 | write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, |
| 853 | CCSR_SSI_SRCR_RFEN1); |
| 854 | write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, |
| 855 | CCSR_SSI_STCR_TFEN1); |
| 856 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, |
| 857 | CCSR_SSI_SCR_TCH_EN); |
| 858 | } |
| 859 | |
| 860 | if (fmt & SND_SOC_DAIFMT_AC97) |
| 861 | fsl_ssi_setup_ac97(ssi_private); |
| 862 | |
| 863 | return 0; |
| 864 | |
| 865 | } |
| 866 | |
| 867 | /** |
| 868 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. |
| 869 | */ |
| 870 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) |
| 871 | { |
| 872 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
| 873 | |
| 874 | return _fsl_ssi_set_dai_fmt(ssi_private, fmt); |
| 875 | } |
| 876 | |
| 877 | /** |
| 878 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number |
| 879 | * |
| 880 | * Note: This function can be only called when using SSI as DAI master |
| 881 | */ |
| 882 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, |
| 883 | u32 rx_mask, int slots, int slot_width) |
| 884 | { |
| 885 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
| 886 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 887 | u32 val; |
| 888 | |
| 889 | /* The slot number should be >= 2 if using Network mode or I2S mode */ |
| 890 | val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); |
| 891 | if (val && slots < 2) { |
| 892 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); |
| 893 | return -EINVAL; |
| 894 | } |
| 895 | |
| 896 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, |
| 897 | CCSR_SSI_SxCCR_DC(slots)); |
| 898 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, |
| 899 | CCSR_SSI_SxCCR_DC(slots)); |
| 900 | |
| 901 | /* The register SxMSKs needs SSI to provide essential clock due to |
| 902 | * hardware design. So we here temporarily enable SSI to set them. |
| 903 | */ |
| 904 | val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
| 905 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); |
| 906 | |
| 907 | write_ssi(tx_mask, &ssi->stmsk); |
| 908 | write_ssi(rx_mask, &ssi->srmsk); |
| 909 | |
| 910 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); |
| 911 | |
| 912 | return 0; |
| 913 | } |
| 914 | |
| 915 | /** |
| 916 | * fsl_ssi_trigger: start and stop the DMA transfer. |
| 917 | * |
| 918 | * This function is called by ALSA to start, stop, pause, and resume the DMA |
| 919 | * transfer of data. |
| 920 | * |
| 921 | * The DMA channel is in external master start and pause mode, which |
| 922 | * means the SSI completely controls the flow of data. |
| 923 | */ |
| 924 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
| 925 | struct snd_soc_dai *dai) |
| 926 | { |
| 927 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 928 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 929 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
| 930 | |
| 931 | switch (cmd) { |
| 932 | case SNDRV_PCM_TRIGGER_START: |
| 933 | case SNDRV_PCM_TRIGGER_RESUME: |
| 934 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 935 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 936 | fsl_ssi_tx_config(ssi_private, true); |
| 937 | else |
| 938 | fsl_ssi_rx_config(ssi_private, true); |
| 939 | break; |
| 940 | |
| 941 | case SNDRV_PCM_TRIGGER_STOP: |
| 942 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 943 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 944 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 945 | fsl_ssi_tx_config(ssi_private, false); |
| 946 | else |
| 947 | fsl_ssi_rx_config(ssi_private, false); |
| 948 | break; |
| 949 | |
| 950 | default: |
| 951 | return -EINVAL; |
| 952 | } |
| 953 | |
| 954 | if (fsl_ssi_is_ac97(ssi_private)) { |
| 955 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 956 | write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); |
| 957 | else |
| 958 | write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); |
| 959 | } |
| 960 | |
| 961 | return 0; |
| 962 | } |
| 963 | |
| 964 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
| 965 | { |
| 966 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); |
| 967 | |
| 968 | if (ssi_private->soc->imx && ssi_private->use_dma) { |
| 969 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
| 970 | dai->capture_dma_data = &ssi_private->dma_params_rx; |
| 971 | } |
| 972 | |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
| 977 | .startup = fsl_ssi_startup, |
| 978 | .hw_params = fsl_ssi_hw_params, |
| 979 | .hw_free = fsl_ssi_hw_free, |
| 980 | .set_fmt = fsl_ssi_set_dai_fmt, |
| 981 | .set_sysclk = fsl_ssi_set_dai_sysclk, |
| 982 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, |
| 983 | .trigger = fsl_ssi_trigger, |
| 984 | }; |
| 985 | |
| 986 | /* Template for the CPU dai driver structure */ |
| 987 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { |
| 988 | .probe = fsl_ssi_dai_probe, |
| 989 | .playback = { |
| 990 | .channels_min = 1, |
| 991 | .channels_max = 2, |
| 992 | .rates = FSLSSI_I2S_RATES, |
| 993 | .formats = FSLSSI_I2S_FORMATS, |
| 994 | }, |
| 995 | .capture = { |
| 996 | .channels_min = 1, |
| 997 | .channels_max = 2, |
| 998 | .rates = FSLSSI_I2S_RATES, |
| 999 | .formats = FSLSSI_I2S_FORMATS, |
| 1000 | }, |
| 1001 | .ops = &fsl_ssi_dai_ops, |
| 1002 | }; |
| 1003 | |
| 1004 | static const struct snd_soc_component_driver fsl_ssi_component = { |
| 1005 | .name = "fsl-ssi", |
| 1006 | }; |
| 1007 | |
| 1008 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
| 1009 | .ac97_control = 1, |
| 1010 | .playback = { |
| 1011 | .stream_name = "AC97 Playback", |
| 1012 | .channels_min = 2, |
| 1013 | .channels_max = 2, |
| 1014 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 1015 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
| 1016 | }, |
| 1017 | .capture = { |
| 1018 | .stream_name = "AC97 Capture", |
| 1019 | .channels_min = 2, |
| 1020 | .channels_max = 2, |
| 1021 | .rates = SNDRV_PCM_RATE_48000, |
| 1022 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
| 1023 | }, |
| 1024 | .ops = &fsl_ssi_dai_ops, |
| 1025 | }; |
| 1026 | |
| 1027 | |
| 1028 | static struct fsl_ssi_private *fsl_ac97_data; |
| 1029 | |
| 1030 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
| 1031 | unsigned short val) |
| 1032 | { |
| 1033 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; |
| 1034 | unsigned int lreg; |
| 1035 | unsigned int lval; |
| 1036 | |
| 1037 | if (reg > 0x7f) |
| 1038 | return; |
| 1039 | |
| 1040 | |
| 1041 | lreg = reg << 12; |
| 1042 | write_ssi(lreg, &ssi->sacadd); |
| 1043 | |
| 1044 | lval = val << 4; |
| 1045 | write_ssi(lval , &ssi->sacdat); |
| 1046 | |
| 1047 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, |
| 1048 | CCSR_SSI_SACNT_WR); |
| 1049 | udelay(100); |
| 1050 | } |
| 1051 | |
| 1052 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
| 1053 | unsigned short reg) |
| 1054 | { |
| 1055 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; |
| 1056 | |
| 1057 | unsigned short val = -1; |
| 1058 | unsigned int lreg; |
| 1059 | |
| 1060 | lreg = (reg & 0x7f) << 12; |
| 1061 | write_ssi(lreg, &ssi->sacadd); |
| 1062 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, |
| 1063 | CCSR_SSI_SACNT_RD); |
| 1064 | |
| 1065 | udelay(100); |
| 1066 | |
| 1067 | val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; |
| 1068 | |
| 1069 | return val; |
| 1070 | } |
| 1071 | |
| 1072 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { |
| 1073 | .read = fsl_ssi_ac97_read, |
| 1074 | .write = fsl_ssi_ac97_write, |
| 1075 | }; |
| 1076 | |
| 1077 | /** |
| 1078 | * Make every character in a string lower-case |
| 1079 | */ |
| 1080 | static void make_lowercase(char *s) |
| 1081 | { |
| 1082 | char *p = s; |
| 1083 | char c; |
| 1084 | |
| 1085 | while ((c = *p)) { |
| 1086 | if ((c >= 'A') && (c <= 'Z')) |
| 1087 | *p = c + ('a' - 'A'); |
| 1088 | p++; |
| 1089 | } |
| 1090 | } |
| 1091 | |
| 1092 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
| 1093 | struct fsl_ssi_private *ssi_private, void __iomem *iomem) |
| 1094 | { |
| 1095 | struct device_node *np = pdev->dev.of_node; |
| 1096 | u32 dmas[4]; |
| 1097 | int ret; |
| 1098 | |
| 1099 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); |
| 1100 | if (IS_ERR(ssi_private->clk)) { |
| 1101 | ret = PTR_ERR(ssi_private->clk); |
| 1102 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); |
| 1103 | return ret; |
| 1104 | } |
| 1105 | |
| 1106 | ret = clk_prepare_enable(ssi_private->clk); |
| 1107 | if (ret) { |
| 1108 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); |
| 1109 | return ret; |
| 1110 | } |
| 1111 | |
| 1112 | /* For those SLAVE implementations, we ingore non-baudclk cases |
| 1113 | * and, instead, abandon MASTER mode that needs baud clock. |
| 1114 | */ |
| 1115 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); |
| 1116 | if (IS_ERR(ssi_private->baudclk)) |
| 1117 | dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", |
| 1118 | PTR_ERR(ssi_private->baudclk)); |
| 1119 | |
| 1120 | /* |
| 1121 | * We have burstsize be "fifo_depth - 2" to match the SSI |
| 1122 | * watermark setting in fsl_ssi_startup(). |
| 1123 | */ |
| 1124 | ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; |
| 1125 | ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; |
| 1126 | ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + |
| 1127 | offsetof(struct ccsr_ssi, stx0); |
| 1128 | ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + |
| 1129 | offsetof(struct ccsr_ssi, srx0); |
| 1130 | |
| 1131 | ret = !of_property_read_u32_array(np, "dmas", dmas, 4); |
| 1132 | if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { |
| 1133 | ssi_private->use_dual_fifo = true; |
| 1134 | /* When using dual fifo mode, we need to keep watermark |
| 1135 | * as even numbers due to dma script limitation. |
| 1136 | */ |
| 1137 | ssi_private->dma_params_tx.maxburst &= ~0x1; |
| 1138 | ssi_private->dma_params_rx.maxburst &= ~0x1; |
| 1139 | } |
| 1140 | |
| 1141 | if (!ssi_private->use_dma) { |
| 1142 | |
| 1143 | /* |
| 1144 | * Some boards use an incompatible codec. To get it |
| 1145 | * working, we are using imx-fiq-pcm-audio, that |
| 1146 | * can handle those codecs. DMA is not possible in this |
| 1147 | * situation. |
| 1148 | */ |
| 1149 | |
| 1150 | ssi_private->fiq_params.irq = ssi_private->irq; |
| 1151 | ssi_private->fiq_params.base = iomem; |
| 1152 | ssi_private->fiq_params.dma_params_rx = |
| 1153 | &ssi_private->dma_params_rx; |
| 1154 | ssi_private->fiq_params.dma_params_tx = |
| 1155 | &ssi_private->dma_params_tx; |
| 1156 | |
| 1157 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); |
| 1158 | if (ret) |
| 1159 | goto error_pcm; |
| 1160 | } else { |
| 1161 | ret = imx_pcm_dma_init(pdev); |
| 1162 | if (ret) |
| 1163 | goto error_pcm; |
| 1164 | } |
| 1165 | |
| 1166 | return 0; |
| 1167 | |
| 1168 | error_pcm: |
| 1169 | clk_disable_unprepare(ssi_private->clk); |
| 1170 | |
| 1171 | return ret; |
| 1172 | } |
| 1173 | |
| 1174 | static void fsl_ssi_imx_clean(struct platform_device *pdev, |
| 1175 | struct fsl_ssi_private *ssi_private) |
| 1176 | { |
| 1177 | if (!ssi_private->use_dma) |
| 1178 | imx_pcm_fiq_exit(pdev); |
| 1179 | clk_disable_unprepare(ssi_private->clk); |
| 1180 | } |
| 1181 | |
| 1182 | static int fsl_ssi_probe(struct platform_device *pdev) |
| 1183 | { |
| 1184 | struct fsl_ssi_private *ssi_private; |
| 1185 | int ret = 0; |
| 1186 | struct device_node *np = pdev->dev.of_node; |
| 1187 | const struct of_device_id *of_id; |
| 1188 | const char *p, *sprop; |
| 1189 | const uint32_t *iprop; |
| 1190 | struct resource res; |
| 1191 | char name[64]; |
| 1192 | |
| 1193 | /* SSIs that are not connected on the board should have a |
| 1194 | * status = "disabled" |
| 1195 | * property in their device tree nodes. |
| 1196 | */ |
| 1197 | if (!of_device_is_available(np)) |
| 1198 | return -ENODEV; |
| 1199 | |
| 1200 | of_id = of_match_device(fsl_ssi_ids, &pdev->dev); |
| 1201 | if (!of_id || !of_id->data) |
| 1202 | return -EINVAL; |
| 1203 | |
| 1204 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), |
| 1205 | GFP_KERNEL); |
| 1206 | if (!ssi_private) { |
| 1207 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
| 1208 | return -ENOMEM; |
| 1209 | } |
| 1210 | |
| 1211 | ssi_private->soc = of_id->data; |
| 1212 | |
| 1213 | sprop = of_get_property(np, "fsl,mode", NULL); |
| 1214 | if (sprop) { |
| 1215 | if (!strcmp(sprop, "ac97-slave")) |
| 1216 | ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; |
| 1217 | else if (!strcmp(sprop, "i2s-slave")) |
| 1218 | ssi_private->dai_fmt = SND_SOC_DAIFMT_I2S | |
| 1219 | SND_SOC_DAIFMT_CBM_CFM; |
| 1220 | } |
| 1221 | |
| 1222 | ssi_private->use_dma = !of_property_read_bool(np, |
| 1223 | "fsl,fiq-stream-filter"); |
| 1224 | |
| 1225 | if (fsl_ssi_is_ac97(ssi_private)) { |
| 1226 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, |
| 1227 | sizeof(fsl_ssi_ac97_dai)); |
| 1228 | |
| 1229 | fsl_ac97_data = ssi_private; |
| 1230 | |
| 1231 | snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); |
| 1232 | } else { |
| 1233 | /* Initialize this copy of the CPU DAI driver structure */ |
| 1234 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, |
| 1235 | sizeof(fsl_ssi_dai_template)); |
| 1236 | } |
| 1237 | ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); |
| 1238 | |
| 1239 | /* Get the addresses and IRQ */ |
| 1240 | ret = of_address_to_resource(np, 0, &res); |
| 1241 | if (ret) { |
| 1242 | dev_err(&pdev->dev, "could not determine device resources\n"); |
| 1243 | return ret; |
| 1244 | } |
| 1245 | ssi_private->ssi = of_iomap(np, 0); |
| 1246 | if (!ssi_private->ssi) { |
| 1247 | dev_err(&pdev->dev, "could not map device resources\n"); |
| 1248 | return -ENOMEM; |
| 1249 | } |
| 1250 | ssi_private->ssi_phys = res.start; |
| 1251 | |
| 1252 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
| 1253 | if (!ssi_private->irq) { |
| 1254 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
| 1255 | return -ENXIO; |
| 1256 | } |
| 1257 | |
| 1258 | /* Are the RX and the TX clocks locked? */ |
| 1259 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
| 1260 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
| 1261 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
| 1262 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; |
| 1263 | } |
| 1264 | |
| 1265 | /* Determine the FIFO depth. */ |
| 1266 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); |
| 1267 | if (iprop) |
| 1268 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
| 1269 | else |
| 1270 | /* Older 8610 DTs didn't have the fifo-depth property */ |
| 1271 | ssi_private->fifo_depth = 8; |
| 1272 | |
| 1273 | dev_set_drvdata(&pdev->dev, ssi_private); |
| 1274 | |
| 1275 | if (ssi_private->soc->imx) { |
| 1276 | ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi); |
| 1277 | if (ret) |
| 1278 | goto error_irqmap; |
| 1279 | } |
| 1280 | |
| 1281 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
| 1282 | &ssi_private->cpu_dai_drv, 1); |
| 1283 | if (ret) { |
| 1284 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
| 1285 | goto error_asoc_register; |
| 1286 | } |
| 1287 | |
| 1288 | if (ssi_private->use_dma) { |
| 1289 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, |
| 1290 | fsl_ssi_isr, 0, dev_name(&pdev->dev), |
| 1291 | ssi_private); |
| 1292 | if (ret < 0) { |
| 1293 | dev_err(&pdev->dev, "could not claim irq %u\n", |
| 1294 | ssi_private->irq); |
| 1295 | goto error_irq; |
| 1296 | } |
| 1297 | } |
| 1298 | |
| 1299 | ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); |
| 1300 | if (ret) |
| 1301 | goto error_asoc_register; |
| 1302 | |
| 1303 | /* |
| 1304 | * If codec-handle property is missing from SSI node, we assume |
| 1305 | * that the machine driver uses new binding which does not require |
| 1306 | * SSI driver to trigger machine driver's probe. |
| 1307 | */ |
| 1308 | if (!of_get_property(np, "codec-handle", NULL)) |
| 1309 | goto done; |
| 1310 | |
| 1311 | /* Trigger the machine driver's probe function. The platform driver |
| 1312 | * name of the machine driver is taken from /compatible property of the |
| 1313 | * device tree. We also pass the address of the CPU DAI driver |
| 1314 | * structure. |
| 1315 | */ |
| 1316 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
| 1317 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ |
| 1318 | p = strrchr(sprop, ','); |
| 1319 | if (p) |
| 1320 | sprop = p + 1; |
| 1321 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); |
| 1322 | make_lowercase(name); |
| 1323 | |
| 1324 | ssi_private->pdev = |
| 1325 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
| 1326 | if (IS_ERR(ssi_private->pdev)) { |
| 1327 | ret = PTR_ERR(ssi_private->pdev); |
| 1328 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
| 1329 | goto error_sound_card; |
| 1330 | } |
| 1331 | |
| 1332 | done: |
| 1333 | if (ssi_private->dai_fmt) |
| 1334 | _fsl_ssi_set_dai_fmt(ssi_private, ssi_private->dai_fmt); |
| 1335 | |
| 1336 | return 0; |
| 1337 | |
| 1338 | error_sound_card: |
| 1339 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
| 1340 | |
| 1341 | error_irq: |
| 1342 | snd_soc_unregister_component(&pdev->dev); |
| 1343 | |
| 1344 | error_asoc_register: |
| 1345 | if (ssi_private->soc->imx) |
| 1346 | fsl_ssi_imx_clean(pdev, ssi_private); |
| 1347 | |
| 1348 | error_irqmap: |
| 1349 | if (ssi_private->use_dma) |
| 1350 | irq_dispose_mapping(ssi_private->irq); |
| 1351 | |
| 1352 | return ret; |
| 1353 | } |
| 1354 | |
| 1355 | static int fsl_ssi_remove(struct platform_device *pdev) |
| 1356 | { |
| 1357 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
| 1358 | |
| 1359 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
| 1360 | |
| 1361 | if (ssi_private->pdev) |
| 1362 | platform_device_unregister(ssi_private->pdev); |
| 1363 | snd_soc_unregister_component(&pdev->dev); |
| 1364 | |
| 1365 | if (ssi_private->soc->imx) |
| 1366 | fsl_ssi_imx_clean(pdev, ssi_private); |
| 1367 | |
| 1368 | if (ssi_private->use_dma) |
| 1369 | irq_dispose_mapping(ssi_private->irq); |
| 1370 | |
| 1371 | return 0; |
| 1372 | } |
| 1373 | |
| 1374 | static struct platform_driver fsl_ssi_driver = { |
| 1375 | .driver = { |
| 1376 | .name = "fsl-ssi-dai", |
| 1377 | .owner = THIS_MODULE, |
| 1378 | .of_match_table = fsl_ssi_ids, |
| 1379 | }, |
| 1380 | .probe = fsl_ssi_probe, |
| 1381 | .remove = fsl_ssi_remove, |
| 1382 | }; |
| 1383 | |
| 1384 | module_platform_driver(fsl_ssi_driver); |
| 1385 | |
| 1386 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
| 1387 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
| 1388 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); |
| 1389 | MODULE_LICENSE("GPL v2"); |