1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
4 specification and can be connected in various topologies to suit a particular
5 SoCs tracing needs. These trace components can generally be classified as
6 sinks, links and sources. Trace data produced by one or more sources flows
7 through the intermediate links connecting the source to the currently selected
8 sink. Each CoreSight component device should use these properties to describe
9 its hardware characteristcs.
11 * Required properties for all components *except* non-configurable replicators:
13 * compatible: These have to be supplemented with "arm,primecell" as
14 drivers are using the AMBA bus interface. Possible values include:
15 - "arm,coresight-etb10", "arm,primecell";
16 - "arm,coresight-tpiu", "arm,primecell";
17 - "arm,coresight-tmc", "arm,primecell";
18 - "arm,coresight-funnel", "arm,primecell";
19 - "arm,coresight-etm3x", "arm,primecell";
20 - "arm,coresight-etm4x", "arm,primecell";
21 - "qcom,coresight-replicator1x", "arm,primecell";
22 - "arm,coresight-stm", "arm,primecell"; [1]
24 * reg: physical base address and length of the register
25 set(s) of the component.
27 * clocks: the clocks associated to this component.
29 * clock-names: the name of the clocks referenced by the code.
30 Since we are using the AMBA framework, the name of the clock
31 providing the interconnect should be "apb_pclk", and some
32 coresight blocks also have an additional clock "atclk", which
33 clocks the core of that coresight component. The latter clock
36 * port or ports: The representation of the component's port
37 layout using the generic DT graph presentation found in
40 * Additional required properties for System Trace Macrocells (STM):
41 * reg: along with the physical base address and length of the register
42 set as described above, another entry is required to describe the
43 mapping of the extended stimulus port area.
45 * reg-names: the only acceptable values are "stm-base" and
46 "stm-stimulus-base", each corresponding to the areas defined in "reg".
48 * Required properties for devices that don't show up on the AMBA bus, such as
49 non-configurable replicators:
51 * compatible: Currently supported value is (note the absence of the
53 - "arm,coresight-replicator"
55 * port or ports: same as above.
57 * Optional properties for ETM/PTMs:
59 * arm,cp14: must be present if the system accesses ETM/PTM management
60 registers via co-processor 14.
62 * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
63 source is considered to belong to CPU0.
65 * Optional property for TMC:
67 * arm,buffer-size: size of contiguous buffer space for TMC ETR
68 (embedded trace router)
75 compatible = "arm,coresight-etb10", "arm,primecell";
76 reg = <0 0x20010000 0 0x1000>;
79 clock-names = "apb_pclk";
81 etb_in_port: endpoint@0 {
83 remote-endpoint = <&replicator_out_port0>;
89 compatible = "arm,coresight-tpiu", "arm,primecell";
90 reg = <0 0x20030000 0 0x1000>;
93 clock-names = "apb_pclk";
95 tpiu_in_port: endpoint@0 {
97 remote-endpoint = <&replicator_out_port1>;
104 /* non-configurable replicators don't show up on the
105 * AMBA bus. As such no need to add "arm,primecell".
107 compatible = "arm,coresight-replicator";
110 #address-cells = <1>;
113 /* replicator output ports */
116 replicator_out_port0: endpoint {
117 remote-endpoint = <&etb_in_port>;
123 replicator_out_port1: endpoint {
124 remote-endpoint = <&tpiu_in_port>;
128 /* replicator input port */
131 replicator_in_port0: endpoint {
133 remote-endpoint = <&funnel_out_port0>;
140 compatible = "arm,coresight-funnel", "arm,primecell";
141 reg = <0 0x20040000 0 0x1000>;
143 clocks = <&oscclk6a>;
144 clock-names = "apb_pclk";
146 #address-cells = <1>;
149 /* funnel output port */
152 funnel_out_port0: endpoint {
154 <&replicator_in_port0>;
158 /* funnel input ports */
161 funnel_in_port0: endpoint {
163 remote-endpoint = <&ptm0_out_port>;
169 funnel_in_port1: endpoint {
171 remote-endpoint = <&ptm1_out_port>;
177 funnel_in_port2: endpoint {
179 remote-endpoint = <&etm0_out_port>;
188 compatible = "arm,coresight-etm3x", "arm,primecell";
189 reg = <0 0x2201c000 0 0x1000>;
192 clocks = <&oscclk6a>;
193 clock-names = "apb_pclk";
195 ptm0_out_port: endpoint {
196 remote-endpoint = <&funnel_in_port0>;
202 compatible = "arm,coresight-etm3x", "arm,primecell";
203 reg = <0 0x2201d000 0 0x1000>;
206 clocks = <&oscclk6a>;
207 clock-names = "apb_pclk";
209 ptm1_out_port: endpoint {
210 remote-endpoint = <&funnel_in_port1>;
217 compatible = "arm,coresight-stm", "arm,primecell";
218 reg = <0 0x20100000 0 0x1000>,
219 <0 0x28000000 0 0x180000>;
220 reg-names = "stm-base", "stm-stimulus-base";
222 clocks = <&soc_smc50mhz>;
223 clock-names = "apb_pclk";
225 stm_out_port: endpoint {
226 remote-endpoint = <&main_funnel_in_port2>;
231 [1]. There is currently two version of STM: STM32 and STM500. Both
232 have the same HW interface and as such don't need an explicit binding name.