1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
4 specification and can be connected in various topologies to suit a particular
5 SoCs tracing needs. These trace components can generally be classified as
6 sinks, links and sources. Trace data produced by one or more sources flows
7 through the intermediate links connecting the source to the currently selected
8 sink. Each CoreSight component device should use these properties to describe
9 its hardware characteristcs.
11 * Required properties for all components *except* non-configurable replicators:
13 * compatible: These have to be supplemented with "arm,primecell" as
14 drivers are using the AMBA bus interface. Possible values include:
15 - "arm,coresight-etb10", "arm,primecell";
16 - "arm,coresight-tpiu", "arm,primecell";
17 - "arm,coresight-tmc", "arm,primecell";
18 - "arm,coresight-funnel", "arm,primecell";
19 - "arm,coresight-etm3x", "arm,primecell";
20 - "qcom,coresight-replicator1x", "arm,primecell";
22 * reg: physical base address and length of the register
23 set(s) of the component.
25 * clocks: the clocks associated to this component.
27 * clock-names: the name of the clocks referenced by the code.
28 Since we are using the AMBA framework, the name of the clock
29 providing the interconnect should be "apb_pclk", and some
30 coresight blocks also have an additional clock "atclk", which
31 clocks the core of that coresight component. The latter clock
34 * port or ports: The representation of the component's port
35 layout using the generic DT graph presentation found in
38 * Required properties for devices that don't show up on the AMBA bus, such as
39 non-configurable replicators:
41 * compatible: Currently supported value is (note the absence of the
43 - "arm,coresight-replicator"
45 * port or ports: same as above.
47 * Optional properties for ETM/PTMs:
49 * arm,cp14: must be present if the system accesses ETM/PTM management
50 registers via co-processor 14.
52 * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
53 source is considered to belong to CPU0.
55 * Optional property for TMC:
57 * arm,buffer-size: size of contiguous buffer space for TMC ETR
58 (embedded trace router)
65 compatible = "arm,coresight-etb10", "arm,primecell";
66 reg = <0 0x20010000 0 0x1000>;
69 clock-names = "apb_pclk";
71 etb_in_port: endpoint@0 {
73 remote-endpoint = <&replicator_out_port0>;
79 compatible = "arm,coresight-tpiu", "arm,primecell";
80 reg = <0 0x20030000 0 0x1000>;
83 clock-names = "apb_pclk";
85 tpiu_in_port: endpoint@0 {
87 remote-endpoint = <&replicator_out_port1>;
94 /* non-configurable replicators don't show up on the
95 * AMBA bus. As such no need to add "arm,primecell".
97 compatible = "arm,coresight-replicator";
100 #address-cells = <1>;
103 /* replicator output ports */
106 replicator_out_port0: endpoint {
107 remote-endpoint = <&etb_in_port>;
113 replicator_out_port1: endpoint {
114 remote-endpoint = <&tpiu_in_port>;
118 /* replicator input port */
121 replicator_in_port0: endpoint {
123 remote-endpoint = <&funnel_out_port0>;
130 compatible = "arm,coresight-funnel", "arm,primecell";
131 reg = <0 0x20040000 0 0x1000>;
133 clocks = <&oscclk6a>;
134 clock-names = "apb_pclk";
136 #address-cells = <1>;
139 /* funnel output port */
142 funnel_out_port0: endpoint {
144 <&replicator_in_port0>;
148 /* funnel input ports */
151 funnel_in_port0: endpoint {
153 remote-endpoint = <&ptm0_out_port>;
159 funnel_in_port1: endpoint {
161 remote-endpoint = <&ptm1_out_port>;
167 funnel_in_port2: endpoint {
169 remote-endpoint = <&etm0_out_port>;
178 compatible = "arm,coresight-etm3x", "arm,primecell";
179 reg = <0 0x2201c000 0 0x1000>;
182 clocks = <&oscclk6a>;
183 clock-names = "apb_pclk";
185 ptm0_out_port: endpoint {
186 remote-endpoint = <&funnel_in_port0>;
192 compatible = "arm,coresight-etm3x", "arm,primecell";
193 reg = <0 0x2201d000 0 0x1000>;
196 clocks = <&oscclk6a>;
197 clock-names = "apb_pclk";
199 ptm1_out_port: endpoint {
200 remote-endpoint = <&funnel_in_port1>;