5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
180 "nvidia,tegra132-denver"
185 Value type: <stringlist>
186 Usage and definition depend on ARM architecture version.
187 # On ARM v8 64-bit this property is required and must
191 # On ARM 32-bit systems this property is optional and
193 "allwinner,sun6i-a31"
194 "allwinner,sun8i-a23"
198 "marvell,armada-375-smp"
199 "marvell,armada-380-smp"
200 "marvell,armada-390-smp"
201 "marvell,armada-xp-smp"
202 "mediatek,mt6589-smp"
203 "mediatek,mt81xx-tz-smp"
207 "rockchip,rk3036-smp"
208 "rockchip,rk3066-smp"
212 Usage: required for systems that have an "enable-method"
213 property value of "spin-table".
214 Value type: <prop-encoded-array>
216 # On ARM v8 64-bit systems must be a two cell
217 property identifying a 64-bit zero-initialised
221 Usage: required for systems that have an "enable-method"
222 property value of "qcom,kpss-acc-v1" or
224 Value type: <phandle>
225 Definition: Specifies the SAW[1] node associated with this CPU.
228 Usage: required for systems that have an "enable-method"
229 property value of "qcom,kpss-acc-v1" or
231 Value type: <phandle>
232 Definition: Specifies the ACC[2] node associated with this CPU.
236 Value type: <prop-encoded-array>
238 # List of phandles to idle state nodes supported
242 Usage: optional for systems that have an "enable-method"
243 property value of "rockchip,rk3066-smp"
244 While optional, it is the preferred way to get access to
245 the cpu-core power-domains.
246 Value type: <phandle>
247 Definition: Specifies the syscon node controlling the cpu core
250 - dynamic-power-coefficient
252 Value type: <prop-encoded-array>
253 Definition: A u32 value that represents the running time dynamic
254 power coefficient in units of mW/MHz/uV^2. The
255 coefficient can either be calculated from power
256 measurements or derived by analysis.
258 The dynamic power consumption of the CPU is
259 proportional to the square of the Voltage (V) and
260 the clock frequency (f). The coefficient is used to
261 calculate the dynamic power as below -
263 Pdyn = dynamic-power-coefficient * V^2 * f
265 where voltage is in uV, frequency is in MHz.
267 Example 1 (dual-cluster big.LITTLE system 32-bit):
271 #address-cells = <1>;
275 compatible = "arm,cortex-a15";
281 compatible = "arm,cortex-a15";
287 compatible = "arm,cortex-a7";
293 compatible = "arm,cortex-a7";
298 Example 2 (Cortex-A8 uniprocessor 32-bit system):
302 #address-cells = <1>;
306 compatible = "arm,cortex-a8";
311 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
315 #address-cells = <1>;
319 compatible = "arm,arm926ej-s";
324 Example 4 (ARM Cortex-A57 64-bit system):
328 #address-cells = <2>;
332 compatible = "arm,cortex-a57";
334 enable-method = "spin-table";
335 cpu-release-addr = <0 0x20000000>;
340 compatible = "arm,cortex-a57";
342 enable-method = "spin-table";
343 cpu-release-addr = <0 0x20000000>;
348 compatible = "arm,cortex-a57";
350 enable-method = "spin-table";
351 cpu-release-addr = <0 0x20000000>;
356 compatible = "arm,cortex-a57";
358 enable-method = "spin-table";
359 cpu-release-addr = <0 0x20000000>;
364 compatible = "arm,cortex-a57";
366 enable-method = "spin-table";
367 cpu-release-addr = <0 0x20000000>;
372 compatible = "arm,cortex-a57";
374 enable-method = "spin-table";
375 cpu-release-addr = <0 0x20000000>;
380 compatible = "arm,cortex-a57";
382 enable-method = "spin-table";
383 cpu-release-addr = <0 0x20000000>;
388 compatible = "arm,cortex-a57";
390 enable-method = "spin-table";
391 cpu-release-addr = <0 0x20000000>;
396 compatible = "arm,cortex-a57";
398 enable-method = "spin-table";
399 cpu-release-addr = <0 0x20000000>;
404 compatible = "arm,cortex-a57";
406 enable-method = "spin-table";
407 cpu-release-addr = <0 0x20000000>;
412 compatible = "arm,cortex-a57";
414 enable-method = "spin-table";
415 cpu-release-addr = <0 0x20000000>;
420 compatible = "arm,cortex-a57";
422 enable-method = "spin-table";
423 cpu-release-addr = <0 0x20000000>;
428 compatible = "arm,cortex-a57";
430 enable-method = "spin-table";
431 cpu-release-addr = <0 0x20000000>;
436 compatible = "arm,cortex-a57";
438 enable-method = "spin-table";
439 cpu-release-addr = <0 0x20000000>;
444 compatible = "arm,cortex-a57";
446 enable-method = "spin-table";
447 cpu-release-addr = <0 0x20000000>;
452 compatible = "arm,cortex-a57";
454 enable-method = "spin-table";
455 cpu-release-addr = <0 0x20000000>;
460 [1] arm/msm/qcom,saw2.txt
461 [2] arm/msm/qcom,kpss-acc.txt
462 [3] ARM Linux kernel documentation - idle states bindings
463 Documentation/devicetree/bindings/arm/idle-states.txt