5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
178 "nvidia,tegra132-denver"
182 Value type: <stringlist>
183 Usage and definition depend on ARM architecture version.
184 # On ARM v8 64-bit this property is required and must
188 # On ARM 32-bit systems this property is optional and
190 "allwinner,sun6i-a31"
193 "marvell,armada-375-smp"
194 "marvell,armada-380-smp"
195 "marvell,armada-xp-smp"
199 "rockchip,rk3066-smp"
202 Usage: required for systems that have an "enable-method"
203 property value of "spin-table".
204 Value type: <prop-encoded-array>
206 # On ARM v8 64-bit systems must be a two cell
207 property identifying a 64-bit zero-initialised
211 Usage: required for systems that have an "enable-method"
212 property value of "qcom,kpss-acc-v1" or
214 Value type: <phandle>
215 Definition: Specifies the SAW[1] node associated with this CPU.
218 Usage: required for systems that have an "enable-method"
219 property value of "qcom,kpss-acc-v1" or
221 Value type: <phandle>
222 Definition: Specifies the ACC[2] node associated with this CPU.
226 Value type: <prop-encoded-array>
228 # List of phandles to idle state nodes supported
232 Usage: optional for systems that have an "enable-method"
233 property value of "rockchip,rk3066-smp"
234 While optional, it is the preferred way to get access to
235 the cpu-core power-domains.
236 Value type: <phandle>
237 Definition: Specifies the syscon node controlling the cpu core
240 Example 1 (dual-cluster big.LITTLE system 32-bit):
244 #address-cells = <1>;
248 compatible = "arm,cortex-a15";
254 compatible = "arm,cortex-a15";
260 compatible = "arm,cortex-a7";
266 compatible = "arm,cortex-a7";
271 Example 2 (Cortex-A8 uniprocessor 32-bit system):
275 #address-cells = <1>;
279 compatible = "arm,cortex-a8";
284 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
288 #address-cells = <1>;
292 compatible = "arm,arm926ej-s";
297 Example 4 (ARM Cortex-A57 64-bit system):
301 #address-cells = <2>;
305 compatible = "arm,cortex-a57";
307 enable-method = "spin-table";
308 cpu-release-addr = <0 0x20000000>;
313 compatible = "arm,cortex-a57";
315 enable-method = "spin-table";
316 cpu-release-addr = <0 0x20000000>;
321 compatible = "arm,cortex-a57";
323 enable-method = "spin-table";
324 cpu-release-addr = <0 0x20000000>;
329 compatible = "arm,cortex-a57";
331 enable-method = "spin-table";
332 cpu-release-addr = <0 0x20000000>;
337 compatible = "arm,cortex-a57";
339 enable-method = "spin-table";
340 cpu-release-addr = <0 0x20000000>;
345 compatible = "arm,cortex-a57";
347 enable-method = "spin-table";
348 cpu-release-addr = <0 0x20000000>;
353 compatible = "arm,cortex-a57";
355 enable-method = "spin-table";
356 cpu-release-addr = <0 0x20000000>;
361 compatible = "arm,cortex-a57";
363 enable-method = "spin-table";
364 cpu-release-addr = <0 0x20000000>;
369 compatible = "arm,cortex-a57";
371 enable-method = "spin-table";
372 cpu-release-addr = <0 0x20000000>;
377 compatible = "arm,cortex-a57";
379 enable-method = "spin-table";
380 cpu-release-addr = <0 0x20000000>;
385 compatible = "arm,cortex-a57";
387 enable-method = "spin-table";
388 cpu-release-addr = <0 0x20000000>;
393 compatible = "arm,cortex-a57";
395 enable-method = "spin-table";
396 cpu-release-addr = <0 0x20000000>;
401 compatible = "arm,cortex-a57";
403 enable-method = "spin-table";
404 cpu-release-addr = <0 0x20000000>;
409 compatible = "arm,cortex-a57";
411 enable-method = "spin-table";
412 cpu-release-addr = <0 0x20000000>;
417 compatible = "arm,cortex-a57";
419 enable-method = "spin-table";
420 cpu-release-addr = <0 0x20000000>;
425 compatible = "arm,cortex-a57";
427 enable-method = "spin-table";
428 cpu-release-addr = <0 0x20000000>;
433 [1] arm/msm/qcom,saw2.txt
434 [2] arm/msm/qcom,kpss-acc.txt
435 [3] ARM Linux kernel documentation - idle states bindings
436 Documentation/devicetree/bindings/arm/idle-states.txt