Documentation/devicetree/bindings/arm/exynos/power_domain.txt

   1 * Samsung Exynos Power Domains
   2
   3 Exynos processors include support for multiple power domains which are used
   4 to gate power to one or more peripherals on the processor.
   5
   6 Required Properties:
   7 - compatible: should be one of the following.
   8     * samsung,exynos4210-pd - for exynos4210 type power domain.
   9 - reg: physical base address of the controller and length of memory mapped
  10     region.
  11 - #power-domain-cells: number of cells in power domain specifier;
  12     must be 0.
  13
  14 Optional Properties:
  15 - clocks: List of clock handles. The parent clocks of the input clocks to the
  16         devices in this power domain are set to oscclk before power gating
  17         and restored back after powering on a domain. This is required for
  18         all domains which are powered on and off and not required for unused
  19         domains.
  20 - clock-names: The following clocks can be specified:
  21         - oscclk: Oscillator clock.
  22         - pclkN, clkN: Pairs of parent of input clock and input clock to the
  23                 devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
  24                 are supported currently.
  25 - power-domains: phandle pointing to the parent power domain, for more details
  26                  see Documentation/devicetree/bindings/power/power_domain.txt
  27
  28 Node of a device using power domains must have a power-domains property
  29 defined with a phandle to respective power domain.
  30
  31 Example:
  32
  33         lcd0: power-domain-lcd0 {
  34                 compatible = "samsung,exynos4210-pd";
  35                 reg = <0x10023C00 0x10>;
  36                 #power-domain-cells = <0>;
  37         };
  38
  39         mfc_pd: power-domain@10044060 {
  40                 compatible = "samsung,exynos4210-pd";
  41                 reg = <0x10044060 0x20>;
  42                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
  43                         <&clock CLK_MOUT_USER_ACLK333>;
  44                 clock-names = "oscclk", "pclk0", "clk0";
  45                 #power-domain-cells = <0>;
  46         };
  47
  48 See Documentation/devicetree/bindings/power/power_domain.txt for description
  49 of consumer-side bindings.