Documentation/devicetree/bindings/arm/pmu.txt

   1 * ARM Performance Monitor Units
   2
   3 ARM cores often have a PMU for counting cpu and cache events like cache misses
   4 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
   5 representation in the device tree should be done as under:-
   6
   7 Required properties:
   8
   9 - compatible : should be one of
  10         "apm,potenza-pmu"
  11         "arm,armv8-pmuv3"
  12         "arm,cortex-a72-pmu"
  13         "arm,cortex-a57-pmu"
  14         "arm,cortex-a53-pmu"
  15         "arm,cortex-a17-pmu"
  16         "arm,cortex-a15-pmu"
  17         "arm,cortex-a12-pmu"
  18         "arm,cortex-a9-pmu"
  19         "arm,cortex-a8-pmu"
  20         "arm,cortex-a7-pmu"
  21         "arm,cortex-a5-pmu"
  22         "arm,arm11mpcore-pmu"
  23         "arm,arm1176-pmu"
  24         "arm,arm1136-pmu"
  25         "brcm,vulcan-pmu"
  26         "cavium,thunder-pmu"
  27         "qcom,scorpion-pmu"
  28         "qcom,scorpion-mp-pmu"
  29         "qcom,krait-pmu"
  30 - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
  31                interrupt (PPI) then 1 interrupt should be specified.
  32
  33 Optional properties:
  34
  35 - interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
  36                        nodes corresponding directly to the affinity of
  37                        the SPIs listed in the interrupts property.
  38
  39                        When using a PPI, specifies a list of phandles to CPU
  40                        nodes corresponding to the set of CPUs which have
  41                        a PMU of this type signalling the PPI listed in the
  42                        interrupts property, unless this is already specified
  43                        by the PPI interrupt specifier itself (in which case
  44                        the interrupt-affinity property shouldn't be present).
  45
  46                        This property should be present when there is more than
  47                        a single SPI.
  48
  49
  50 - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
  51                      events.
  52
  53 - secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
  54                       (SDER) is accessible. This will cause the driver to do
  55                       any setup required that is only possible in ARMv7 secure
  56                       state. If not present the ARMv7 SDER will not be touched,
  57                       which means the PMU may fail to operate unless external
  58                       code (bootloader or security monitor) has performed the
  59                       appropriate initialisation. Note that this property is
  60                       not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
  61                       in Non-secure state.
  62
  63 Example:
  64
  65 pmu {
  66         compatible = "arm,cortex-a9-pmu";
  67         interrupts = <100 101>;
  68 };