Documentation/devicetree/bindings/ata/sata_highbank.txt

   1 * Calxeda AHCI SATA Controller
   2
   3 SATA nodes are defined to describe on-chip Serial ATA controllers.
   4 The Calxeda SATA controller mostly conforms to the AHCI interface
   5 with some special extensions to add functionality.
   6 Each SATA controller should have its own node.
   7
   8 Required properties:
   9 - compatible        : compatible list, contains "calxeda,hb-ahci"
  10 - interrupts        : <interrupt mapping for SATA IRQ>
  11 - reg               : <registers mapping>
  12
  13 Optional properties:
  14 - dma-coherent      : Present if dma operations are coherent
  15 - calxeda,port-phys : phandle-combophy and lane assignment, which maps each
  16                         SATA port to a combophy and a lane within that
  17                         combophy
  18 - calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
  19                         which indicates that the driver supports SGPIO
  20                         indicator lights using the indicated GPIOs
  21 - calxeda,led-order : a u32 array that map port numbers to offsets within the
  22                         SGPIO bitstream.
  23 - calxeda,tx-atten  : a u32 array that contains TX attenuation override
  24                         codes, one per port. The upper 3 bytes are always
  25                         0 and thus ignored.
  26 - calxeda,pre-clocks : a u32 that indicates the number of additional clock
  27                         cycles to transmit before sending an SGPIO pattern
  28 - calxeda,post-clocks: a u32 that indicates the number of additional clock
  29                         cycles to transmit after sending an SGPIO pattern
  30
  31 Example:
  32         sata@ffe08000 {
  33                 compatible = "calxeda,hb-ahci";
  34                 reg = <0xffe08000 0x1000>;
  35                 interrupts = <115>;
  36                 dma-coherent;
  37                 calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
  38                                         &combophy0 2 &combophy0 3>;
  39                 calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
  40                 calxeda,led-order = <4 0 1 2 3>;
  41                 calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
  42                 calxeda,pre-clocks = <10>;
  43                 calxeda,post-clocks = <0>;
  44         };