Documentation/devicetree/bindings/clock/exynos5250-clock.txt

   1 * Samsung Exynos5250 Clock Controller
   2
   3 The Exynos5250 clock controller generates and supplies clock to various
   4 controllers within the Exynos5250 SoC.
   5
   6 Required Properties:
   7
   8 - comptible: should be one of the following.
   9   - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
  10
  11 - reg: physical base address of the controller and length of memory mapped
  12   region.
  13
  14 - #clock-cells: should be 1.
  15
  16 The following is the list of clocks generated by the controller. Each clock is
  17 assigned an identifier and client nodes use this identifier to specify the
  18 clock which they consume.
  19
  20
  21        [Core Clocks]
  22
  23   Clock                 ID
  24   ----------------------------
  25
  26   fin_pll               1
  27
  28   [Clock Gate for Special Clocks]
  29
  30   Clock                 ID
  31   ----------------------------
  32
  33   sclk_cam_bayer        128
  34   sclk_cam0             129
  35   sclk_cam1             130
  36   sclk_gscl_wa          131
  37   sclk_gscl_wb          132
  38   sclk_fimd1            133
  39   sclk_mipi1            134
  40   sclk_dp               135
  41   sclk_hdmi             136
  42   sclk_pixel            137
  43   sclk_audio0           138
  44   sclk_mmc0             139
  45   sclk_mmc1             140
  46   sclk_mmc2             141
  47   sclk_mmc3             142
  48   sclk_sata             143
  49   sclk_usb3             144
  50   sclk_jpeg             145
  51   sclk_uart0            146
  52   sclk_uart1            147
  53   sclk_uart2            148
  54   sclk_uart3            149
  55   sclk_pwm              150
  56   sclk_audio1           151
  57   sclk_audio2           152
  58   sclk_spdif            153
  59   sclk_spi0             154
  60   sclk_spi1             155
  61   sclk_spi2             156
  62   div_i2s1              157
  63   div_i2s2              158
  64   sclk_hdmiphy          159
  65
  66
  67    [Peripheral Clock Gates]
  68
  69   Clock                 ID
  70   ----------------------------
  71
  72   gscl0                 256
  73   gscl1                 257
  74   gscl2                 258
  75   gscl3                 259
  76   gscl_wa               260
  77   gscl_wb               261
  78   smmu_gscl0            262
  79   smmu_gscl1            263
  80   smmu_gscl2            264
  81   smmu_gscl3            265
  82   mfc                   266
  83   smmu_mfcl             267
  84   smmu_mfcr             268
  85   rotator               269
  86   jpeg                  270
  87   mdma1                 271
  88   smmu_rotator          272
  89   smmu_jpeg             273
  90   smmu_mdma1            274
  91   pdma0                 275
  92   pdma1                 276
  93   sata                  277
  94   usbotg                278
  95   mipi_hsi              279
  96   sdmmc0                280
  97   sdmmc1                281
  98   sdmmc2                282
  99   sdmmc3                283
 100   sromc                 284
 101   usb2                  285
 102   usb3                  286
 103   sata_phyctrl          287
 104   sata_phyi2c           288
 105   uart0                 289
 106   uart1                 290
 107   uart2                 291
 108   uart3                 292
 109   uart4                 293
 110   i2c0                  294
 111   i2c1                  295
 112   i2c2                  296
 113   i2c3                  297
 114   i2c4                  298
 115   i2c5                  299
 116   i2c6                  300
 117   i2c7                  301
 118   i2c_hdmi              302
 119   adc                   303
 120   spi0                  304
 121   spi1                  305
 122   spi2                  306
 123   i2s1                  307
 124   i2s2                  308
 125   pcm1                  309
 126   pcm2                  310
 127   pwm                   311
 128   spdif                 312
 129   ac97                  313
 130   hsi2c0                314
 131   hsi2c1                315
 132   hs12c2                316
 133   hs12c3                317
 134   chipid                318
 135   sysreg                319
 136   pmu                   320
 137   cmu_top               321
 138   cmu_core              322
 139   cmu_mem               323
 140   tzpc0                 324
 141   tzpc1                 325
 142   tzpc2                 326
 143   tzpc3                 327
 144   tzpc4                 328
 145   tzpc5                 329
 146   tzpc6                 330
 147   tzpc7                 331
 148   tzpc8                 332
 149   tzpc9                 333
 150   hdmi_cec              334
 151   mct                   335
 152   wdt                   336
 153   rtc                   337
 154   tmu                   338
 155   fimd1                 339
 156   mie1                  340
 157   dsim0                 341
 158   dp                    342
 159   mixer                 343
 160   hdmi                  344
 161   g2d                   345
 162   mdma0                 346
 163   smmu_mdma0            347
 164
 165
 166    [Clock Muxes]
 167
 168   Clock                 ID
 169   ----------------------------
 170   mout_hdmi             1024
 171
 172
 173 Example 1: An example of a clock controller node is listed below.
 174
 175         clock: clock-controller@0x10010000 {
 176                 compatible = "samsung,exynos5250-clock";
 177                 reg = <0x10010000 0x30000>;
 178                 #clock-cells = <1>;
 179         };
 180
 181 Example 2: UART controller node that consumes the clock generated by the clock
 182            controller. Refer to the standard clock bindings for information
 183            about 'clocks' and 'clock-names' property.
 184
 185         serial@13820000 {
 186                 compatible = "samsung,exynos4210-uart";
 187                 reg = <0x13820000 0x100>;
 188                 interrupts = <0 54 0>;
 189                 clocks = <&clock 314>, <&clock 153>;
 190                 clock-names = "uart", "clk_uart_baud0";
 191         };