Documentation/devicetree/bindings/clock/mvebu-core-clock.txt

   1 * Core Clock bindings for Marvell MVEBU SoCs
   2
   3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
   4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
   5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
   6
   7 The following is a list of provided IDs and clock names on Armada 370/XP:
   8  0 = tclk    (Internal Bus clock)
   9  1 = cpuclk  (CPU clock)
  10  2 = nbclk   (L2 Cache clock)
  11  3 = hclk    (DRAM control clock)
  12  4 = dramclk (DDR clock)
  13
  14 The following is a list of provided IDs and clock names on Armada 375:
  15  0 = tclk    (Internal Bus clock)
  16  1 = cpuclk  (CPU clock)
  17  2 = l2clk   (L2 Cache clock)
  18  3 = ddrclk  (DDR clock)
  19
  20 The following is a list of provided IDs and clock names on Armada 380/385:
  21  0 = tclk    (Internal Bus clock)
  22  1 = cpuclk  (CPU clock)
  23  2 = l2clk   (L2 Cache clock)
  24  3 = ddrclk  (DDR clock)
  25
  26 The following is a list of provided IDs and clock names on Kirkwood and Dove:
  27  0 = tclk   (Internal Bus clock)
  28  1 = cpuclk (CPU0 clock)
  29  2 = l2clk  (L2 Cache clock derived from CPU0 clock)
  30  3 = ddrclk (DDR controller clock derived from CPU0 clock)
  31
  32 The following is a list of provided IDs and clock names on Orion5x:
  33  0 = tclk   (Internal Bus clock)
  34  1 = cpuclk (CPU0 clock)
  35  2 = ddrclk (DDR controller clock derived from CPU0 clock)
  36
  37 Required properties:
  38 - compatible : shall be one of the following:
  39         "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
  40         "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
  41         "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
  42         "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
  43         "marvell,dove-core-clock" - for Dove SoC core clocks
  44         "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
  45         "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
  46         "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
  47         "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
  48         "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
  49 - reg : shall be the register address of the Sample-At-Reset (SAR) register
  50 - #clock-cells : from common clock binding; shall be set to 1
  51
  52 Optional properties:
  53 - clock-output-names : from common clock binding; allows overwrite default clock
  54         output names ("tclk", "cpuclk", "l2clk", "ddrclk")
  55
  56 Example:
  57
  58 core_clk: core-clocks@d0214 {
  59         compatible = "marvell,dove-core-clock";
  60         reg = <0xd0214 0x4>;
  61         #clock-cells = <1>;
  62 };
  63
  64 spi0: spi@10600 {
  65         compatible = "marvell,orion-spi";
  66         /* ... */
  67         /* get tclk from core clock provider */
  68         clocks = <&core_clk 0>;
  69 };