Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt

   1 * Renesas RZ Clock Pulse Generator (CPG)
   2
   3 The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
   4 CPU and GPU clocks, and several fixed ratio dividers.
   5 The CPG also provides a Clock Domain for SoC devices, in combination with the
   6 CPG Module Stop (MSTP) Clocks.
   7
   8 Required Properties:
   9
  10   - compatible: Must be one of
  11     - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
  12     and "renesas,rz-cpg-clocks" as a fallback.
  13   - reg: Base address and length of the memory resource used by the CPG
  14   - clocks: References to possible parent clocks. Order must match clock modes
  15     in the datasheet. For the r7s72100, this is extal, usb_x1.
  16   - #clock-cells: Must be 1
  17   - clock-output-names: The names of the clocks. Supported clocks are "pll",
  18     "i", and "g"
  19   - #power-domain-cells: Must be 0
  20
  21 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
  22 through an MSTP clock should refer to the CPG device node in their
  23 "power-domains" property, as documented by the generic PM domain bindings in
  24 Documentation/devicetree/bindings/power/power_domain.txt.
  25
  26
  27 Examples
  28 --------
  29
  30   - CPG device node:
  31
  32         cpg_clocks: cpg_clocks@fcfe0000 {
  33                 #clock-cells = <1>;
  34                 compatible = "renesas,r7s72100-cpg-clocks",
  35                              "renesas,rz-cpg-clocks";
  36                 reg = <0xfcfe0000 0x18>;
  37                 clocks = <&extal_clk>, <&usb_x1_clk>;
  38                 clock-output-names = "pll", "i", "g";
  39                 #power-domain-cells = <0>;
  40         };
  41
  42
  43   - CPG/MSTP Clock Domain member device node:
  44
  45         mtu2: timer@fcff0000 {
  46                 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
  47                 reg = <0xfcff0000 0x400>;
  48                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-names = "tgi0a";
  50                 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
  51                 clock-names = "fck";
  52                 power-domains = <&cpg_clocks>;
  53                 status = "disabled";
  54         };