Documentation/devicetree/bindings/clock/sunxi.txt

   1 Device Tree Clock bindings for arch-sunxi
   2
   3 This binding uses the common clock binding[1].
   4
   5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
   6
   7 Required properties:
   8 - compatible : shall be one of the following:
   9         "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
  10         "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
  11         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
  12         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
  13         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
  14         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
  15         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
  16         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
  17         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
  18         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
  19         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
  20         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  21         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
  22         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
  23         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
  24         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
  25         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
  26         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
  27         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
  28         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
  29         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
  30         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
  31         "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
  32         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
  33         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
  34         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
  35         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
  36         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
  37         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  38         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  39         "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
  40         "allwinner,sun7i-a20-out-clk" - for the external output clocks
  41         "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
  42         "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
  43         "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
  44         "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
  45
  46 Required properties for all clocks:
  47 - reg : shall be the control register address for the clock.
  48 - clocks : shall be the input parent clock(s) phandle for the clock. For
  49         multiplexed clocks, the list order must match the hardware
  50         programming order.
  51 - #clock-cells : from common clock binding; shall be set to 0 except for
  52         "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
  53         "allwinner,sun4i-pll6-clk" where it shall be set to 1
  54 - clock-output-names : shall be the corresponding names of the outputs.
  55         If the clock module only has one output, the name shall be the
  56         module name.
  57
  58 And "allwinner,*-usb-clk" clocks also require:
  59 - reset-cells : shall be set to 1
  60
  61 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
  62 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
  63
  64 Clock consumers should specify the desired clocks they use with a
  65 "clocks" phandle cell. Consumers that are using a gated clock should
  66 provide an additional ID in their clock property. This ID is the
  67 offset of the bit controlling this particular gate in the register.
  68
  69 For example:
  70
  71 osc24M: clk@01c20050 {
  72         #clock-cells = <0>;
  73         compatible = "allwinner,sun4i-a10-osc-clk";
  74         reg = <0x01c20050 0x4>;
  75         clocks = <&osc24M_fixed>;
  76         clock-output-names = "osc24M";
  77 };
  78
  79 pll1: clk@01c20000 {
  80         #clock-cells = <0>;
  81         compatible = "allwinner,sun4i-a10-pll1-clk";
  82         reg = <0x01c20000 0x4>;
  83         clocks = <&osc24M>;
  84         clock-output-names = "pll1";
  85 };
  86
  87 pll5: clk@01c20020 {
  88         #clock-cells = <1>;
  89         compatible = "allwinner,sun4i-pll5-clk";
  90         reg = <0x01c20020 0x4>;
  91         clocks = <&osc24M>;
  92         clock-output-names = "pll5_ddr", "pll5_other";
  93 };
  94
  95 cpu: cpu@01c20054 {
  96         #clock-cells = <0>;
  97         compatible = "allwinner,sun4i-a10-cpu-clk";
  98         reg = <0x01c20054 0x4>;
  99         clocks = <&osc32k>, <&osc24M>, <&pll1>;
 100         clock-output-names = "cpu";
 101 };
 102
 103 mmc0_clk: clk@01c20088 {
 104         #clock-cells = <0>;
 105         compatible = "allwinner,sun4i-mod0-clk";
 106         reg = <0x01c20088 0x4>;
 107         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 108         clock-output-names = "mmc0";
 109 };
 110
 111 mii_phy_tx_clk: clk@2 {
 112         #clock-cells = <0>;
 113         compatible = "fixed-clock";
 114         clock-frequency = <25000000>;
 115         clock-output-names = "mii_phy_tx";
 116 };
 117
 118 gmac_int_tx_clk: clk@3 {
 119         #clock-cells = <0>;
 120         compatible = "fixed-clock";
 121         clock-frequency = <125000000>;
 122         clock-output-names = "gmac_int_tx";
 123 };
 124
 125 gmac_clk: clk@01c20164 {
 126         #clock-cells = <0>;
 127         compatible = "allwinner,sun7i-a20-gmac-clk";
 128         reg = <0x01c20164 0x4>;
 129         /*
 130          * The first clock must be fixed at 25MHz;
 131          * the second clock must be fixed at 125MHz
 132          */
 133         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 134         clock-output-names = "gmac";
 135 };