1 Qualcomm adreno/snapdragon hdmi output
4 - compatible: one of the following
7 - reg: Physical base address and length of the controller's registers
8 - reg-names: "core_physical"
9 - interrupts: The interrupt signal from the hdmi block.
10 - clocks: device clocks
11 See ../clocks/clock-bindings.txt for details.
12 - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
13 - qcom,hdmi-tx-ddc-data-gpio: ddc data pin
14 - qcom,hdmi-tx-hpd-gpio: hpd pin
15 - core-vdda-supply: phandle to supply regulator
16 - hdmi-mux-supply: phandle to mux regulator
19 - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
20 - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
27 hdmi: qcom,hdmi-tx-8960@4a00000 {
28 compatible = "qcom,hdmi-tx-8960";
29 reg-names = "core_physical";
30 reg = <0x04a00000 0x1000>;
31 interrupts = <GIC_SPI 79 0>;
38 <&mmcc HDMI_M_AHB_CLK>,
39 <&mmcc HDMI_S_AHB_CLK>;
40 qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
41 qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
42 qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
43 core-vdda-supply = <&pm8921_hdmi_mvs>;
44 hdmi-mux-supply = <&ext_3p3v>;