Documentation/devicetree/bindings/hsi/omap-ssi.txt

   1 OMAP SSI controller bindings
   2
   3 OMAP Synchronous Serial Interface (SSI) controller implements a legacy
   4 variant of MIPI's High Speed Synchronous Serial Interface (HSI).
   5
   6 Required properties:
   7 - compatible:           Should include "ti,omap3-ssi".
   8 - reg-names:            Contains the values "sys" and "gdd" (in this order).
   9 - reg:                  Contains a matching register specifier for each entry
  10                         in reg-names.
  11 - interrupt-names:      Contains the value "gdd_mpu".
  12 - interrupts:           Contains matching interrupt information for each entry
  13                         in interrupt-names.
  14 - ranges:               Represents the bus address mapping between the main
  15                         controller node and the child nodes below.
  16 - clock-names:          Must include the following entries:
  17   "ssi_ssr_fck": The OMAP clock of that name
  18   "ssi_sst_fck": The OMAP clock of that name
  19   "ssi_ick": The OMAP clock of that name
  20 - clocks:               Contains a matching clock specifier for each entry in
  21                         clock-names.
  22 - #address-cells:       Should be set to <1>
  23 - #size-cells:          Should be set to <1>
  24
  25 Each port is represented as a sub-node of the ti,omap3-ssi device.
  26
  27 Required Port sub-node properties:
  28 - compatible:           Should be set to the following value
  29                         ti,omap3-ssi-port (applicable to OMAP34xx devices)
  30 - reg-names:            Contains the values "tx" and "rx" (in this order).
  31 - reg:                  Contains a matching register specifier for each entry
  32                         in reg-names.
  33 - interrupt-parent      Should be a phandle for the interrupt controller
  34 - interrupts:           Should contain interrupt specifiers for mpu interrupts
  35                         0 and 1 (in this order).
  36 - ti,ssi-cawake-gpio:   Defines which GPIO pin is used to signify CAWAKE
  37                         events for the port. This is an optional board-specific
  38                         property. If it's missing the port will not be
  39                         enabled.
  40
  41 Example for Nokia N900:
  42
  43 ssi-controller@48058000 {
  44         compatible = "ti,omap3-ssi";
  45
  46         /* needed until hwmod is updated to use the compatible string */
  47         ti,hwmods = "ssi";
  48
  49         reg = <0x48058000 0x1000>,
  50               <0x48059000 0x1000>;
  51         reg-names = "sys",
  52                     "gdd";
  53
  54         interrupts = <55>;
  55         interrupt-names = "gdd_mpu";
  56
  57         clocks = <&ssi_ssr_fck>,
  58                  <&ssi_sst_fck>,
  59                  <&ssi_ick>;
  60         clock-names = "ssi_ssr_fck",
  61                       "ssi_sst_fck",
  62                       "ssi_ick";
  63
  64         #address-cells = <1>;
  65         #size-cells = <1>;
  66         ranges;
  67
  68         ssi-port@4805a000 {
  69                 compatible = "ti,omap3-ssi-port";
  70
  71                 reg = <0x4805a000 0x800>,
  72                       <0x4805a800 0x800>;
  73                 reg-names = "tx",
  74                             "rx";
  75
  76                 interrupt-parent = <&intc>;
  77                 interrupts = <67>,
  78                              <68>;
  79
  80                 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
  81         }
  82
  83         ssi-port@4805a000 {
  84                 compatible = "ti,omap3-ssi-port";
  85
  86                 reg = <0x4805b000 0x800>,
  87                       <0x4805b800 0x800>;
  88                 reg-names = "tx",
  89                             "rx";
  90
  91                 interrupt-parent = <&intc>;
  92                 interrupts = <69>,
  93                              <70>;
  94
  95                 status = "disabled"; /* second port is not used on N900 */
  96         }
  97 }