Documentation/devicetree/bindings/iommu/arm,smmu.txt

   1 * ARM System MMU Architecture Implementation
   2
   3 ARM SoCs may contain an implementation of the ARM System Memory
   4 Management Unit Architecture, which can be used to provide 1 or 2 stages
   5 of address translation to bus masters external to the CPU.
   6
   7 The SMMU may also raise interrupts in response to various fault
   8 conditions.
   9
  10 ** System MMU required properties:
  11
  12 - compatible    : Should be one of:
  13
  14                         "arm,smmu-v1"
  15                         "arm,smmu-v2"
  16                         "arm,mmu-400"
  17                         "arm,mmu-401"
  18                         "arm,mmu-500"
  19                         "cavium,smmu-v2"
  20
  21                   depending on the particular implementation and/or the
  22                   version of the architecture implemented.
  23
  24 - reg           : Base address and size of the SMMU.
  25
  26 - #global-interrupts : The number of global interrupts exposed by the
  27                        device.
  28
  29 - interrupts    : Interrupt list, with the first #global-irqs entries
  30                   corresponding to the global interrupts and any
  31                   following entries corresponding to context interrupts,
  32                   specified in order of their indexing by the SMMU.
  33
  34                   For SMMUv2 implementations, there must be exactly one
  35                   interrupt per context bank. In the case of a single,
  36                   combined interrupt, it must be listed multiple times.
  37
  38 - mmu-masters   : A list of phandles to device nodes representing bus
  39                   masters for which the SMMU can provide a translation
  40                   and their corresponding StreamIDs (see example below).
  41                   Each device node linked from this list must have a
  42                   "#stream-id-cells" property, indicating the number of
  43                   StreamIDs associated with it.
  44
  45 ** System MMU optional properties:
  46
  47 - dma-coherent  : Present if page table walks made by the SMMU are
  48                   cache coherent with the CPU.
  49
  50                   NOTE: this only applies to the SMMU itself, not
  51                   masters connected upstream of the SMMU.
  52
  53 - calxeda,smmu-secure-config-access : Enable proper handling of buggy
  54                   implementations that always use secure access to
  55                   SMMU configuration registers. In this case non-secure
  56                   aliases of secure registers have to be used during
  57                   SMMU configuration.
  58
  59 Example:
  60
  61         smmu {
  62                 compatible = "arm,smmu-v1";
  63                 reg = <0xba5e0000 0x10000>;
  64                 #global-interrupts = <2>;
  65                 interrupts = <0 32 4>,
  66                              <0 33 4>,
  67                              <0 34 4>, /* This is the first context interrupt */
  68                              <0 35 4>,
  69                              <0 36 4>,
  70                              <0 37 4>;
  71
  72                 /*
  73                  * Two DMA controllers, the first with two StreamIDs (0xd01d
  74                  * and 0xd01e) and the second with only one (0xd11c).
  75                  */
  76                 mmu-masters = <&dma0 0xd01d 0xd01e>,
  77                               <&dma1 0xd11c>;
  78         };