Documentation/devicetree/bindings/marvell.txt

   1 Marvell Discovery mv64[345]6x System Controller chips
   2 ===========================================================
   3
   4 The Marvell mv64[345]60 series of system controller chips contain
   5 many of the peripherals needed to implement a complete computer
   6 system.  In this section, we define device tree nodes to describe
   7 the system controller chip itself and each of the peripherals
   8 which it contains.  Compatible string values for each node are
   9 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
  10
  11 1) The /system-controller node
  12
  13   This node is used to represent the system-controller and must be
  14   present when the system uses a system controller chip. The top-level
  15   system-controller node contains information that is global to all
  16   devices within the system controller chip. The node name begins
  17   with "system-controller" followed by the unit address, which is
  18   the base address of the memory-mapped register set for the system
  19   controller chip.
  20
  21   Required properties:
  22
  23     - ranges : Describes the translation of system controller addresses
  24       for memory mapped registers.
  25     - clock-frequency: Contains the main clock frequency for the system
  26       controller chip.
  27     - reg : This property defines the address and size of the
  28       memory-mapped registers contained within the system controller
  29       chip.  The address specified in the "reg" property should match
  30       the unit address of the system-controller node.
  31     - #address-cells : Address representation for system controller
  32       devices.  This field represents the number of cells needed to
  33       represent the address of the memory-mapped registers of devices
  34       within the system controller chip.
  35     - #size-cells : Size representation for the memory-mapped
  36       registers within the system controller chip.
  37     - #interrupt-cells : Defines the width of cells used to represent
  38       interrupts.
  39
  40   Optional properties:
  41
  42     - model : The specific model of the system controller chip.  Such
  43       as, "mv64360", "mv64460", or "mv64560".
  44     - compatible : A string identifying the compatibility identifiers
  45       of the system controller chip.
  46
  47   The system-controller node contains child nodes for each system
  48   controller device that the platform uses.  Nodes should not be created
  49   for devices which exist on the system controller chip but are not used
  50
  51   Example Marvell Discovery mv64360 system-controller node:
  52
  53     system-controller@f1000000 { /* Marvell Discovery mv64360 */
  54             #address-cells = <1>;
  55             #size-cells = <1>;
  56             model = "mv64360";                      /* Default */
  57             compatible = "marvell,mv64360";
  58             clock-frequency = <133333333>;
  59             reg = <0xf1000000 0x10000>;
  60             virtual-reg = <0xf1000000>;
  61             ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
  62                     0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
  63                     0xa0000000 0xa0000000 0x4000000 /* User FLASH */
  64                     0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
  65                     0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
  66
  67             [ child node definitions... ]
  68     }
  69
  70 2) Child nodes of /system-controller
  71
  72    a) Marvell Discovery MDIO bus
  73
  74    The MDIO is a bus to which the PHY devices are connected.  For each
  75    device that exists on this bus, a child node should be created.  See
  76    the definition of the PHY node below for an example of how to define
  77    a PHY.
  78
  79    Required properties:
  80      - #address-cells : Should be <1>
  81      - #size-cells : Should be <0>
  82      - device_type : Should be "mdio"
  83      - compatible : Should be "marvell,mv64360-mdio"
  84
  85    Example:
  86
  87      mdio {
  88              #address-cells = <1>;
  89              #size-cells = <0>;
  90              device_type = "mdio";
  91              compatible = "marvell,mv64360-mdio";
  92
  93              ethernet-phy@0 {
  94                      ......
  95              };
  96      };
  97
  98
  99    b) Marvell Discovery ethernet controller
 100
 101    The Discover ethernet controller is described with two levels
 102    of nodes.  The first level describes an ethernet silicon block
 103    and the second level describes up to 3 ethernet nodes within
 104    that block.  The reason for the multiple levels is that the
 105    registers for the node are interleaved within a single set
 106    of registers.  The "ethernet-block" level describes the
 107    shared register set, and the "ethernet" nodes describe ethernet
 108    port-specific properties.
 109
 110    Ethernet block node
 111
 112    Required properties:
 113      - #address-cells : <1>
 114      - #size-cells : <0>
 115      - compatible : "marvell,mv64360-eth-block"
 116      - reg : Offset and length of the register set for this block
 117
 118    Optional properties:
 119      - clocks : Phandle to the clock control device and gate bit
 120
 121    Example Discovery Ethernet block node:
 122      ethernet-block@2000 {
 123              #address-cells = <1>;
 124              #size-cells = <0>;
 125              compatible = "marvell,mv64360-eth-block";
 126              reg = <0x2000 0x2000>;
 127              ethernet@0 {
 128                      .......
 129              };
 130      };
 131
 132    Ethernet port node
 133
 134    Required properties:
 135      - device_type : Should be "network".
 136      - compatible : Should be "marvell,mv64360-eth".
 137      - reg : Should be <0>, <1>, or <2>, according to which registers
 138        within the silicon block the device uses.
 139      - interrupts : <a> where a is the interrupt number for the port.
 140      - interrupt-parent : the phandle for the interrupt controller
 141        that services interrupts for this device.
 142      - phy : the phandle for the PHY connected to this ethernet
 143        controller.
 144      - local-mac-address : 6 bytes, MAC address
 145
 146    Example Discovery Ethernet port node:
 147      ethernet@0 {
 148              device_type = "network";
 149              compatible = "marvell,mv64360-eth";
 150              reg = <0>;
 151              interrupts = <32>;
 152              interrupt-parent = <&PIC>;
 153              phy = <&PHY0>;
 154              local-mac-address = [ 00 00 00 00 00 00 ];
 155      };
 156
 157
 158
 159    c) Marvell Discovery PHY nodes
 160
 161    Required properties:
 162      - device_type : Should be "ethernet-phy"
 163      - interrupts : <a> where a is the interrupt number for this phy.
 164      - interrupt-parent : the phandle for the interrupt controller that
 165        services interrupts for this device.
 166      - reg : The ID number for the phy, usually a small integer
 167
 168    Example Discovery PHY node:
 169      ethernet-phy@1 {
 170              device_type = "ethernet-phy";
 171              compatible = "broadcom,bcm5421";
 172              interrupts = <76>;      /* GPP 12 */
 173              interrupt-parent = <&PIC>;
 174              reg = <1>;
 175      };
 176
 177
 178    d) Marvell Discovery SDMA nodes
 179
 180    Represent DMA hardware associated with the MPSC (multiprotocol
 181    serial controllers).
 182
 183    Required properties:
 184      - compatible : "marvell,mv64360-sdma"
 185      - reg : Offset and length of the register set for this device
 186      - interrupts : <a> where a is the interrupt number for the DMA
 187        device.
 188      - interrupt-parent : the phandle for the interrupt controller
 189        that services interrupts for this device.
 190
 191    Example Discovery SDMA node:
 192      sdma@4000 {
 193              compatible = "marvell,mv64360-sdma";
 194              reg = <0x4000 0xc18>;
 195              virtual-reg = <0xf1004000>;
 196              interrupts = <36>;
 197              interrupt-parent = <&PIC>;
 198      };
 199
 200
 201    e) Marvell Discovery BRG nodes
 202
 203    Represent baud rate generator hardware associated with the MPSC
 204    (multiprotocol serial controllers).
 205
 206    Required properties:
 207      - compatible : "marvell,mv64360-brg"
 208      - reg : Offset and length of the register set for this device
 209      - clock-src : A value from 0 to 15 which selects the clock
 210        source for the baud rate generator.  This value corresponds
 211        to the CLKS value in the BRGx configuration register.  See
 212        the mv64x60 User's Manual.
 213      - clock-frequence : The frequency (in Hz) of the baud rate
 214        generator's input clock.
 215      - current-speed : The current speed setting (presumably by
 216        firmware) of the baud rate generator.
 217
 218    Example Discovery BRG node:
 219      brg@b200 {
 220              compatible = "marvell,mv64360-brg";
 221              reg = <0xb200 0x8>;
 222              clock-src = <8>;
 223              clock-frequency = <133333333>;
 224              current-speed = <9600>;
 225      };
 226
 227
 228    f) Marvell Discovery CUNIT nodes
 229
 230    Represent the Serial Communications Unit device hardware.
 231
 232    Required properties:
 233      - reg : Offset and length of the register set for this device
 234
 235    Example Discovery CUNIT node:
 236      cunit@f200 {
 237              reg = <0xf200 0x200>;
 238      };
 239
 240
 241    g) Marvell Discovery MPSCROUTING nodes
 242
 243    Represent the Discovery's MPSC routing hardware
 244
 245    Required properties:
 246      - reg : Offset and length of the register set for this device
 247
 248    Example Discovery CUNIT node:
 249      mpscrouting@b500 {
 250              reg = <0xb400 0xc>;
 251      };
 252
 253
 254    h) Marvell Discovery MPSCINTR nodes
 255
 256    Represent the Discovery's MPSC DMA interrupt hardware registers
 257    (SDMA cause and mask registers).
 258
 259    Required properties:
 260      - reg : Offset and length of the register set for this device
 261
 262    Example Discovery MPSCINTR node:
 263      mpsintr@b800 {
 264              reg = <0xb800 0x100>;
 265      };
 266
 267
 268    i) Marvell Discovery MPSC nodes
 269
 270    Represent the Discovery's MPSC (Multiprotocol Serial Controller)
 271    serial port.
 272
 273    Required properties:
 274      - device_type : "serial"
 275      - compatible : "marvell,mv64360-mpsc"
 276      - reg : Offset and length of the register set for this device
 277      - sdma : the phandle for the SDMA node used by this port
 278      - brg : the phandle for the BRG node used by this port
 279      - cunit : the phandle for the CUNIT node used by this port
 280      - mpscrouting : the phandle for the MPSCROUTING node used by this port
 281      - mpscintr : the phandle for the MPSCINTR node used by this port
 282      - cell-index : the hardware index of this cell in the MPSC core
 283      - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
 284        register
 285      - interrupts : <a> where a is the interrupt number for the MPSC.
 286      - interrupt-parent : the phandle for the interrupt controller
 287        that services interrupts for this device.
 288
 289    Example Discovery MPSCINTR node:
 290      mpsc@8000 {
 291              device_type = "serial";
 292              compatible = "marvell,mv64360-mpsc";
 293              reg = <0x8000 0x38>;
 294              virtual-reg = <0xf1008000>;
 295              sdma = <&SDMA0>;
 296              brg = <&BRG0>;
 297              cunit = <&CUNIT>;
 298              mpscrouting = <&MPSCROUTING>;
 299              mpscintr = <&MPSCINTR>;
 300              cell-index = <0>;
 301              max_idle = <40>;
 302              interrupts = <40>;
 303              interrupt-parent = <&PIC>;
 304      };
 305
 306
 307    j) Marvell Discovery Watch Dog Timer nodes
 308
 309    Represent the Discovery's watchdog timer hardware
 310
 311    Required properties:
 312      - compatible : "marvell,mv64360-wdt"
 313      - reg : Offset and length of the register set for this device
 314
 315    Example Discovery Watch Dog Timer node:
 316      wdt@b410 {
 317              compatible = "marvell,mv64360-wdt";
 318              reg = <0xb410 0x8>;
 319      };
 320
 321
 322    k) Marvell Discovery I2C nodes
 323
 324    Represent the Discovery's I2C hardware
 325
 326    Required properties:
 327      - device_type : "i2c"
 328      - compatible : "marvell,mv64360-i2c"
 329      - reg : Offset and length of the register set for this device
 330      - interrupts : <a> where a is the interrupt number for the I2C.
 331      - interrupt-parent : the phandle for the interrupt controller
 332        that services interrupts for this device.
 333
 334    Example Discovery I2C node:
 335              compatible = "marvell,mv64360-i2c";
 336              reg = <0xc000 0x20>;
 337              virtual-reg = <0xf100c000>;
 338              interrupts = <37>;
 339              interrupt-parent = <&PIC>;
 340      };
 341
 342
 343    l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
 344
 345    Represent the Discovery's PIC hardware
 346
 347    Required properties:
 348      - #interrupt-cells : <1>
 349      - #address-cells : <0>
 350      - compatible : "marvell,mv64360-pic"
 351      - reg : Offset and length of the register set for this device
 352      - interrupt-controller
 353
 354    Example Discovery PIC node:
 355      pic {
 356              #interrupt-cells = <1>;
 357              #address-cells = <0>;
 358              compatible = "marvell,mv64360-pic";
 359              reg = <0x0 0x88>;
 360              interrupt-controller;
 361      };
 362
 363
 364    m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
 365
 366    Represent the Discovery's MPP hardware
 367
 368    Required properties:
 369      - compatible : "marvell,mv64360-mpp"
 370      - reg : Offset and length of the register set for this device
 371
 372    Example Discovery MPP node:
 373      mpp@f000 {
 374              compatible = "marvell,mv64360-mpp";
 375              reg = <0xf000 0x10>;
 376      };
 377
 378
 379    n) Marvell Discovery GPP (General Purpose Pins) nodes
 380
 381    Represent the Discovery's GPP hardware
 382
 383    Required properties:
 384      - compatible : "marvell,mv64360-gpp"
 385      - reg : Offset and length of the register set for this device
 386
 387    Example Discovery GPP node:
 388      gpp@f000 {
 389              compatible = "marvell,mv64360-gpp";
 390              reg = <0xf100 0x20>;
 391      };
 392
 393
 394    o) Marvell Discovery PCI host bridge node
 395
 396    Represents the Discovery's PCI host bridge device.  The properties
 397    for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
 398    1275-1994.  A typical value for the compatible property is
 399    "marvell,mv64360-pci".
 400
 401    Example Discovery PCI host bridge node
 402      pci@80000000 {
 403              #address-cells = <3>;
 404              #size-cells = <2>;
 405              #interrupt-cells = <1>;
 406              device_type = "pci";
 407              compatible = "marvell,mv64360-pci";
 408              reg = <0xcf8 0x8>;
 409              ranges = <0x01000000 0x0        0x0
 410                              0x88000000 0x0 0x01000000
 411                        0x02000000 0x0 0x80000000
 412                              0x80000000 0x0 0x08000000>;
 413              bus-range = <0 255>;
 414              clock-frequency = <66000000>;
 415              interrupt-parent = <&PIC>;
 416              interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 417              interrupt-map = <
 418                      /* IDSEL 0x0a */
 419                      0x5000 0 0 1 &PIC 80
 420                      0x5000 0 0 2 &PIC 81
 421                      0x5000 0 0 3 &PIC 91
 422                      0x5000 0 0 4 &PIC 93
 423
 424                      /* IDSEL 0x0b */
 425                      0x5800 0 0 1 &PIC 91
 426                      0x5800 0 0 2 &PIC 93
 427                      0x5800 0 0 3 &PIC 80
 428                      0x5800 0 0 4 &PIC 81
 429
 430                      /* IDSEL 0x0c */
 431                      0x6000 0 0 1 &PIC 91
 432                      0x6000 0 0 2 &PIC 93
 433                      0x6000 0 0 3 &PIC 80
 434                      0x6000 0 0 4 &PIC 81
 435
 436                      /* IDSEL 0x0d */
 437                      0x6800 0 0 1 &PIC 93
 438                      0x6800 0 0 2 &PIC 80
 439                      0x6800 0 0 3 &PIC 81
 440                      0x6800 0 0 4 &PIC 91
 441              >;
 442      };
 443
 444
 445    p) Marvell Discovery CPU Error nodes
 446
 447    Represent the Discovery's CPU error handler device.
 448
 449    Required properties:
 450      - compatible : "marvell,mv64360-cpu-error"
 451      - reg : Offset and length of the register set for this device
 452      - interrupts : the interrupt number for this device
 453      - interrupt-parent : the phandle for the interrupt controller
 454        that services interrupts for this device.
 455
 456    Example Discovery CPU Error node:
 457      cpu-error@0070 {
 458              compatible = "marvell,mv64360-cpu-error";
 459              reg = <0x70 0x10 0x128 0x28>;
 460              interrupts = <3>;
 461              interrupt-parent = <&PIC>;
 462      };
 463
 464
 465    q) Marvell Discovery SRAM Controller nodes
 466
 467    Represent the Discovery's SRAM controller device.
 468
 469    Required properties:
 470      - compatible : "marvell,mv64360-sram-ctrl"
 471      - reg : Offset and length of the register set for this device
 472      - interrupts : the interrupt number for this device
 473      - interrupt-parent : the phandle for the interrupt controller
 474        that services interrupts for this device.
 475
 476    Example Discovery SRAM Controller node:
 477      sram-ctrl@0380 {
 478              compatible = "marvell,mv64360-sram-ctrl";
 479              reg = <0x380 0x80>;
 480              interrupts = <13>;
 481              interrupt-parent = <&PIC>;
 482      };
 483
 484
 485    r) Marvell Discovery PCI Error Handler nodes
 486
 487    Represent the Discovery's PCI error handler device.
 488
 489    Required properties:
 490      - compatible : "marvell,mv64360-pci-error"
 491      - reg : Offset and length of the register set for this device
 492      - interrupts : the interrupt number for this device
 493      - interrupt-parent : the phandle for the interrupt controller
 494        that services interrupts for this device.
 495
 496    Example Discovery PCI Error Handler node:
 497      pci-error@1d40 {
 498              compatible = "marvell,mv64360-pci-error";
 499              reg = <0x1d40 0x40 0xc28 0x4>;
 500              interrupts = <12>;
 501              interrupt-parent = <&PIC>;
 502      };
 503
 504
 505    s) Marvell Discovery Memory Controller nodes
 506
 507    Represent the Discovery's memory controller device.
 508
 509    Required properties:
 510      - compatible : "marvell,mv64360-mem-ctrl"
 511      - reg : Offset and length of the register set for this device
 512      - interrupts : the interrupt number for this device
 513      - interrupt-parent : the phandle for the interrupt controller
 514        that services interrupts for this device.
 515
 516    Example Discovery Memory Controller node:
 517      mem-ctrl@1400 {
 518              compatible = "marvell,mv64360-mem-ctrl";
 519              reg = <0x1400 0x60>;
 520              interrupts = <17>;
 521              interrupt-parent = <&PIC>;
 522      };
 523
 524