Documentation/devicetree/bindings/media/video-interfaces.txt

   1 Common bindings for video receiver and transmitter interfaces
   2
   3 General concept
   4 ---------------
   5
   6 Video data pipelines usually consist of external devices, e.g. camera sensors,
   7 controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
   8 video DMA engines and video data processors.
   9
  10 SoC internal blocks are described by DT nodes, placed similarly to other SoC
  11 blocks.  External devices are represented as child nodes of their respective
  12 bus controller nodes, e.g. I2C.
  13
  14 Data interfaces on all video devices are described by their child 'port' nodes.
  15 Configuration of a port depends on other devices participating in the data
  16 transfer and is described by 'endpoint' subnodes.
  17
  18 device {
  19         ...
  20         ports {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 port@0 {
  25                         ...
  26                         endpoint@0 { ... };
  27                         endpoint@1 { ... };
  28                 };
  29                 port@1 { ... };
  30         };
  31 };
  32
  33 If a port can be configured to work with more than one remote device on the same
  34 bus, an 'endpoint' child node must be provided for each of them.  If more than
  35 one port is present in a device node or there is more than one endpoint at a
  36 port, or port node needs to be associated with a selected hardware interface,
  37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
  38 used.
  39
  40 All 'port' nodes can be grouped under optional 'ports' node, which allows to
  41 specify #address-cells, #size-cells properties independently for the 'port'
  42 and 'endpoint' nodes and any child device nodes a device might have.
  43
  44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
  45 phandles.  An endpoint subnode of a device contains all properties needed for
  46 configuration of this device for data exchange with other device.  In most
  47 cases properties at the peer 'endpoint' nodes will be identical, however they
  48 might need to be different when there is any signal modifications on the bus
  49 between two devices, e.g. there are logic signal inverters on the lines.
  50
  51 It is allowed for multiple endpoints at a port to be active simultaneously,
  52 where supported by a device.  For example, in case where a data interface of
  53 a device is partitioned into multiple data busses, e.g. 16-bit input port
  54 divided into two separate ITU-R BT.656 8-bit busses.  In such case bus-width
  55 and data-shift properties can be used to assign physical data lines to each
  56 endpoint node (logical bus).
  57
  58
  59 Required properties
  60 -------------------
  61
  62 If there is more than one 'port' or more than one 'endpoint' node or 'reg'
  63 property is present in port and/or endpoint nodes the following properties
  64 are required in a relevant parent node:
  65
  66  - #address-cells : number of cells required to define port/endpoint
  67                     identifier, should be 1.
  68  - #size-cells    : should be zero.
  69
  70 Optional endpoint properties
  71 ----------------------------
  72
  73 - remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
  74 - slave-mode: a boolean property indicating that the link is run in slave mode.
  75   The default when this property is not specified is master mode. In the slave
  76   mode horizontal and vertical synchronization signals are provided to the
  77   slave device (data source) by the master device (data sink). In the master
  78   mode the data source device is also the source of the synchronization signals.
  79 - bus-width: number of data lines actively used, valid for the parallel busses.
  80 - data-shift: on the parallel data busses, if bus-width is used to specify the
  81   number of data lines, data-shift can be used to specify which data lines are
  82   used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
  83 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
  84 - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
  85   Note, that if HSYNC and VSYNC polarities are not specified, embedded
  86   synchronization may be required, where supported.
  87 - data-active: similar to HSYNC and VSYNC, specifies data line polarity.
  88 - field-even-active: field signal level during the even field data transmission.
  89 - pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
  90   signal.
  91 - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for
  92   LOW/HIGH respectively.
  93 - data-lanes: an array of physical data lane indexes. Position of an entry
  94   determines the logical lane number, while the value of an entry indicates
  95   physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
  96   "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
  97   This property is valid for serial busses only (e.g. MIPI CSI-2).
  98 - clock-lanes: an array of physical clock lane indexes. Position of an entry
  99   determines the logical lane number, while the value of an entry indicates
 100   physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
 101   which places the clock lane on hardware lane 0. This property is valid for
 102   serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this
 103   array contains only one entry.
 104 - clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous
 105   clock mode.
 106 - link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for
 107   instance, this is the actual frequency of the bus, not bits per clock per
 108   lane value. An array of 64-bit unsigned integers.
 109
 110
 111 Example
 112 -------
 113
 114 The example snippet below describes two data pipelines.  ov772x and imx074 are
 115 camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively.
 116 Both sensors are on the I2C control bus corresponding to the i2c0 controller
 117 node.  ov772x sensor is linked directly to the ceu0 video host interface.
 118 imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a
 119 (single) DMA engine writing captured data to memory.  ceu0 node has a single
 120 'port' node which may indicate that at any time only one of the following data
 121 pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
 122
 123         ceu0: ceu@0xfe910000 {
 124                 compatible = "renesas,sh-mobile-ceu";
 125                 reg = <0xfe910000 0xa0>;
 126                 interrupts = <0x880>;
 127
 128                 mclk: master_clock {
 129                         compatible = "renesas,ceu-clock";
 130                         #clock-cells = <1>;
 131                         clock-frequency = <50000000>;   /* Max clock frequency */
 132                         clock-output-names = "mclk";
 133                 };
 134
 135                 port {
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138
 139                         /* Parallel bus endpoint */
 140                         ceu0_1: endpoint@1 {
 141                                 reg = <1>;              /* Local endpoint # */
 142                                 remote = <&ov772x_1_1>; /* Remote phandle */
 143                                 bus-width = <8>;        /* Used data lines */
 144                                 data-shift = <2>;       /* Lines 9:2 are used */
 145
 146                                 /* If hsync-active/vsync-active are missing,
 147                                    embedded BT.656 sync is used */
 148                                 hsync-active = <0>;     /* Active low */
 149                                 vsync-active = <0>;     /* Active low */
 150                                 data-active = <1>;      /* Active high */
 151                                 pclk-sample = <1>;      /* Rising */
 152                         };
 153
 154                         /* MIPI CSI-2 bus endpoint */
 155                         ceu0_0: endpoint@0 {
 156                                 reg = <0>;
 157                                 remote = <&csi2_2>;
 158                         };
 159                 };
 160         };
 161
 162         i2c0: i2c@0xfff20000 {
 163                 ...
 164                 ov772x_1: camera@0x21 {
 165                         compatible = "omnivision,ov772x";
 166                         reg = <0x21>;
 167                         vddio-supply = <&regulator1>;
 168                         vddcore-supply = <&regulator2>;
 169
 170                         clock-frequency = <20000000>;
 171                         clocks = <&mclk 0>;
 172                         clock-names = "xclk";
 173
 174                         port {
 175                                 /* With 1 endpoint per port no need for addresses. */
 176                                 ov772x_1_1: endpoint {
 177                                         bus-width = <8>;
 178                                         remote-endpoint = <&ceu0_1>;
 179                                         hsync-active = <1>;
 180                                         vsync-active = <0>; /* Who came up with an
 181                                                                inverter here ?... */
 182                                         data-active = <1>;
 183                                         pclk-sample = <1>;
 184                                 };
 185                         };
 186                 };
 187
 188                 imx074: camera@0x1a {
 189                         compatible = "sony,imx074";
 190                         reg = <0x1a>;
 191                         vddio-supply = <&regulator1>;
 192                         vddcore-supply = <&regulator2>;
 193
 194                         clock-frequency = <30000000>;   /* Shared clock with ov772x_1 */
 195                         clocks = <&mclk 0>;
 196                         clock-names = "sysclk";         /* Assuming this is the
 197                                                            name in the datasheet */
 198                         port {
 199                                 imx074_1: endpoint {
 200                                         clock-lanes = <0>;
 201                                         data-lanes = <1 2>;
 202                                         remote-endpoint = <&csi2_1>;
 203                                 };
 204                         };
 205                 };
 206         };
 207
 208         csi2: csi2@0xffc90000 {
 209                 compatible = "renesas,sh-mobile-csi2";
 210                 reg = <0xffc90000 0x1000>;
 211                 interrupts = <0x17a0>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214
 215                 port@1 {
 216                         compatible = "renesas,csi2c";   /* One of CSI2I and CSI2C. */
 217                         reg = <1>;                      /* CSI-2 PHY #1 of 2: PHY_S,
 218                                                            PHY_M has port address 0,
 219                                                            is unused. */
 220                         csi2_1: endpoint {
 221                                 clock-lanes = <0>;
 222                                 data-lanes = <2 1>;
 223                                 remote-endpoint = <&imx074_1>;
 224                         };
 225                 };
 226                 port@2 {
 227                         reg = <2>;                      /* port 2: link to the CEU */
 228
 229                         csi2_2: endpoint {
 230                                 remote-endpoint = <&ceu0_0>;
 231                         };
 232                 };
 233         };