Documentation/devicetree/bindings/net/amd-xgbe.txt

   1 * AMD 10GbE driver (amd-xgbe)
   2
   3 Required properties (ethernet device):
   4 - compatible: Should be "amd,xgbe-seattle-v1a"
   5 - reg: Address and length of the register sets for the device
   6    - MAC registers
   7    - PCS registers
   8 - interrupt-parent: Should be the phandle for the interrupt controller
   9   that services interrupts for this device
  10 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
  11   listed is required and is the general device interrupt. If the optional
  12   amd,per-channel-interrupt property is specified, then one additional
  13   interrupt for each DMA channel supported by the device should be specified
  14 - clocks:
  15    - DMA clock for the amd-xgbe device (used for calculating the
  16      correct Rx interrupt watchdog timer value on a DMA channel
  17      for coalescing)
  18    - PTP clock for the amd-xgbe device
  19 - clock-names: Should be the names of the clocks
  20    - "dma_clk" for the DMA clock
  21    - "ptp_clk" for the PTP clock
  22 - phy-handle: See ethernet.txt file in the same directory
  23 - phy-mode: See ethernet.txt file in the same directory
  24
  25 Optional properties (ethernet device):
  26 - mac-address: mac address to be assigned to the device. Can be overridden
  27   by UEFI.
  28 - dma-coherent: Present if dma operations are coherent
  29 - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
  30   a unique interrupt for each DMA channel - this requires an additional
  31   interrupt be configured for each DMA channel
  32
  33 Required properties (phy device):
  34 - compatible: Should be "amd,xgbe-phy-seattle-v1a"
  35 - reg: Address and length of the register sets for the device
  36    - SerDes Rx/Tx registers
  37    - SerDes integration registers (1/2)
  38    - SerDes integration registers (2/2)
  39 - interrupt-parent: Should be the phandle for the interrupt controller
  40   that services interrupts for this device
  41 - interrupts: Should contain the amd-xgbe-phy interrupt.
  42
  43 Optional properties (phy device):
  44 - amd,speed-set: Speed capabilities of the device
  45     0 - 1GbE and 10GbE (default)
  46     1 - 2.5GbE and 10GbE
  47
  48 The following optional properties are represented by an array with each
  49 value corresponding to a particular speed. The first array value represents
  50 the setting for the 1GbE speed, the second value for the 2.5GbE speed and
  51 the third value for the 10GbE speed.  All three values are required if the
  52 property is used.
  53 - amd,serdes-blwc: Baseline wandering correction enablement
  54     0 - Off
  55     1 - On
  56 - amd,serdes-cdr-rate: CDR rate speed selection
  57 - amd,serdes-pq-skew: PQ (data sampling) skew
  58 - amd,serdes-tx-amp: TX amplitude boost
  59 - amd,serdes-dfe-tap-config: DFE taps available to run
  60 - amd,serdes-dfe-tap-enable: DFE taps to enable
  61
  62 Example:
  63         xgbe@e0700000 {
  64                 compatible = "amd,xgbe-seattle-v1a";
  65                 reg = <0 0xe0700000 0 0x80000>,
  66                       <0 0xe0780000 0 0x80000>;
  67                 interrupt-parent = <&gic>;
  68                 interrupts = <0 325 4>,
  69                              <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>;
  70                 amd,per-channel-interrupt;
  71                 clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
  72                 clock-names = "dma_clk", "ptp_clk";
  73                 phy-handle = <&xgbe_phy>;
  74                 phy-mode = "xgmii";
  75                 mac-address = [ 02 a1 a2 a3 a4 a5 ];
  76         };
  77
  78         xgbe_phy@e1240800 {
  79                 compatible = "amd,xgbe-phy-seattle-v1a";
  80                 reg = <0 0xe1240800 0 0x00400>,
  81                       <0 0xe1250000 0 0x00060>,
  82                       <0 0xe1250080 0 0x00004>;
  83                 interrupt-parent = <&gic>;
  84                 interrupts = <0 323 4>;
  85                 amd,speed-set = <0>;
  86                 amd,serdes-blwc = <1>, <1>, <0>;
  87                 amd,serdes-cdr-rate = <2>, <2>, <7>;
  88                 amd,serdes-pq-skew = <10>, <10>, <30>;
  89                 amd,serdes-tx-amp = <15>, <15>, <10>;
  90                 amd,serdes-dfe-tap-config = <3>, <3>, <1>;
  91                 amd,serdes-dfe-tap-enable = <0>, <0>, <127>;
  92         };