Documentation/devicetree/bindings/net/apm-xgene-enet.txt

   1 APM X-Gene SoC Ethernet nodes
   2
   3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
   4 APM X-Gene SoC.
   5
   6 Required properties for all the ethernet interfaces:
   7 - compatible: Should state binding information from the following list,
   8   - "apm,xgene-enet":    RGMII based 1G interface
   9   - "apm,xgene1-sgenet": SGMII based 1G interface
  10   - "apm,xgene1-xgenet": XFI based 10G interface
  11 - reg: Address and length of the register set for the device. It contains the
  12   information of registers in the same order as described by reg-names
  13 - reg-names: Should contain the register set names
  14   - "enet_csr": Ethernet control and status register address space
  15   - "ring_csr": Descriptor ring control and status register address space
  16   - "ring_cmd": Descriptor ring command register address space
  17 - interrupts: Two interrupt specifiers can be specified.
  18   - First is the Rx interrupt.  This irq is mandatory.
  19   - Second is the Tx completion interrupt.
  20     This is supported only on SGMII based 1GbE and 10GbE interfaces.
  21 - port-id: Port number (0 or 1)
  22 - clocks: Reference to the clock entry.
  23 - local-mac-address: MAC address assigned to this device
  24 - phy-connection-type: Interface type between ethernet device and PHY device
  25
  26 Required properties for ethernet interfaces that have external PHY:
  27 - phy-handle: Reference to a PHY node connected to this device
  28
  29 - mdio: Device tree subnode with the following required properties:
  30   - compatible: Must be "apm,xgene-mdio".
  31   - #address-cells: Must be <1>.
  32   - #size-cells: Must be <0>.
  33
  34   For the phy on the mdio bus, there must be a node with the following fields:
  35   - compatible: PHY identifier.  Please refer ./phy.txt for the format.
  36   - reg: The ID number for the phy.
  37
  38 Optional properties:
  39 - status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok".
  40 - tx-delay: Delay value for RGMII bridge TX clock.
  41             Valid values are between 0 to 7, that maps to
  42             417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps
  43             Default value is 4, which corresponds to 1611 ps
  44 - rx-delay: Delay value for RGMII bridge RX clock.
  45             Valid values are between 0 to 7, that maps to
  46             273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
  47             Default value is 2, which corresponds to 899 ps
  48
  49 Example:
  50         menetclk: menetclk {
  51                 compatible = "apm,xgene-device-clock";
  52                 clock-output-names = "menetclk";
  53                 status = "ok";
  54         };
  55
  56         menet: ethernet@17020000 {
  57                 compatible = "apm,xgene-enet";
  58                 status = "disabled";
  59                 reg = <0x0 0x17020000 0x0 0xd100>,
  60                       <0x0 0X17030000 0x0 0X400>,
  61                       <0x0 0X10000000 0x0 0X200>;
  62                 reg-names = "enet_csr", "ring_csr", "ring_cmd";
  63                 interrupts = <0x0 0x3c 0x4>;
  64                 port-id = <0>;
  65                 clocks = <&menetclk 0>;
  66                 local-mac-address = [00 01 73 00 00 01];
  67                 phy-connection-type = "rgmii";
  68                 phy-handle = <&menetphy>;
  69                 mdio {
  70                         compatible = "apm,xgene-mdio";
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         menetphy: menetphy@3 {
  74                                 compatible = "ethernet-phy-id001c.c915";
  75                                 reg = <0x3>;
  76                         };
  77
  78                 };
  79         };
  80
  81 /* Board-specific peripheral configurations */
  82 &menet {
  83         tx-delay = <4>;
  84         rx-delay = <2>;
  85         status = "ok";
  86 };