Documentation/devicetree/bindings/net/mdio-mux-gpio.txt

   1 Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
   2
   3 This is a special case of a MDIO bus multiplexer.  One or more GPIO
   4 lines are used to control which child bus is connected.
   5
   6 Required properties in addition to the generic multiplexer properties:
   7
   8 - compatible : mdio-mux-gpio.
   9 - gpios : GPIO specifiers for each GPIO line.  One or more must be specified.
  10
  11
  12 Example :
  13
  14         /* The parent MDIO bus. */
  15         smi1: mdio@1180000001900 {
  16                 compatible = "cavium,octeon-3860-mdio";
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 reg = <0x11800 0x00001900 0x0 0x40>;
  20         };
  21
  22         /*
  23            An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
  24            pair of GPIO lines.  Child busses 2 and 3 populated with 4
  25            PHYs each.
  26          */
  27         mdio-mux {
  28                 compatible = "mdio-mux-gpio";
  29                 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
  30                 mdio-parent-bus = <&smi1>;
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 mdio@2 {
  35                         reg = <2>;
  36                         #address-cells = <1>;
  37                         #size-cells = <0>;
  38
  39                         phy11: ethernet-phy@1 {
  40                                 reg = <1>;
  41                                 compatible = "marvell,88e1149r";
  42                                 marvell,reg-init = <3 0x10 0 0x5777>,
  43                                         <3 0x11 0 0x00aa>,
  44                                         <3 0x12 0 0x4105>,
  45                                         <3 0x13 0 0x0a60>;
  46                                 interrupt-parent = <&gpio>;
  47                                 interrupts = <10 8>; /* Pin 10, active low */
  48                         };
  49                         phy12: ethernet-phy@2 {
  50                                 reg = <2>;
  51                                 compatible = "marvell,88e1149r";
  52                                 marvell,reg-init = <3 0x10 0 0x5777>,
  53                                         <3 0x11 0 0x00aa>,
  54                                         <3 0x12 0 0x4105>,
  55                                         <3 0x13 0 0x0a60>;
  56                                 interrupt-parent = <&gpio>;
  57                                 interrupts = <10 8>; /* Pin 10, active low */
  58                         };
  59                         phy13: ethernet-phy@3 {
  60                                 reg = <3>;
  61                                 compatible = "marvell,88e1149r";
  62                                 marvell,reg-init = <3 0x10 0 0x5777>,
  63                                         <3 0x11 0 0x00aa>,
  64                                         <3 0x12 0 0x4105>,
  65                                         <3 0x13 0 0x0a60>;
  66                                 interrupt-parent = <&gpio>;
  67                                 interrupts = <10 8>; /* Pin 10, active low */
  68                         };
  69                         phy14: ethernet-phy@4 {
  70                                 reg = <4>;
  71                                 compatible = "marvell,88e1149r";
  72                                 marvell,reg-init = <3 0x10 0 0x5777>,
  73                                         <3 0x11 0 0x00aa>,
  74                                         <3 0x12 0 0x4105>,
  75                                         <3 0x13 0 0x0a60>;
  76                                 interrupt-parent = <&gpio>;
  77                                 interrupts = <10 8>; /* Pin 10, active low */
  78                         };
  79                 };
  80
  81                 mdio@3 {
  82                         reg = <3>;
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85
  86                         phy21: ethernet-phy@1 {
  87                                 reg = <1>;
  88                                 compatible = "marvell,88e1149r";
  89                                 marvell,reg-init = <3 0x10 0 0x5777>,
  90                                         <3 0x11 0 0x00aa>,
  91                                         <3 0x12 0 0x4105>,
  92                                         <3 0x13 0 0x0a60>;
  93                                 interrupt-parent = <&gpio>;
  94                                 interrupts = <12 8>; /* Pin 12, active low */
  95                         };
  96                         phy22: ethernet-phy@2 {
  97                                 reg = <2>;
  98                                 compatible = "marvell,88e1149r";
  99                                 marvell,reg-init = <3 0x10 0 0x5777>,
 100                                         <3 0x11 0 0x00aa>,
 101                                         <3 0x12 0 0x4105>,
 102                                         <3 0x13 0 0x0a60>;
 103                                 interrupt-parent = <&gpio>;
 104                                 interrupts = <12 8>; /* Pin 12, active low */
 105                         };
 106                         phy23: ethernet-phy@3 {
 107                                 reg = <3>;
 108                                 compatible = "marvell,88e1149r";
 109                                 marvell,reg-init = <3 0x10 0 0x5777>,
 110                                         <3 0x11 0 0x00aa>,
 111                                         <3 0x12 0 0x4105>,
 112                                         <3 0x13 0 0x0a60>;
 113                                 interrupt-parent = <&gpio>;
 114                                 interrupts = <12 8>; /* Pin 12, active low */
 115                         };
 116                         phy24: ethernet-phy@4 {
 117                                 reg = <4>;
 118                                 compatible = "marvell,88e1149r";
 119                                 marvell,reg-init = <3 0x10 0 0x5777>,
 120                                         <3 0x11 0 0x00aa>,
 121                                         <3 0x12 0 0x4105>,
 122                                         <3 0x13 0 0x0a60>;
 123                                 interrupt-parent = <&gpio>;
 124                                 interrupts = <12 8>; /* Pin 12, active low */
 125                         };
 126                 };
 127         };