Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt

   1 * Broadcom iProc PCIe controller with the platform bus interface
   2
   3 Required properties:
   4 - compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
   5   for PAXC.  PAXB-based root complex is used for external endpoint devices.
   6   PAXC-based root complex is connected to emulated endpoint devices
   7   internal to the ASIC
   8 - reg: base address and length of the PCIe controller I/O register space
   9 - #interrupt-cells: set to <1>
  10 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
  11   mapping of the PCIe interface to interrupt numbers
  12 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
  13 - bus-range: PCI bus numbers covered
  14 - #address-cells: set to <3>
  15 - #size-cells: set to <2>
  16 - device_type: set to "pci"
  17 - ranges: ranges for the PCI memory and I/O regions
  18
  19 Optional properties:
  20 - phys: phandle of the PCIe PHY device
  21 - phy-names: must be "pcie-phy"
  22
  23 - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
  24 by the ASIC after power on reset. In this case, SW needs to configure it
  25
  26 If the brcm,pcie-ob property is present, the following properties become
  27 effective:
  28
  29 Required:
  30 - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
  31 address used by the iProc PCIe core (not the PCIe address)
  32 - brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)
  33
  34 Optional:
  35 - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
  36 increase the outbound window size
  37
  38 MSI support (optional):
  39
  40 For older platforms without MSI integrated in the GIC, iProc PCIe core provides
  41 an event queue based MSI support.  The iProc MSI uses host memories to store
  42 MSI posted writes in the event queues
  43
  44 - msi-parent: Link to the device node of the MSI controller.  On newer iProc
  45 platforms, the MSI controller may be gicv2m or gicv3-its.  On older iProc
  46 platforms without MSI support in its interrupt controller, one may use the
  47 event queue based MSI support integrated within the iProc PCIe core.
  48
  49 When the iProc event queue based MSI is used, one needs to define the
  50 following properties in the MSI device node:
  51 - compatible: Must be "brcm,iproc-msi"
  52 - msi-controller: claims itself as an MSI controller
  53 - interrupt-parent: Link to its parent interrupt device
  54 - interrupts: List of interrupt IDs from its parent interrupt device
  55
  56 Optional properties:
  57 - brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
  58 require the interrupt enable registers to be set explicitly to enable MSI
  59
  60 Example:
  61         pcie0: pcie@18012000 {
  62                 compatible = "brcm,iproc-pcie";
  63                 reg = <0x18012000 0x1000>;
  64
  65                 #interrupt-cells = <1>;
  66                 interrupt-map-mask = <0 0 0 0>;
  67                 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
  68
  69                 linux,pci-domain = <0>;
  70
  71                 bus-range = <0x00 0xff>;
  72
  73                 #address-cells = <3>;
  74                 #size-cells = <2>;
  75                 device_type = "pci";
  76                 ranges = <0x81000000 0 0          0x28000000 0 0x00010000
  77                           0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
  78
  79                 phys = <&phy 0 5>;
  80                 phy-names = "pcie-phy";
  81
  82                 brcm,pcie-ob;
  83                 brcm,pcie-ob-oarr-size;
  84                 brcm,pcie-ob-axi-offset = <0x00000000>;
  85                 brcm,pcie-ob-window-size = <256>;
  86
  87                 msi-parent = <&msi0>;
  88
  89                 /* iProc event queue based MSI */
  90                 msi0: msi@18012000 {
  91                         compatible = "brcm,iproc-msi";
  92                         msi-controller;
  93                         interrupt-parent = <&gic>;
  94                         interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
  95                                      <GIC_SPI 97 IRQ_TYPE_NONE>,
  96                                      <GIC_SPI 98 IRQ_TYPE_NONE>,
  97                                      <GIC_SPI 99 IRQ_TYPE_NONE>,
  98                 };
  99         };
 100
 101         pcie1: pcie@18013000 {
 102                 compatible = "brcm,iproc-pcie";
 103                 reg = <0x18013000 0x1000>;
 104
 105                 #interrupt-cells = <1>;
 106                 interrupt-map-mask = <0 0 0 0>;
 107                 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
 108
 109                 linux,pci-domain = <1>;
 110
 111                 bus-range = <0x00 0xff>;
 112
 113                 #address-cells = <3>;
 114                 #size-cells = <2>;
 115                 device_type = "pci";
 116                 ranges = <0x81000000 0 0          0x48000000 0 0x00010000
 117                           0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
 118
 119                 phys = <&phy 1 6>;
 120                 phy-names = "pcie-phy";
 121         };