Documentation/devicetree/bindings/pci/mvebu-pci.txt

   1 * Marvell EBU PCIe interfaces
   2
   3 Mandatory properties:
   4
   5 - compatible: one of the following values:
   6     marvell,armada-370-pcie
   7     marvell,armada-xp-pcie
   8     marvell,dove-pcie
   9     marvell,kirkwood-pcie
  10 - #address-cells, set to <3>
  11 - #size-cells, set to <2>
  12 - #interrupt-cells, set to <1>
  13 - bus-range: PCI bus numbers covered
  14 - device_type, set to "pci"
  15 - ranges: ranges describing the MMIO registers to control the PCIe
  16   interfaces, and ranges describing the MBus windows needed to access
  17   the memory and I/O regions of each PCIe interface.
  18 - msi-parent: Link to the hardware entity that serves as the Message
  19   Signaled Interrupt controller for this PCI controller.
  20
  21 The ranges describing the MMIO registers have the following layout:
  22
  23     0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
  24
  25 where:
  26
  27   * r is a 32-bits value that gives the offset of the MMIO
  28   registers of this PCIe interface, from the base of the internal
  29   registers.
  30
  31   * s is a 32-bits value that give the size of this MMIO
  32   registers area. This range entry translates the '0x82000000 0 r' PCI
  33   address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
  34   of the internal register window (as identified by MBUS_ID(0xf0,
  35   0x01)).
  36
  37 The ranges describing the MBus windows have the following layout:
  38
  39     0x8t000000 s 0     MBUS_ID(w, a) 0 1 0
  40
  41 where:
  42
  43    * t is the type of the MBus window (as defined by the standard PCI DT
  44    bindings), 1 for I/O and 2 for memory.
  45
  46    * s is the PCI slot that corresponds to this PCIe interface
  47
  48    * w is the 'target ID' value for the MBus window
  49
  50    * a the 'attribute' value for the MBus window.
  51
  52 Since the location and size of the different MBus windows is not fixed in
  53 hardware, and only determined in runtime, those ranges cover the full first
  54 4 GB of the physical address space, and do not translate into a valid CPU
  55 address.
  56
  57 In addition, the device tree node must have sub-nodes describing each
  58 PCIe interface, having the following mandatory properties:
  59
  60 - reg: used only for interrupt mapping, so only the first four bytes
  61   are used to refer to the correct bus number and device number.
  62 - assigned-addresses: reference to the MMIO registers used to control
  63   this PCIe interface.
  64 - clocks: the clock associated to this PCIe interface
  65 - marvell,pcie-port: the physical PCIe port number
  66 - status: either "disabled" or "okay"
  67 - device_type, set to "pci"
  68 - #address-cells, set to <3>
  69 - #size-cells, set to <2>
  70 - #interrupt-cells, set to <1>
  71 - ranges, translating the MBus windows ranges of the parent node into
  72   standard PCI addresses.
  73 - interrupt-map-mask and interrupt-map, standard PCI properties to
  74   define the mapping of the PCIe interface to interrupt numbers.
  75
  76 and the following optional properties:
  77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
  78   multiple lanes. If this property is not found, we assume that the
  79   value is 0.
  80 - reset-gpios: optional gpio to PERST#
  81 - reset-delay-us: delay in us to wait after reset de-assertion
  82
  83 Example:
  84
  85 pcie-controller {
  86         compatible = "marvell,armada-xp-pcie";
  87         status = "disabled";
  88         device_type = "pci";
  89
  90         #address-cells = <3>;
  91         #size-cells = <2>;
  92
  93         bus-range = <0x00 0xff>;
  94         msi-parent = <&mpic>;
  95
  96         ranges =
  97                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
  98                 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
  99                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
 100                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
 101                 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
 102                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
 103                 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
 104                 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
 105                 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
 106                 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
 107                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 108                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
 109                 0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
 110                 0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
 111                 0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
 112                 0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
 113                 0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
 114                 0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 115
 116                 0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 117                 0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 118                 0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
 119                 0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
 120                 0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
 121                 0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
 122                 0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
 123                 0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
 124
 125                 0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 126                 0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
 127
 128                 0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
 129                 0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 130
 131         pcie@1,0 {
 132                 device_type = "pci";
 133                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 134                 reg = <0x0800 0 0 0 0>;
 135                 #address-cells = <3>;
 136                 #size-cells = <2>;
 137                 #interrupt-cells = <1>;
 138                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 139                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 140                 interrupt-map-mask = <0 0 0 0>;
 141                 interrupt-map = <0 0 0 0 &mpic 58>;
 142                 marvell,pcie-port = <0>;
 143                 marvell,pcie-lane = <0>;
 144                 /* low-active PERST# reset on GPIO 25 */
 145                 reset-gpios = <&gpio0 25 1>;
 146                 /* wait 20ms for device settle after reset deassertion */
 147                 reset-delay-us = <20000>;
 148                 clocks = <&gateclk 5>;
 149                 status = "disabled";
 150         };
 151
 152         pcie@2,0 {
 153                 device_type = "pci";
 154                 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 155                 reg = <0x1000 0 0 0 0>;
 156                 #address-cells = <3>;
 157                 #size-cells = <2>;
 158                 #interrupt-cells = <1>;
 159                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 160                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 161                 interrupt-map-mask = <0 0 0 0>;
 162                 interrupt-map = <0 0 0 0 &mpic 59>;
 163                 marvell,pcie-port = <0>;
 164                 marvell,pcie-lane = <1>;
 165                 clocks = <&gateclk 6>;
 166                 status = "disabled";
 167         };
 168
 169         pcie@3,0 {
 170                 device_type = "pci";
 171                 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
 172                 reg = <0x1800 0 0 0 0>;
 173                 #address-cells = <3>;
 174                 #size-cells = <2>;
 175                 #interrupt-cells = <1>;
 176                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 177                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 178                 interrupt-map-mask = <0 0 0 0>;
 179                 interrupt-map = <0 0 0 0 &mpic 60>;
 180                 marvell,pcie-port = <0>;
 181                 marvell,pcie-lane = <2>;
 182                 clocks = <&gateclk 7>;
 183                 status = "disabled";
 184         };
 185
 186         pcie@4,0 {
 187                 device_type = "pci";
 188                 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
 189                 reg = <0x2000 0 0 0 0>;
 190                 #address-cells = <3>;
 191                 #size-cells = <2>;
 192                 #interrupt-cells = <1>;
 193                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 194                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 195                 interrupt-map-mask = <0 0 0 0>;
 196                 interrupt-map = <0 0 0 0 &mpic 61>;
 197                 marvell,pcie-port = <0>;
 198                 marvell,pcie-lane = <3>;
 199                 clocks = <&gateclk 8>;
 200                 status = "disabled";
 201         };
 202
 203         pcie@5,0 {
 204                 device_type = "pci";
 205                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 206                 reg = <0x2800 0 0 0 0>;
 207                 #address-cells = <3>;
 208                 #size-cells = <2>;
 209                 #interrupt-cells = <1>;
 210                 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
 211                           0x81000000 0 0 0x81000000 0x5 0 1 0>;
 212                 interrupt-map-mask = <0 0 0 0>;
 213                 interrupt-map = <0 0 0 0 &mpic 62>;
 214                 marvell,pcie-port = <1>;
 215                 marvell,pcie-lane = <0>;
 216                 clocks = <&gateclk 9>;
 217                 status = "disabled";
 218         };
 219
 220         pcie@6,0 {
 221                 device_type = "pci";
 222                 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
 223                 reg = <0x3000 0 0 0 0>;
 224                 #address-cells = <3>;
 225                 #size-cells = <2>;
 226                 #interrupt-cells = <1>;
 227                 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
 228                           0x81000000 0 0 0x81000000 0x6 0 1 0>;
 229                 interrupt-map-mask = <0 0 0 0>;
 230                 interrupt-map = <0 0 0 0 &mpic 63>;
 231                 marvell,pcie-port = <1>;
 232                 marvell,pcie-lane = <1>;
 233                 clocks = <&gateclk 10>;
 234                 status = "disabled";
 235         };
 236
 237         pcie@7,0 {
 238                 device_type = "pci";
 239                 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
 240                 reg = <0x3800 0 0 0 0>;
 241                 #address-cells = <3>;
 242                 #size-cells = <2>;
 243                 #interrupt-cells = <1>;
 244                 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
 245                           0x81000000 0 0 0x81000000 0x7 0 1 0>;
 246                 interrupt-map-mask = <0 0 0 0>;
 247                 interrupt-map = <0 0 0 0 &mpic 64>;
 248                 marvell,pcie-port = <1>;
 249                 marvell,pcie-lane = <2>;
 250                 clocks = <&gateclk 11>;
 251                 status = "disabled";
 252         };
 253
 254         pcie@8,0 {
 255                 device_type = "pci";
 256                 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
 257                 reg = <0x4000 0 0 0 0>;
 258                 #address-cells = <3>;
 259                 #size-cells = <2>;
 260                 #interrupt-cells = <1>;
 261                 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
 262                           0x81000000 0 0 0x81000000 0x8 0 1 0>;
 263                 interrupt-map-mask = <0 0 0 0>;
 264                 interrupt-map = <0 0 0 0 &mpic 65>;
 265                 marvell,pcie-port = <1>;
 266                 marvell,pcie-lane = <3>;
 267                 clocks = <&gateclk 12>;
 268                 status = "disabled";
 269         };
 270
 271         pcie@9,0 {
 272                 device_type = "pci";
 273                 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
 274                 reg = <0x4800 0 0 0 0>;
 275                 #address-cells = <3>;
 276                 #size-cells = <2>;
 277                 #interrupt-cells = <1>;
 278                 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 279                           0x81000000 0 0 0x81000000 0x9 0 1 0>;
 280                 interrupt-map-mask = <0 0 0 0>;
 281                 interrupt-map = <0 0 0 0 &mpic 99>;
 282                 marvell,pcie-port = <2>;
 283                 marvell,pcie-lane = <0>;
 284                 clocks = <&gateclk 26>;
 285                 status = "disabled";
 286         };
 287
 288         pcie@10,0 {
 289                 device_type = "pci";
 290                 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
 291                 reg = <0x5000 0 0 0 0>;
 292                 #address-cells = <3>;
 293                 #size-cells = <2>;
 294                 #interrupt-cells = <1>;
 295                 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
 296                           0x81000000 0 0 0x81000000 0xa 0 1 0>;
 297                 interrupt-map-mask = <0 0 0 0>;
 298                 interrupt-map = <0 0 0 0 &mpic 103>;
 299                 marvell,pcie-port = <3>;
 300                 marvell,pcie-lane = <0>;
 301                 clocks = <&gateclk 27>;
 302                 status = "disabled";
 303         };
 304 };