Documentation/devicetree/bindings/pci/mvebu-pci.txt

   1 * Marvell EBU PCIe interfaces
   2
   3 Mandatory properties:
   4
   5 - compatible: one of the following values:
   6     marvell,armada-370-pcie
   7     marvell,armada-xp-pcie
   8     marvell,kirkwood-pcie
   9 - #address-cells, set to <3>
  10 - #size-cells, set to <2>
  11 - #interrupt-cells, set to <1>
  12 - bus-range: PCI bus numbers covered
  13 - device_type, set to "pci"
  14 - ranges: ranges describing the MMIO registers to control the PCIe
  15   interfaces, and ranges describing the MBus windows needed to access
  16   the memory and I/O regions of each PCIe interface.
  17
  18 The ranges describing the MMIO registers have the following layout:
  19
  20     0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
  21
  22 where:
  23
  24   * r is a 32-bits value that gives the offset of the MMIO
  25   registers of this PCIe interface, from the base of the internal
  26   registers.
  27
  28   * s is a 32-bits value that give the size of this MMIO
  29   registers area. This range entry translates the '0x82000000 0 r' PCI
  30   address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
  31   of the internal register window (as identified by MBUS_ID(0xf0,
  32   0x01)).
  33
  34 The ranges describing the MBus windows have the following layout:
  35
  36     0x8t000000 s 0     MBUS_ID(w, a) 0 1 0
  37
  38 where:
  39
  40    * t is the type of the MBus window (as defined by the standard PCI DT
  41    bindings), 1 for I/O and 2 for memory.
  42
  43    * s is the PCI slot that corresponds to this PCIe interface
  44
  45    * w is the 'target ID' value for the MBus window
  46
  47    * a the 'attribute' value for the MBus window.
  48
  49 Since the location and size of the different MBus windows is not fixed in
  50 hardware, and only determined in runtime, those ranges cover the full first
  51 4 GB of the physical address space, and do not translate into a valid CPU
  52 address.
  53
  54 In addition, the device tree node must have sub-nodes describing each
  55 PCIe interface, having the following mandatory properties:
  56
  57 - reg: used only for interrupt mapping, so only the first four bytes
  58   are used to refer to the correct bus number and device number.
  59 - assigned-addresses: reference to the MMIO registers used to control
  60   this PCIe interface.
  61 - clocks: the clock associated to this PCIe interface
  62 - marvell,pcie-port: the physical PCIe port number
  63 - status: either "disabled" or "okay"
  64 - device_type, set to "pci"
  65 - #address-cells, set to <3>
  66 - #size-cells, set to <2>
  67 - #interrupt-cells, set to <1>
  68 - ranges, translating the MBus windows ranges of the parent node into
  69   standard PCI addresses.
  70 - interrupt-map-mask and interrupt-map, standard PCI properties to
  71   define the mapping of the PCIe interface to interrupt numbers.
  72
  73 and the following optional properties:
  74 - marvell,pcie-lane: the physical PCIe lane number, for ports having
  75   multiple lanes. If this property is not found, we assume that the
  76   value is 0.
  77
  78 Example:
  79
  80 pcie-controller {
  81         compatible = "marvell,armada-xp-pcie";
  82         status = "disabled";
  83         device_type = "pci";
  84
  85         #address-cells = <3>;
  86         #size-cells = <2>;
  87
  88         bus-range = <0x00 0xff>;
  89
  90         ranges =
  91                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
  92                 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
  93                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
  94                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
  95                 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
  96                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
  97                 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
  98                 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
  99                 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
 100                 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
 101                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 102                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
 103                 0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
 104                 0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
 105                 0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
 106                 0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
 107                 0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
 108                 0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 109
 110                 0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 111                 0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 112                 0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
 113                 0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
 114                 0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
 115                 0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
 116                 0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
 117                 0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
 118
 119                 0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 120                 0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
 121
 122                 0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
 123                 0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 124
 125         pcie@1,0 {
 126                 device_type = "pci";
 127                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 128                 reg = <0x0800 0 0 0 0>;
 129                 #address-cells = <3>;
 130                 #size-cells = <2>;
 131                 #interrupt-cells = <1>;
 132                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 133                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 134                 interrupt-map-mask = <0 0 0 0>;
 135                 interrupt-map = <0 0 0 0 &mpic 58>;
 136                 marvell,pcie-port = <0>;
 137                 marvell,pcie-lane = <0>;
 138                 clocks = <&gateclk 5>;
 139                 status = "disabled";
 140         };
 141
 142         pcie@2,0 {
 143                 device_type = "pci";
 144                 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 145                 reg = <0x1000 0 0 0 0>;
 146                 #address-cells = <3>;
 147                 #size-cells = <2>;
 148                 #interrupt-cells = <1>;
 149                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 150                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 151                 interrupt-map-mask = <0 0 0 0>;
 152                 interrupt-map = <0 0 0 0 &mpic 59>;
 153                 marvell,pcie-port = <0>;
 154                 marvell,pcie-lane = <1>;
 155                 clocks = <&gateclk 6>;
 156                 status = "disabled";
 157         };
 158
 159         pcie@3,0 {
 160                 device_type = "pci";
 161                 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
 162                 reg = <0x1800 0 0 0 0>;
 163                 #address-cells = <3>;
 164                 #size-cells = <2>;
 165                 #interrupt-cells = <1>;
 166                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 167                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 168                 interrupt-map-mask = <0 0 0 0>;
 169                 interrupt-map = <0 0 0 0 &mpic 60>;
 170                 marvell,pcie-port = <0>;
 171                 marvell,pcie-lane = <2>;
 172                 clocks = <&gateclk 7>;
 173                 status = "disabled";
 174         };
 175
 176         pcie@4,0 {
 177                 device_type = "pci";
 178                 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
 179                 reg = <0x2000 0 0 0 0>;
 180                 #address-cells = <3>;
 181                 #size-cells = <2>;
 182                 #interrupt-cells = <1>;
 183                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 184                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 185                 interrupt-map-mask = <0 0 0 0>;
 186                 interrupt-map = <0 0 0 0 &mpic 61>;
 187                 marvell,pcie-port = <0>;
 188                 marvell,pcie-lane = <3>;
 189                 clocks = <&gateclk 8>;
 190                 status = "disabled";
 191         };
 192
 193         pcie@5,0 {
 194                 device_type = "pci";
 195                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 196                 reg = <0x2800 0 0 0 0>;
 197                 #address-cells = <3>;
 198                 #size-cells = <2>;
 199                 #interrupt-cells = <1>;
 200                 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
 201                           0x81000000 0 0 0x81000000 0x5 0 1 0>;
 202                 interrupt-map-mask = <0 0 0 0>;
 203                 interrupt-map = <0 0 0 0 &mpic 62>;
 204                 marvell,pcie-port = <1>;
 205                 marvell,pcie-lane = <0>;
 206                 clocks = <&gateclk 9>;
 207                 status = "disabled";
 208         };
 209
 210         pcie@6,0 {
 211                 device_type = "pci";
 212                 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
 213                 reg = <0x3000 0 0 0 0>;
 214                 #address-cells = <3>;
 215                 #size-cells = <2>;
 216                 #interrupt-cells = <1>;
 217                 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
 218                           0x81000000 0 0 0x81000000 0x6 0 1 0>;
 219                 interrupt-map-mask = <0 0 0 0>;
 220                 interrupt-map = <0 0 0 0 &mpic 63>;
 221                 marvell,pcie-port = <1>;
 222                 marvell,pcie-lane = <1>;
 223                 clocks = <&gateclk 10>;
 224                 status = "disabled";
 225         };
 226
 227         pcie@7,0 {
 228                 device_type = "pci";
 229                 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
 230                 reg = <0x3800 0 0 0 0>;
 231                 #address-cells = <3>;
 232                 #size-cells = <2>;
 233                 #interrupt-cells = <1>;
 234                 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
 235                           0x81000000 0 0 0x81000000 0x7 0 1 0>;
 236                 interrupt-map-mask = <0 0 0 0>;
 237                 interrupt-map = <0 0 0 0 &mpic 64>;
 238                 marvell,pcie-port = <1>;
 239                 marvell,pcie-lane = <2>;
 240                 clocks = <&gateclk 11>;
 241                 status = "disabled";
 242         };
 243
 244         pcie@8,0 {
 245                 device_type = "pci";
 246                 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
 247                 reg = <0x4000 0 0 0 0>;
 248                 #address-cells = <3>;
 249                 #size-cells = <2>;
 250                 #interrupt-cells = <1>;
 251                 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
 252                           0x81000000 0 0 0x81000000 0x8 0 1 0>;
 253                 interrupt-map-mask = <0 0 0 0>;
 254                 interrupt-map = <0 0 0 0 &mpic 65>;
 255                 marvell,pcie-port = <1>;
 256                 marvell,pcie-lane = <3>;
 257                 clocks = <&gateclk 12>;
 258                 status = "disabled";
 259         };
 260
 261         pcie@9,0 {
 262                 device_type = "pci";
 263                 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
 264                 reg = <0x4800 0 0 0 0>;
 265                 #address-cells = <3>;
 266                 #size-cells = <2>;
 267                 #interrupt-cells = <1>;
 268                 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 269                           0x81000000 0 0 0x81000000 0x9 0 1 0>;
 270                 interrupt-map-mask = <0 0 0 0>;
 271                 interrupt-map = <0 0 0 0 &mpic 99>;
 272                 marvell,pcie-port = <2>;
 273                 marvell,pcie-lane = <0>;
 274                 clocks = <&gateclk 26>;
 275                 status = "disabled";
 276         };
 277
 278         pcie@10,0 {
 279                 device_type = "pci";
 280                 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
 281                 reg = <0x5000 0 0 0 0>;
 282                 #address-cells = <3>;
 283                 #size-cells = <2>;
 284                 #interrupt-cells = <1>;
 285                 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
 286                           0x81000000 0 0 0x81000000 0xa 0 1 0>;
 287                 interrupt-map-mask = <0 0 0 0>;
 288                 interrupt-map = <0 0 0 0 &mpic 103>;
 289                 marvell,pcie-port = <3>;
 290                 marvell,pcie-lane = <0>;
 291                 clocks = <&gateclk 27>;
 292                 status = "disabled";
 293         };
 294 };