1 NVIDIA Tegra PCIe controller
4 - compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
5 "nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
6 Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
7 <chip> is tegra132 or tegra210.
8 - device_type: Must be "pci"
9 - reg: A list of physical base address and length for each set of controller
10 registers. Must contain an entry for each entry in the reg-names property.
11 - reg-names: Must include the following entries:
12 "pads": PADS registers
14 "cs": configuration space region
15 - interrupts: A list of interrupt outputs of the controller. Must contain an
16 entry for each entry in the interrupt-names property.
17 - interrupt-names: Must include the following entries:
18 "intr": The Tegra interrupt that is asserted for controller interrupts
19 "msi": The Tegra interrupt that is asserted when an MSI is received
20 - bus-range: Range of bus numbers associated with this controller
21 - #address-cells: Address representation for root ports (must be 3)
22 - cell 0 specifies the bus and device numbers of the root port:
24 [15:11]: device number
25 - cell 1 denotes the upper 32 address bits and should be 0
26 - cell 2 contains the lower 32 address bits and is used to translate to the
28 - #size-cells: Size representation for root ports (must be 2)
29 - ranges: Describes the translation of addresses for root ports and standard
30 PCI regions. The entries must be 6 cells each, where the first three cells
31 correspond to the address as described for the #address-cells property
32 above, the fourth cell is the physical CPU address to translate to and the
33 fifth and six cells are as described for the #size-cells property above.
34 - The first two entries are expected to translate the addresses for the root
35 port registers, which are referenced by the assigned-addresses property of
36 the root port nodes (see below).
37 - The remaining entries setup the mapping for the standard I/O, memory and
38 prefetchable PCI regions. The first cell determines the type of region
40 - 0x81000000: I/O memory region
41 - 0x82000000: non-prefetchable memory region
42 - 0xc2000000: prefetchable memory region
43 Please refer to the standard PCI bus binding document for a more detailed
45 - #interrupt-cells: Size representation for interrupts (must be 1)
46 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
47 Please refer to the standard PCI bus binding document for a more detailed
49 - clocks: Must contain an entry for each entry in clock-names.
50 See ../clocks/clock-bindings.txt for details.
51 - clock-names: Must include the following entries:
55 - cml (not required for Tegra20)
56 - resets: Must contain an entry for each entry in reset-names.
57 See ../reset/reset.txt for details.
58 - reset-names: Must include the following entries:
63 Required properties on Tegra124 and later (deprecated):
64 - phys: Must contain an entry for each entry in phy-names.
65 - phy-names: Must include the following entries:
68 These properties are deprecated in favour of per-lane PHYs define in each of
69 the root ports (see below).
71 Power supplies for Tegra20:
72 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
73 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
74 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
76 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
78 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
80 Power supplies for Tegra30:
82 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
84 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
86 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
88 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
91 - If lanes 0 to 3 are used:
92 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
93 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
94 - If lanes 4 or 5 are used:
95 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
96 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
98 Power supplies for Tegra124:
100 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
101 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
102 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
104 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
106 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
108 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
110 - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
113 Root ports are defined as subnodes of the PCIe controller node.
116 - device_type: Must be "pci"
117 - assigned-addresses: Address and size of the port configuration registers
118 - reg: PCI bus address of the root port
119 - #address-cells: Must be 3
120 - #size-cells: Must be 2
121 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
122 property is sufficient.
123 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
125 - Root port 0 uses 4 lanes, root port 1 is unused.
126 - Both root ports use 2 lanes.
128 Required properties for Tegra124 and later:
129 - phys: Must contain an phandle to a PHY for each entry in phy-names.
130 - phy-names: Must include an entry for each active lane. Note that the number
131 of entries does not have to (though usually will) be equal to the specified
132 number of lanes in the nvidia,num-lanes property. Entries are of the form
133 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
143 pcie-controller@80003000 {
144 compatible = "nvidia,tegra20-pcie";
146 reg = <0x80003000 0x00000800 /* PADS registers */
147 0x80003800 0x00000200 /* AFI registers */
148 0x90000000 0x10000000>; /* configuration space */
149 reg-names = "pads", "afi", "cs";
150 interrupts = <0 98 0x04 /* controller interrupt */
151 0 99 0x04>; /* MSI interrupt */
152 interrupt-names = "intr", "msi";
154 #interrupt-cells = <1>;
155 interrupt-map-mask = <0 0 0 0>;
156 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
158 bus-range = <0x00 0xff>;
159 #address-cells = <3>;
162 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
163 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
164 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
165 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
166 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
168 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
169 clock-names = "pex", "afi", "pll_e";
170 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
171 reset-names = "pex", "afi", "pcie_x";
176 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
177 reg = <0x000800 0 0 0 0>;
180 #address-cells = <3>;
185 nvidia,num-lanes = <2>;
190 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
191 reg = <0x001000 0 0 0 0>;
194 #address-cells = <3>;
199 nvidia,num-lanes = <2>;
205 pcie-controller@80003000 {
208 vdd-supply = <&pci_vdd_reg>;
209 pex-clk-supply = <&pci_clk_reg>;
211 /* root port 00:01.0 */
215 /* bridge 01:00.0 (optional) */
217 reg = <0x010000 0 0 0 0>;
219 #address-cells = <3>;
224 /* endpoint 02:00.0 */
226 reg = <0x020000 0 0 0 0>;
232 Note that devices on the PCI bus are dynamically discovered using PCI's bus
233 enumeration and therefore don't need corresponding device nodes in DT. However
234 if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
235 device nodes need to be added in order to allow the bus' children to be
236 instantiated at the proper location in the operating system's device tree (as
237 illustrated by the optional nodes in the example above).
244 pcie-controller@00003000 {
245 compatible = "nvidia,tegra30-pcie";
247 reg = <0x00003000 0x00000800 /* PADS registers */
248 0x00003800 0x00000200 /* AFI registers */
249 0x10000000 0x10000000>; /* configuration space */
250 reg-names = "pads", "afi", "cs";
251 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
252 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
253 interrupt-names = "intr", "msi";
255 #interrupt-cells = <1>;
256 interrupt-map-mask = <0 0 0 0>;
257 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
259 bus-range = <0x00 0xff>;
260 #address-cells = <3>;
263 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
264 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
265 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
266 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
267 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
268 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
270 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
271 <&tegra_car TEGRA30_CLK_AFI>,
272 <&tegra_car TEGRA30_CLK_PLL_E>,
273 <&tegra_car TEGRA30_CLK_CML0>;
274 clock-names = "pex", "afi", "pll_e", "cml";
275 resets = <&tegra_car 70>,
278 reset-names = "pex", "afi", "pcie_x";
283 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
284 reg = <0x000800 0 0 0 0>;
287 #address-cells = <3>;
291 nvidia,num-lanes = <2>;
296 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
297 reg = <0x001000 0 0 0 0>;
300 #address-cells = <3>;
304 nvidia,num-lanes = <2>;
309 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
310 reg = <0x001800 0 0 0 0>;
313 #address-cells = <3>;
317 nvidia,num-lanes = <2>;
323 pcie-controller@00003000 {
326 avdd-pexa-supply = <&ldo1_reg>;
327 vdd-pexa-supply = <&ldo1_reg>;
328 avdd-pexb-supply = <&ldo1_reg>;
329 vdd-pexb-supply = <&ldo1_reg>;
330 avdd-pex-pll-supply = <&ldo1_reg>;
331 avdd-plle-supply = <&ldo1_reg>;
332 vddio-pex-ctl-supply = <&sys_3v3_reg>;
333 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
349 pcie-controller@01003000 {
350 compatible = "nvidia,tegra124-pcie";
352 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
353 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
354 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
355 reg-names = "pads", "afi", "cs";
356 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
357 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
358 interrupt-names = "intr", "msi";
360 #interrupt-cells = <1>;
361 interrupt-map-mask = <0 0 0 0>;
362 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
364 bus-range = <0x00 0xff>;
365 #address-cells = <3>;
368 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
369 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
370 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
371 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
372 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
374 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
375 <&tegra_car TEGRA124_CLK_AFI>,
376 <&tegra_car TEGRA124_CLK_PLL_E>,
377 <&tegra_car TEGRA124_CLK_CML0>;
378 clock-names = "pex", "afi", "pll_e", "cml";
379 resets = <&tegra_car 70>,
382 reset-names = "pex", "afi", "pcie_x";
387 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
388 reg = <0x000800 0 0 0 0>;
391 #address-cells = <3>;
395 nvidia,num-lanes = <2>;
400 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
401 reg = <0x001000 0 0 0 0>;
404 #address-cells = <3>;
408 nvidia,num-lanes = <1>;
414 pcie-controller@01003000 {
417 avddio-pex-supply = <&vdd_1v05_run>;
418 dvddio-pex-supply = <&vdd_1v05_run>;
419 avdd-pex-pll-supply = <&vdd_1v05_run>;
420 hvdd-pex-supply = <&vdd_3v3_lp0>;
421 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
422 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
423 avdd-pll-erefe-supply = <&avdd_1v05_run>;
427 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
428 phy-names = "pcie-0";
432 /* Gigabit Ethernet */
434 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
435 phy-names = "pcie-0";