Documentation/devicetree/bindings/phy/samsung-phy.txt

   1 Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY
   2 -------------------------------------------------
   3
   4 Required properties:
   5 - compatible : should be "samsung,s5pv210-mipi-video-phy";
   6 - reg : offset and length of the MIPI DPHY register set;
   7 - #phy-cells : from the generic phy bindings, must be 1;
   8
   9 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
  10 the PHY specifier identifies the PHY and its meaning is as follows:
  11   0 - MIPI CSIS 0,
  12   1 - MIPI DSIM 0,
  13   2 - MIPI CSIS 1,
  14   3 - MIPI DSIM 1.
  15
  16 Samsung EXYNOS SoC series Display Port PHY
  17 -------------------------------------------------
  18
  19 Required properties:
  20 - compatible : should be "samsung,exynos5250-dp-video-phy";
  21 - reg : offset and length of the Display Port PHY register set;
  22 - #phy-cells : from the generic PHY bindings, must be 0;
  23
  24 Samsung S5P/EXYNOS SoC series USB PHY
  25 -------------------------------------------------
  26
  27 Required properties:
  28 - compatible : should be one of the listed compatibles:
  29         - "samsung,s5pv210-usb2-phy"
  30         - "samsung,exynos4210-usb2-phy"
  31         - "samsung,exynos4x12-usb2-phy"
  32         - "samsung,exynos5250-usb2-phy"
  33 - reg : a list of registers used by phy driver
  34         - first and obligatory is the location of phy modules registers
  35 - samsung,sysreg-phandle - handle to syscon used to control the system registers
  36 - samsung,pmureg-phandle - handle to syscon used to control PMU registers
  37 - #phy-cells : from the generic phy bindings, must be 1;
  38 - clocks and clock-names:
  39         - the "phy" clock is required by the phy module, used as a gate
  40         - the "ref" clock is used to get the rate of the clock provided to the
  41           PHY module
  42
  43 The first phandle argument in the PHY specifier identifies the PHY, its
  44 meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
  45 and Exynos 4212) it is as follows:
  46   0 - USB device ("device"),
  47   1 - USB host ("host"),
  48   2 - HSIC0 ("hsic0"),
  49   3 - HSIC1 ("hsic1"),
  50
  51 Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
  52 register is supplied.
  53
  54 Example:
  55
  56 For Exynos 4412 (compatible with Exynos 4212):
  57
  58 usbphy: phy@125b0000 {
  59         compatible = "samsung,exynos4x12-usb2-phy";
  60         reg = <0x125b0000 0x100>;
  61         clocks = <&clock 305>, <&clock 2>;
  62         clock-names = "phy", "ref";
  63         status = "okay";
  64         #phy-cells = <1>;
  65         samsung,sysreg-phandle = <&sys_reg>;
  66         samsung,pmureg-phandle = <&pmu_reg>;
  67 };
  68
  69 Then the PHY can be used in other nodes such as:
  70
  71 phy-consumer@12340000 {
  72         phys = <&usbphy 2>;
  73         phy-names = "phy";
  74 };
  75
  76 Refer to DT bindings documentation of particular PHY consumer devices for more
  77 information about required PHYs and the way of specification.
  78
  79 Samsung SATA PHY Controller
  80 ---------------------------
  81
  82 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
  83 Each SATA PHY controller should have its own node.
  84
  85 Required properties:
  86 - compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
  87 - reg : offset and length of the SATA PHY register set;
  88 - #phy-cells : must be zero
  89 - clocks : must be exactly one entry
  90 - clock-names : must be "sata_phyctrl"
  91 - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
  92 - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
  93
  94 Example:
  95         sata_phy: sata-phy@12170000 {
  96                 compatible = "samsung,exynos5250-sata-phy";
  97                 reg = <0x12170000 0x1ff>;
  98                 clocks = <&clock 287>;
  99                 clock-names = "sata_phyctrl";
 100                 #phy-cells = <0>;
 101                 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
 102                 samsung,syscon-phandle = <&pmu_syscon>;
 103         };
 104
 105 Device-Tree bindings for sataphy i2c client driver
 106 --------------------------------------------------
 107
 108 Required properties:
 109 compatible: Should be "samsung,exynos-sataphy-i2c"
 110 - reg: I2C address of the sataphy i2c device.
 111
 112 Example:
 113
 114         sata_phy_i2c:sata-phy@38 {
 115                 compatible = "samsung,exynos-sataphy-i2c";
 116                 reg = <0x38>;
 117         };
 118
 119 Samsung Exynos5 SoC series USB DRD PHY controller
 120 --------------------------------------------------
 121
 122 Required properties:
 123 - compatible : Should be set to one of the following supported values:
 124         - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
 125         - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
 126 - reg : Register offset and length of USB DRD PHY register set;
 127 - clocks: Clock IDs array as required by the controller
 128 - clock-names: names of clocks correseponding to IDs in the clock property;
 129                Required clocks:
 130         - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
 131                used for register access.
 132         - ref: PHY's reference clock (usually crystal clock), used for
 133                PHY operations, associated by phy name. It is used to
 134                determine bit values for clock settings register.
 135                For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
 136 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
 137                       control pmu registers for power isolation.
 138 - #phy-cells : from the generic PHY bindings, must be 1;
 139
 140 For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
 141 compatible PHYs, the second cell in the PHY specifier identifies the
 142 PHY id, which is interpreted as follows:
 143   0 - UTMI+ type phy,
 144   1 - PIPE3 type phy,
 145
 146 Example:
 147         usbdrd_phy: usbphy@12100000 {
 148                 compatible = "samsung,exynos5250-usbdrd-phy";
 149                 reg = <0x12100000 0x100>;
 150                 clocks = <&clock 286>, <&clock 1>;
 151                 clock-names = "phy", "ref";
 152                 samsung,pmu-syscon = <&pmu_system_controller>;
 153                 #phy-cells = <1>;
 154         };
 155
 156 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
 157            'usbdrd_phy' nodes should have numbered alias in the aliases node,
 158            in the form of usbdrdphyN, N = 0, 1... (depending on number of
 159            controllers).
 160 Example:
 161         aliases {
 162                 usbdrdphy0 = &usb3_phy0;
 163                 usbdrdphy1 = &usb3_phy1;
 164         };