b50e1c10a05d3d5ab998602772276720699c3ef3
[deliverable/linux.git] / Documentation / devicetree / bindings / phy / ti-phy.txt
1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
2
3 OMAP CONTROL PHY
4
5 Required properties:
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
9 e.g. USB2_PHY on OMAP5.
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
13 DRA7 platform.
14 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
15 AM437 platform.
16 - reg : Address and length of the register set for the device. It contains
17 the address of "otghs_control" for control-phy-otghs or "power" register
18 for other types.
19 - reg-names: should be "otghs_control" control-phy-otghs and "power" for
20 other types.
21
22 omap_control_usb: omap-control-usb@4a002300 {
23 compatible = "ti,control-phy-otghs";
24 reg = <0x4a00233c 0x4>;
25 reg-names = "otghs_control";
26 };
27
28 OMAP USB2 PHY
29
30 Required properties:
31 - compatible: Should be "ti,omap-usb2"
32 - reg : Address and length of the register set for the device.
33 - #phy-cells: determine the number of cells that should be given in the
34 phandle while referencing this phy.
35 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
36 clock-names.
37 - clock-names: should include:
38 * "wkupclk" - wakeup clock.
39 * "refclk" - reference clock (optional).
40
41 Optional properties:
42 - ctrl-module : phandle of the control module used by PHY driver to power on
43 the PHY.
44
45 This is usually a subnode of ocp2scp to which it is connected.
46
47 usb2phy@4a0ad080 {
48 compatible = "ti,omap-usb2";
49 reg = <0x4a0ad080 0x58>;
50 ctrl-module = <&omap_control_usb>;
51 #phy-cells = <0>;
52 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
53 clock-names = "wkupclk", "refclk";
54 };
55
56 TI PIPE3 PHY
57
58 Required properties:
59 - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
60 "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
61 - reg : Address and length of the register set for the device.
62 - reg-names: The names of the register addresses corresponding to the registers
63 filled in "reg".
64 - #phy-cells: determine the number of cells that should be given in the
65 phandle while referencing this phy.
66 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
67 clock-names.
68 - clock-names: should include:
69 * "wkupclk" - wakeup clock.
70 * "sysclk" - system clock.
71 * "refclk" - reference clock.
72 * "dpll_ref" - external dpll ref clk
73 * "dpll_ref_m2" - external dpll ref clk
74 * "phy-div" - divider for apll
75 * "div-clk" - apll clock
76
77 Optional properties:
78 - ctrl-module : phandle of the control module used by PHY driver to power on
79 the PHY.
80 - id: If there are multiple instance of the same type, in order to
81 differentiate between each instance "id" can be used (e.g., multi-lane PCIe
82 PHY). If "id" is not provided, it is set to default value of '1'.
83
84 This is usually a subnode of ocp2scp to which it is connected.
85
86 usb3phy@4a084400 {
87 compatible = "ti,phy-usb3";
88 reg = <0x4a084400 0x80>,
89 <0x4a084800 0x64>,
90 <0x4a084c00 0x40>;
91 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
92 ctrl-module = <&omap_control_usb>;
93 #phy-cells = <0>;
94 clocks = <&usb_phy_cm_clk32k>,
95 <&sys_clkin>,
96 <&usb_otg_ss_refclk960m>;
97 clock-names = "wkupclk",
98 "sysclk",
99 "refclk";
100 };
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