Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt

   1 NVIDIA Tegra114 pinmux controller
   2
   3 The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
   4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
   5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
   6 a baseline, and only documents the differences between the two bindings.
   7
   8 Required properties:
   9 - compatible: "nvidia,tegra114-pinmux"
  10 - reg: Should contain the register physical address and length for each of
  11   the pad control and mux registers. The first bank of address must be the
  12   driver strength pad control register address and second bank address must
  13   be pinmux register address.
  14
  15 Tegra114 adds the following optional properties for pin configuration subnodes:
  16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
  17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
  18 - nvidia,lock: Integer. Lock the pin configuration against further changes
  19     until reset. 0: no, 1: yes.
  20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
  21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
  22 - nvidia,drive-type: Integer. Valid range 0...3.
  23
  24 As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding
  25 which groups support which functionality.
  26
  27 Valid values for pin and group names are:
  28
  29   per-pin mux groups:
  30
  31     These all support nvidia,function, nvidia,tristate, nvidia,pull,
  32     nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
  33     nvidia,io-reset and nvidia,rcv-sel.
  34
  35     ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
  36     ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
  37     ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
  38     dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
  39     sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
  40     sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
  41     ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
  42     uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
  43     uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,
  44     gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,
  45     clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
  46     gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,
  47     gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,
  48     gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
  49     gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
  50     gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
  51     gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,
  52     gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,
  53     gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
  54     sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
  55     sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,
  56     pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
  57     pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,
  58     kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,
  59     kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,
  60     kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
  61     kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,
  62     cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
  63     dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,
  64     dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
  65     gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,
  66     gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,
  67     sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
  68     sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
  69     gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,
  70     sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.
  71
  72   drive groups:
  73
  74     These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
  75     nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
  76     support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
  77     and nvidia,drive-type.
  78
  79     ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
  80     dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
  81     gmh, owr, uda.
  82
  83 Valid values for nvidia,functions are:
  84
  85   blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
  86   displaya_alt, displayb, dtv, emc_dll, extperiph1, extperiph2,
  87   extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr,
  88   i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, nand, nand_alt, owr, pmi,
  89   pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, rsvd2, rsvd3,
  90   rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3,
  91   spi4, spi5, spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi,
  92   usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3
  93
  94 Example:
  95
  96         pinmux: pinmux {
  97                 compatible = "nvidia,tegra114-pinmux";
  98                 reg = <0x70000868 0x148         /* Pad control registers */
  99                        0x70003000 0x40c>;       /* PinMux registers */
 100         };
 101
 102 Example board file extract:
 103
 104         pinctrl {
 105                 sdmmc4_default: pinmux {
 106                         sdmmc4_clk_pcc4 {
 107                                 nvidia,pins = "sdmmc4_clk_pcc4",
 108                                 nvidia,function = "sdmmc4";
 109                                 nvidia,pull = <0>;
 110                                 nvidia,tristate = <0>;
 111                         };
 112                         sdmmc4_dat0_paa0 {
 113                                 nvidia,pins = "sdmmc4_dat0_paa0",
 114                                                 "sdmmc4_dat1_paa1",
 115                                                 "sdmmc4_dat2_paa2",
 116                                                 "sdmmc4_dat3_paa3",
 117                                                 "sdmmc4_dat4_paa4",
 118                                                 "sdmmc4_dat5_paa5",
 119                                                 "sdmmc4_dat6_paa6",
 120                                                 "sdmmc4_dat7_paa7";
 121                                 nvidia,function = "sdmmc4";
 122                                 nvidia,pull = <2>;
 123                                 nvidia,tristate = <0>;
 124                         };
 125                 };
 126         };
 127
 128         sdhci@78000400 {
 129                 pinctrl-names = "default";
 130                 pinctrl-0 = <&sdmmc4_default>;
 131         };