Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt

   1 Qualcomm APQ8084 TLMM block
   2
   3 This binding describes the Top Level Mode Multiplexer block found in the
   4 MSM8960 platform.
   5
   6 - compatible:
   7         Usage: required
   8         Value type: <string>
   9         Definition: must be "qcom,apq8084-pinctrl"
  10
  11 - reg:
  12         Usage: required
  13         Value type: <prop-encoded-array>
  14         Definition: the base address and size of the TLMM register space.
  15
  16 - interrupts:
  17         Usage: required
  18         Value type: <prop-encoded-array>
  19         Definition: should specify the TLMM summary IRQ.
  20
  21 - interrupt-controller:
  22         Usage: required
  23         Value type: <none>
  24         Definition: identifies this node as an interrupt controller
  25
  26 - #interrupt-cells:
  27         Usage: required
  28         Value type: <u32>
  29         Definition: must be 2. Specifying the pin number and flags, as defined
  30                     in <dt-bindings/interrupt-controller/irq.h>
  31
  32 - gpio-controller:
  33         Usage: required
  34         Value type: <none>
  35         Definition: identifies this node as a gpio controller
  36
  37 - #gpio-cells:
  38         Usage: required
  39         Value type: <u32>
  40         Definition: must be 2. Specifying the pin number and flags, as defined
  41                     in <dt-bindings/gpio/gpio.h>
  42
  43 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
  44 a general description of GPIO and interrupt bindings.
  45
  46 Please refer to pinctrl-bindings.txt in this directory for details of the
  47 common pinctrl bindings used by client devices, including the meaning of the
  48 phrase "pin configuration node".
  49
  50 The pin configuration nodes act as a container for an arbitrary number of
  51 subnodes. Each of these subnodes represents some desired configuration for a
  52 pin, a group, or a list of pins or groups. This configuration can include the
  53 mux function to select on those pin(s)/group(s), and various pin configuration
  54 parameters, such as pull-up, drive strength, etc.
  55
  56
  57 PIN CONFIGURATION NODES:
  58
  59 The name of each subnode is not important; all subnodes should be enumerated
  60 and processed purely based on their content.
  61
  62 Each subnode only affects those parameters that are explicitly listed. In
  63 other words, a subnode that lists a mux function but no pin configuration
  64 parameters implies no information about any pin configuration parameters.
  65 Similarly, a pin subnode that describes a pullup parameter implies no
  66 information about e.g. the mux function.
  67
  68
  69 The following generic properties as defined in pinctrl-bindings.txt are valid
  70 to specify in a pin configuration subnode:
  71
  72 - pins:
  73         Usage: required
  74         Value type: <string-array>
  75         Definition: List of gpio pins affected by the properties specified in
  76                     this subnode.  Valid pins are:
  77                     gpio0-gpio146,
  78                     sdc1_clk,
  79                     sdc1_cmd,
  80                     sdc1_data
  81                     sdc2_clk,
  82                     sdc2_cmd,
  83                     sdc2_data
  84
  85 - function:
  86         Usage: required
  87         Value type: <string>
  88         Definition: Specify the alternative function to be configured for the
  89                     specified pins. Functions are only valid for gpio pins.
  90                     Valid values are:
  91                     adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
  92                     blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
  93                     blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
  94                     blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
  95                     blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
  96                     blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
  97                     blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
  98                     blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
  99                     blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
 100                     blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
 101                     blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
 102                     cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
 103                     cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
 104                     edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
 105                     gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
 106                     hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
 107                     ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
 108                     pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
 109                     qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
 110                     sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
 111                     spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
 112                     tsif2, uim, uim_batt_alarm
 113
 114 - bias-disable:
 115         Usage: optional
 116         Value type: <none>
 117         Definition: The specified pins should be configued as no pull.
 118
 119 - bias-pull-down:
 120         Usage: optional
 121         Value type: <none>
 122         Definition: The specified pins should be configued as pull down.
 123
 124 - bias-pull-up:
 125         Usage: optional
 126         Value type: <none>
 127         Definition: The specified pins should be configued as pull up.
 128
 129 - output-high:
 130         Usage: optional
 131         Value type: <none>
 132         Definition: The specified pins are configured in output mode, driven
 133                     high.
 134                     Not valid for sdc pins.
 135
 136 - output-low:
 137         Usage: optional
 138         Value type: <none>
 139         Definition: The specified pins are configured in output mode, driven
 140                     low.
 141                     Not valid for sdc pins.
 142
 143 - drive-strength:
 144         Usage: optional
 145         Value type: <u32>
 146         Definition: Selects the drive strength for the specified pins, in mA.
 147                     Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
 148
 149 Example:
 150
 151         tlmm: pinctrl@fd510000 {
 152                 compatible = "qcom,apq8084-pinctrl";
 153                 reg = <0xfd510000 0x4000>;
 154
 155                 gpio-controller;
 156                 #gpio-cells = <2>;
 157                 interrupt-controller;
 158                 #interrupt-cells = <2>;
 159                 interrupts = <0 208 0>;
 160
 161                 uart2: uart2-default {
 162                         mux {
 163                                 pins = "gpio4", "gpio5";
 164                                 function = "blsp_uart2";
 165                         };
 166
 167                         tx {
 168                                 pins = "gpio4";
 169                                 drive-strength = <4>;
 170                                 bias-disable;
 171                         };
 172
 173                         rx {
 174                                 pins = "gpio5";
 175                                 drive-strength = <2>;
 176                                 bias-pull-up;
 177                         };
 178                 };
 179         };