Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt

   1 * Pin configuration nodes
   2
   3 Required properties:
   4 - linux,phandle : phandle of this node; likely referenced by a QE
   5   device.
   6 - pio-map : array of pin configurations.  Each pin is defined by 6
   7   integers.  The six numbers are respectively: port, pin, dir,
   8   open_drain, assignment, has_irq.
   9   - port : port number of the pin; 0-6 represent port A-G in UM.
  10   - pin : pin number in the port.
  11   - dir : direction of the pin, should encode as follows:
  12
  13      0 = The pin is disabled
  14      1 = The pin is an output
  15      2 = The pin is an input
  16      3 = The pin is I/O
  17
  18   - open_drain : indicates the pin is normal or wired-OR:
  19
  20      0 = The pin is actively driven as an output
  21      1 = The pin is an open-drain driver. As an output, the pin is
  22          driven active-low, otherwise it is three-stated.
  23
  24   - assignment : function number of the pin according to the Pin Assignment
  25     tables in User Manual.  Each pin can have up to 4 possible functions in
  26     QE and two options for CPM.
  27   - has_irq : indicates if the pin is used as source of external
  28     interrupts.
  29
  30 Example:
  31      ucc_pin@01 {
  32         linux,phandle = <140001>;
  33         pio-map = <
  34         /* port  pin  dir  open_drain  assignment  has_irq */
  35                 0  3  1  0  1  0        /* TxD0 */
  36                 0  4  1  0  1  0        /* TxD1 */
  37                 0  5  1  0  1  0        /* TxD2 */
  38                 0  6  1  0  1  0        /* TxD3 */
  39                 1  6  1  0  3  0        /* TxD4 */
  40                 1  7  1  0  1  0        /* TxD5 */
  41                 1  9  1  0  2  0        /* TxD6 */
  42                 1  a  1  0  2  0        /* TxD7 */
  43                 0  9  2  0  1  0        /* RxD0 */
  44                 0  a  2  0  1  0        /* RxD1 */
  45                 0  b  2  0  1  0        /* RxD2 */
  46                 0  c  2  0  1  0        /* RxD3 */
  47                 0  d  2  0  1  0        /* RxD4 */
  48                 1  1  2  0  2  0        /* RxD5 */
  49                 1  0  2  0  2  0        /* RxD6 */
  50                 1  4  2  0  2  0        /* RxD7 */
  51                 0  7  1  0  1  0        /* TX_EN */
  52                 0  8  1  0  1  0        /* TX_ER */
  53                 0  f  2  0  1  0        /* RX_DV */
  54                 0  10 2  0  1  0        /* RX_ER */
  55                 0  0  2  0  1  0        /* RX_CLK */
  56                 2  9  1  0  3  0        /* GTX_CLK - CLK10 */
  57                 2  8  2  0  1  0>;      /* GTX125 - CLK9 */
  58      };
  59
  60