Documentation/devicetree/bindings/powerpc/fsl/fman.txt

   1 =============================================================================
   2 Freescale Frame Manager Device Bindings
   3
   4 CONTENTS
   5   - FMan Node
   6   - FMan Port Node
   7   - FMan MURAM Node
   8   - FMan dTSEC/XGEC/mEMAC Node
   9   - FMan IEEE 1588 Node
  10   - FMan MDIO Node
  11   - Example
  12
  13 =============================================================================
  14 FMan Node
  15
  16 DESCRIPTION
  17
  18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
  19 etc.) the FMan node will have child nodes for each of them.
  20
  21 PROPERTIES
  22
  23 - compatible
  24                 Usage: required
  25                 Value type: <stringlist>
  26                 Definition: Must include "fsl,fman"
  27                 FMan version can be determined via FM_IP_REV_1 register in the
  28                 FMan block. The offset is 0xc4 from the beginning of the
  29                 Frame Processing Manager memory map (0xc3000 from the
  30                 beginning of the FMan node).
  31
  32 - cell-index
  33                 Usage: required
  34                 Value type: <u32>
  35                 Definition: Specifies the index of the FMan unit.
  36
  37                 The cell-index value may be used by the SoC, to identify the
  38                 FMan unit in the SoC memory map. In the table bellow,
  39                 there's a description of the cell-index use in each SoC:
  40
  41                 - P1023:
  42                 register[bit]                   FMan unit       cell-index
  43                 ============================================================
  44                 DEVDISR[1]                      1               0
  45
  46                 - P2041, P3041, P4080 P5020, P5040:
  47                 register[bit]                   FMan unit       cell-index
  48                 ============================================================
  49                 DCFG_DEVDISR2[6]                1               0
  50                 DCFG_DEVDISR2[14]               2               1
  51                         (Second FM available only in P4080 and P5040)
  52
  53                 - B4860, T1040, T2080, T4240:
  54                 register[bit]                   FMan unit       cell-index
  55                 ============================================================
  56                 DCFG_CCSR_DEVDISR2[24]          1               0
  57                 DCFG_CCSR_DEVDISR2[25]          2               1
  58                         (Second FM available only in T4240)
  59
  60                 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
  61                 the specific SoC "Device Configuration/Pin Control" Memory
  62                 Map.
  63
  64 - reg
  65                 Usage: required
  66                 Value type: <prop-encoded-array>
  67                 Definition: A standard property. Specifies the offset of the
  68                 following configuration registers:
  69                 - BMI configuration registers.
  70                 - QMI configuration registers.
  71                 - DMA configuration registers.
  72                 - FPM configuration registers.
  73                 - FMan controller configuration registers.
  74
  75 - ranges
  76                 Usage: required
  77                 Value type: <prop-encoded-array>
  78                 Definition: A standard property.
  79
  80 - clocks
  81                 Usage: required
  82                 Value type: <prop-encoded-array>
  83                 Definition: phandle for the fman input clock.
  84
  85 - clock-names
  86                 usage: required
  87                 Value type: <stringlist>
  88                 Definition: "fmanclk" for the fman input clock.
  89
  90 - interrupts
  91                 Usage: required
  92                 Value type: <prop-encoded-array>
  93                 Definition: A pair of IRQs are specified in this property.
  94                 The first element is associated with the event interrupts and
  95                 the second element is associated with the error interrupts.
  96
  97 - fsl,qman-channel-range
  98                 Usage: required
  99                 Value type: <prop-encoded-array>
 100                 Definition: Specifies the range of the available dedicated
 101                 channels in the FMan. The first cell specifies the beginning
 102                 of the range and the second cell specifies the number of
 103                 channels.
 104                 Further information available at:
 105                 "Work Queue (WQ) Channel Assignments in the QMan" section
 106                 in DPAA Reference Manual.
 107
 108 - fsl,qman
 109 - fsl,bman
 110                 Usage: required
 111                 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
 112
 113 =============================================================================
 114 FMan MURAM Node
 115
 116 DESCRIPTION
 117
 118 FMan Internal memory - shared between all the FMan modules.
 119 It contains data structures that are common and written to or read by
 120 the modules.
 121 FMan internal memory is split into the following parts:
 122         Packet buffering (Tx/Rx FIFOs)
 123         Frames internal context
 124
 125 PROPERTIES
 126
 127 - compatible
 128                 Usage: required
 129                 Value type: <stringlist>
 130                 Definition: Must include "fsl,fman-muram"
 131
 132 - ranges
 133                 Usage: required
 134                 Value type: <prop-encoded-array>
 135                 Definition: A standard property.
 136                 Specifies the multi-user memory offset and the size within
 137                 the FMan.
 138
 139 EXAMPLE
 140
 141 muram@0 {
 142         compatible = "fsl,fman-muram";
 143         ranges = <0 0x000000 0x28000>;
 144 };
 145
 146 =============================================================================
 147 FMan Port Node
 148
 149 DESCRIPTION
 150
 151 The Frame Manager (FMan) supports several types of hardware ports:
 152         Ethernet receiver (RX)
 153         Ethernet transmitter (TX)
 154         Offline/Host command (O/H)
 155
 156 PROPERTIES
 157
 158 - compatible
 159                 Usage: required
 160                 Value type: <stringlist>
 161                 Definition: A standard property.
 162                 Must include one of the following:
 163                         - "fsl,fman-v2-port-oh" for FManV2 OH ports
 164                         - "fsl,fman-v2-port-rx" for FManV2 RX ports
 165                         - "fsl,fman-v2-port-tx" for FManV2 TX ports
 166                         - "fsl,fman-v3-port-oh" for FManV3 OH ports
 167                         - "fsl,fman-v3-port-rx" for FManV3 RX ports
 168                         - "fsl,fman-v3-port-tx" for FManV3 TX ports
 169
 170 - cell-index
 171                 Usage: required
 172                 Value type: <u32>
 173                 Definition: Specifies the hardware port id.
 174                 Each hardware port on the FMan has its own hardware PortID.
 175                 Super set of all hardware Port IDs available at FMan Reference
 176                 Manual under "FMan Hardware Ports in Freescale Devices" table.
 177
 178                 Each hardware port is assigned a 4KB, port-specific page in
 179                 the FMan hardware port memory region (which is part of the
 180                 FMan memory map). The first 4 KB in the FMan hardware ports
 181                 memory region is used for what are called common registers.
 182                 The subsequent 63 4KB pages are allocated to the hardware
 183                 ports.
 184                 The page of a specific port is determined by the cell-index.
 185
 186 - reg
 187                 Usage: required
 188                 Value type: <prop-encoded-array>
 189                 Definition: There is one reg region describing the port
 190                 configuration registers.
 191
 192 - fsl,fman-10g-port
 193                 Usage: optional
 194                 Value type: boolean
 195                 Definition: The default port rate is 1G.
 196                 If this property exists, the port is s 10G port.
 197
 198 - fsl,fman-best-effort-port
 199                 Usage: optional
 200                 Value type: boolean
 201                 Definition: Can be defined only if 10G-support is set.
 202                 This property marks a best-effort 10G port (10G port that
 203                 may not be capable of line rate).
 204
 205 EXAMPLE
 206
 207 port@a8000 {
 208         cell-index = <0x28>;
 209         compatible = "fsl,fman-v2-port-tx";
 210         reg = <0xa8000 0x1000>;
 211 };
 212
 213 port@88000 {
 214         cell-index = <0x8>;
 215         compatible = "fsl,fman-v2-port-rx";
 216         reg = <0x88000 0x1000>;
 217 };
 218
 219 port@81000 {
 220         cell-index = <0x1>;
 221         compatible = "fsl,fman-v2-port-oh";
 222         reg = <0x81000 0x1000>;
 223 };
 224
 225 =============================================================================
 226 FMan dTSEC/XGEC/mEMAC Node
 227
 228 DESCRIPTION
 229
 230 mEMAC/dTSEC/XGEC are the Ethernet network interfaces
 231
 232 PROPERTIES
 233
 234 - compatible
 235                 Usage: required
 236                 Value type: <stringlist>
 237                 Definition: A standard property.
 238                 Must include one of the following:
 239                 - "fsl,fman-dtsec" for dTSEC MAC
 240                 - "fsl,fman-xgec" for XGEC MAC
 241                 - "fsl,fman-memac for mEMAC MAC
 242
 243 - cell-index
 244                 Usage: required
 245                 Value type: <u32>
 246                 Definition: Specifies the MAC id.
 247
 248                 The cell-index value may be used by the FMan or the SoC, to
 249                 identify the MAC unit in the FMan (or SoC) memory map.
 250                 In the tables bellow there's a description of the cell-index
 251                 use, there are two tables, one describes the use of cell-index
 252                 by the FMan, the second describes the use by the SoC:
 253
 254                 1. FMan Registers
 255
 256                 FManV2:
 257                 register[bit]           MAC             cell-index
 258                 ============================================================
 259                 FM_EPI[16]              XGEC            8
 260                 FM_EPI[16+n]            dTSECn          n-1
 261                 FM_NPI[11+n]            dTSECn          n-1
 262                         n = 1,..,5
 263
 264                 FManV3:
 265                 register[bit]           MAC             cell-index
 266                 ============================================================
 267                 FM_EPI[16+n]            mEMACn          n-1
 268                 FM_EPI[25]              mEMAC10         9
 269
 270                 FM_NPI[11+n]            mEMACn          n-1
 271                 FM_NPI[10]              mEMAC10         9
 272                 FM_NPI[11]              mEMAC9          8
 273                         n = 1,..8
 274
 275                 FM_EPI and FM_NPI are located in the FMan memory map.
 276
 277                 2. SoC registers:
 278
 279                 - P2041, P3041, P4080 P5020, P5040:
 280                 register[bit]           FMan            MAC             cell
 281                                         Unit                            index
 282                 ============================================================
 283                 DCFG_DEVDISR2[7]        1               XGEC            8
 284                 DCFG_DEVDISR2[7+n]      1               dTSECn          n-1
 285                 DCFG_DEVDISR2[15]       2               XGEC            8
 286                 DCFG_DEVDISR2[15+n]     2               dTSECn          n-1
 287                         n = 1,..5
 288
 289                 - T1040, T2080, T4240, B4860:
 290                 register[bit]                   FMan    MAC             cell
 291                                                 Unit                    index
 292                 ============================================================
 293                 DCFG_CCSR_DEVDISR2[n-1]         1       mEMACn          n-1
 294                 DCFG_CCSR_DEVDISR2[11+n]        2       mEMACn          n-1
 295                         n = 1,..6,9,10
 296
 297                 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
 298                 the specific SoC "Device Configuration/Pin Control" Memory
 299                 Map.
 300
 301 - reg
 302                 Usage: required
 303                 Value type: <prop-encoded-array>
 304                 Definition: A standard property.
 305
 306 - fsl,fman-ports
 307                 Usage: required
 308                 Value type: <prop-encoded-array>
 309                 Definition: An array of two phandles - the first references is
 310                 the FMan RX port and the second is the TX port used by this
 311                 MAC.
 312
 313 - ptp-timer
 314                 Usage required
 315                 Value type: <phandle>
 316                 Definition: A phandle for 1EEE1588 timer.
 317
 318 - pcsphy-handle
 319                 Usage required for "fsl,fman-memac" MACs
 320                 Value type: <phandle>
 321                 Definition: A phandle for pcsphy.
 322
 323 - tbi-handle
 324                 Usage required for "fsl,fman-dtsec" MACs
 325                 Value type: <phandle>
 326                 Definition: A phandle for tbiphy.
 327
 328 EXAMPLE
 329
 330 fman1_tx28: port@a8000 {
 331         cell-index = <0x28>;
 332         compatible = "fsl,fman-v2-port-tx";
 333         reg = <0xa8000 0x1000>;
 334 };
 335
 336 fman1_rx8: port@88000 {
 337         cell-index = <0x8>;
 338         compatible = "fsl,fman-v2-port-rx";
 339         reg = <0x88000 0x1000>;
 340 };
 341
 342 ptp-timer: ptp_timer@fe000 {
 343         compatible = "fsl,fman-ptp-timer";
 344         reg = <0xfe000 0x1000>;
 345 };
 346
 347 ethernet@e0000 {
 348         compatible = "fsl,fman-dtsec";
 349         cell-index = <0>;
 350         reg = <0xe0000 0x1000>;
 351         fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
 352         ptp-timer = <&ptp-timer>;
 353         tbi-handle = <&tbi0>;
 354 };
 355
 356 ============================================================================
 357 FMan IEEE 1588 Node
 358
 359 DESCRIPTION
 360
 361 The FMan interface to support IEEE 1588
 362
 363
 364 PROPERTIES
 365
 366 - compatible
 367                 Usage: required
 368                 Value type: <stringlist>
 369                 Definition: A standard property.
 370                 Must include "fsl,fman-ptp-timer".
 371
 372 - reg
 373                 Usage: required
 374                 Value type: <prop-encoded-array>
 375                 Definition: A standard property.
 376
 377 EXAMPLE
 378
 379 ptp-timer@fe000 {
 380         compatible = "fsl,fman-ptp-timer";
 381         reg = <0xfe000 0x1000>;
 382 };
 383
 384 =============================================================================
 385 FMan MDIO Node
 386
 387 DESCRIPTION
 388
 389 The MDIO is a bus to which the PHY devices are connected.
 390
 391 PROPERTIES
 392
 393 - compatible
 394                 Usage: required
 395                 Value type: <stringlist>
 396                 Definition: A standard property.
 397                 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
 398                 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
 399                 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
 400                 FMan v3.
 401
 402 - reg
 403                 Usage: required
 404                 Value type: <prop-encoded-array>
 405                 Definition: A standard property.
 406
 407 - bus-frequency
 408                 Usage: optional
 409                 Value type: <u32>
 410                 Definition: Specifies the external MDIO bus clock speed to
 411                 be used, if different from the standard 2.5 MHz.
 412                 This may be due to the standard speed being unsupported (e.g.
 413                 due to a hardware problem), or to advertise that all relevant
 414                 components in the system support a faster speed.
 415
 416 - interrupts
 417                 Usage: required for external MDIO
 418                 Value type: <prop-encoded-array>
 419                 Definition: Event interrupt of external MDIO controller.
 420
 421 - fsl,fman-internal-mdio
 422                 Usage: required for internal MDIO
 423                 Value type: boolean
 424                 Definition: Fman has internal MDIO for internal PCS(Physical
 425                 Coding Sublayer) PHYs and external MDIO for external PHYs.
 426                 The settings and programming routines for internal/external
 427                 MDIO are different. Must be included for internal MDIO.
 428
 429 For internal PHY device on internal mdio bus, a PHY node should be created.
 430 See the definition of the PHY node in booting-without-of.txt for an
 431 example of how to define a PHY (Internal PHY has no interrupt line).
 432 - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
 433 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
 434   PCS PHY addr must be '0'.
 435
 436 EXAMPLE
 437
 438 Example for FMan v2 external MDIO:
 439
 440 mdio@f1000 {
 441         compatible = "fsl,fman-xmdio";
 442         reg = <0xf1000 0x1000>;
 443         interrupts = <101 2 0 0>;
 444 };
 445
 446 Example for FMan v2 internal MDIO:
 447
 448 mdio@e3120 {
 449         compatible = "fsl,fman-mdio";
 450         reg = <0xe3120 0xee0>;
 451         fsl,fman-internal-mdio;
 452
 453         tbi1: tbi-phy@8 {
 454                 reg = <0x8>;
 455                 device_type = "tbi-phy";
 456         };
 457 };
 458
 459 Example for FMan v3 internal MDIO:
 460
 461 mdio@f1000 {
 462         compatible = "fsl,fman-memac-mdio";
 463         reg = <0xf1000 0x1000>;
 464         fsl,fman-internal-mdio;
 465
 466         pcsphy6: ethernet-phy@0 {
 467                 reg = <0x0>;
 468         };
 469 };
 470
 471 =============================================================================
 472 Example
 473
 474 fman@400000 {
 475         #address-cells = <1>;
 476         #size-cells = <1>;
 477         cell-index = <1>;
 478         compatible = "fsl,fman"
 479         ranges = <0 0x400000 0x100000>;
 480         reg = <0x400000 0x100000>;
 481         clocks = <&fman_clk>;
 482         clock-names = "fmanclk";
 483         interrupts = <
 484                 96 2 0 0
 485                 16 2 1 1>;
 486         fsl,qman-channel-range = <0x40 0xc>;
 487
 488         muram@0 {
 489                 compatible = "fsl,fman-muram";
 490                 reg = <0x0 0x28000>;
 491         };
 492
 493         port@81000 {
 494                 cell-index = <1>;
 495                 compatible = "fsl,fman-v2-port-oh";
 496                 reg = <0x81000 0x1000>;
 497         };
 498
 499         port@82000 {
 500                 cell-index = <2>;
 501                 compatible = "fsl,fman-v2-port-oh";
 502                 reg = <0x82000 0x1000>;
 503         };
 504
 505         port@83000 {
 506                 cell-index = <3>;
 507                 compatible = "fsl,fman-v2-port-oh";
 508                 reg = <0x83000 0x1000>;
 509         };
 510
 511         port@84000 {
 512                 cell-index = <4>;
 513                 compatible = "fsl,fman-v2-port-oh";
 514                 reg = <0x84000 0x1000>;
 515         };
 516
 517         port@85000 {
 518                 cell-index = <5>;
 519                 compatible = "fsl,fman-v2-port-oh";
 520                 reg = <0x85000 0x1000>;
 521         };
 522
 523         port@86000 {
 524                 cell-index = <6>;
 525                 compatible = "fsl,fman-v2-port-oh";
 526                 reg = <0x86000 0x1000>;
 527         };
 528
 529         fman1_rx_0x8: port@88000 {
 530                 cell-index = <0x8>;
 531                 compatible = "fsl,fman-v2-port-rx";
 532                 reg = <0x88000 0x1000>;
 533         };
 534
 535         fman1_rx_0x9: port@89000 {
 536                 cell-index = <0x9>;
 537                 compatible = "fsl,fman-v2-port-rx";
 538                 reg = <0x89000 0x1000>;
 539         };
 540
 541         fman1_rx_0xa: port@8a000 {
 542                 cell-index = <0xa>;
 543                 compatible = "fsl,fman-v2-port-rx";
 544                 reg = <0x8a000 0x1000>;
 545         };
 546
 547         fman1_rx_0xb: port@8b000 {
 548                 cell-index = <0xb>;
 549                 compatible = "fsl,fman-v2-port-rx";
 550                 reg = <0x8b000 0x1000>;
 551         };
 552
 553         fman1_rx_0xc: port@8c000 {
 554                 cell-index = <0xc>;
 555                 compatible = "fsl,fman-v2-port-rx";
 556                 reg = <0x8c000 0x1000>;
 557         };
 558
 559         fman1_rx_0x10: port@90000 {
 560                 cell-index = <0x10>;
 561                 compatible = "fsl,fman-v2-port-rx";
 562                 reg = <0x90000 0x1000>;
 563         };
 564
 565         fman1_tx_0x28: port@a8000 {
 566                 cell-index = <0x28>;
 567                 compatible = "fsl,fman-v2-port-tx";
 568                 reg = <0xa8000 0x1000>;
 569         };
 570
 571         fman1_tx_0x29: port@a9000 {
 572                 cell-index = <0x29>;
 573                 compatible = "fsl,fman-v2-port-tx";
 574                 reg = <0xa9000 0x1000>;
 575         };
 576
 577         fman1_tx_0x2a: port@aa000 {
 578                 cell-index = <0x2a>;
 579                 compatible = "fsl,fman-v2-port-tx";
 580                 reg = <0xaa000 0x1000>;
 581         };
 582
 583         fman1_tx_0x2b: port@ab000 {
 584                 cell-index = <0x2b>;
 585                 compatible = "fsl,fman-v2-port-tx";
 586                 reg = <0xab000 0x1000>;
 587         };
 588
 589         fman1_tx_0x2c: port@ac0000 {
 590                 cell-index = <0x2c>;
 591                 compatible = "fsl,fman-v2-port-tx";
 592                 reg = <0xac000 0x1000>;
 593         };
 594
 595         fman1_tx_0x30: port@b0000 {
 596                 cell-index = <0x30>;
 597                 compatible = "fsl,fman-v2-port-tx";
 598                 reg = <0xb0000 0x1000>;
 599         };
 600
 601         ethernet@e0000 {
 602                 compatible = "fsl,fman-dtsec";
 603                 cell-index = <0>;
 604                 reg = <0xe0000 0x1000>;
 605                 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
 606                 tbi-handle = <&tbi5>;
 607         };
 608
 609         ethernet@e2000 {
 610                 compatible = "fsl,fman-dtsec";
 611                 cell-index = <1>;
 612                 reg = <0xe2000 0x1000>;
 613                 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
 614                 tbi-handle = <&tbi6>;
 615         };
 616
 617         ethernet@e4000 {
 618                 compatible = "fsl,fman-dtsec";
 619                 cell-index = <2>;
 620                 reg = <0xe4000 0x1000>;
 621                 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
 622                 tbi-handle = <&tbi7>;
 623         };
 624
 625         ethernet@e6000 {
 626                 compatible = "fsl,fman-dtsec";
 627                 cell-index = <3>;
 628                 reg = <0xe6000 0x1000>;
 629                 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
 630                 tbi-handle = <&tbi8>;
 631         };
 632
 633         ethernet@e8000 {
 634                 compatible = "fsl,fman-dtsec";
 635                 cell-index = <4>;
 636                 reg = <0xf0000 0x1000>;
 637                 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
 638                 tbi-handle = <&tbi9>;
 639
 640         ethernet@f0000 {
 641                 cell-index = <8>;
 642                 compatible = "fsl,fman-xgec";
 643                 reg = <0xf0000 0x1000>;
 644                 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
 645         };
 646
 647         ptp-timer@fe000 {
 648                 compatible = "fsl,fman-ptp-timer";
 649                 reg = <0xfe000 0x1000>;
 650         };
 651
 652         mdio@f1000 {
 653                 compatible = "fsl,fman-xmdio";
 654                 reg = <0xf1000 0x1000>;
 655                 interrupts = <101 2 0 0>;
 656         };
 657 };