Documentation/devicetree/bindings/serial/8250.txt

   1 * UART (Universal Asynchronous Receiver/Transmitter)
   2
   3 Required properties:
   4 - compatible : one of:
   5         - "ns8250"
   6         - "ns16450"
   7         - "ns16550a"
   8         - "ns16550"
   9         - "ns16750"
  10         - "ns16850"
  11         - For Tegra20, must contain "nvidia,tegra20-uart"
  12         - For other Tegra, must contain '"nvidia,<chip>-uart",
  13           "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
  14           tegra132, or tegra210.
  15         - "nxp,lpc3220-uart"
  16         - "ralink,rt2880-uart"
  17         - "altr,16550-FIFO32"
  18         - "altr,16550-FIFO64"
  19         - "altr,16550-FIFO128"
  20         - "fsl,16550-FIFO64"
  21         - "fsl,ns16550"
  22         - "serial" if the port type is unknown.
  23 - reg : offset and length of the register set for the device.
  24 - interrupts : should contain uart interrupt.
  25 - clock-frequency : the input clock frequency for the UART
  26          or
  27   clocks phandle to refer to the clk used as per Documentation/devicetree
  28   /bindings/clock/clock-bindings.txt
  29
  30 Optional properties:
  31 - current-speed : the current active speed of the UART.
  32 - reg-offset : offset to apply to the mapbase from the start of the registers.
  33 - reg-shift : quantity to shift the register offsets by.
  34 - reg-io-width : the size (in bytes) of the IO accesses that should be
  35   performed on the device.  There are some systems that require 32-bit
  36   accesses to the UART (e.g. TI davinci).
  37 - used-by-rtas : set to indicate that the port is in use by the OpenFirmware
  38   RTAS and should not be registered.
  39 - no-loopback-test: set to indicate that the port does not implements loopback
  40   test mode
  41 - fifo-size: the fifo size of the UART.
  42 - auto-flow-control: one way to enable automatic flow control support. The
  43   driver is allowed to detect support for the capability even without this
  44   property.
  45 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
  46   line respectively. It will use specified GPIO instead of the peripheral
  47   function pin for the UART feature. If unsure, don't specify this property.
  48
  49 Note:
  50 * fsl,ns16550:
  51   ------------
  52   Freescale DUART is very similar to the PC16552D (and to a
  53   pair of NS16550A), albeit with some nonstandard behavior such as
  54   erratum A-004737 (relating to incorrect BRK handling).
  55
  56   Represents a single port that is compatible with the DUART found
  57   on many Freescale chips (examples include mpc8349, mpc8548,
  58   mpc8641d, p4080 and ls2085a).
  59
  60 Example:
  61
  62         uart@80230000 {
  63                 compatible = "ns8250";
  64                 reg = <0x80230000 0x100>;
  65                 clock-frequency = <3686400>;
  66                 interrupts = <10>;
  67                 reg-shift = <2>;
  68         };
  69
  70 Example for OMAP UART using GPIO-based modem control signals:
  71
  72         uart4: serial@49042000 {
  73                 compatible = "ti,omap3-uart";
  74                 reg = <0x49042000 0x400>;
  75                 interrupts = <80>;
  76                 ti,hwmods = "uart4";
  77                 clock-frequency = <48000000>;
  78                 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
  79                 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
  80                 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  81                 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  82                 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  83                 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  84         };