Documentation/devicetree/bindings/sound/fsl,esai.txt

   1 Freescale Enhanced Serial Audio Interface (ESAI) Controller
   2
   3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
   4 for serial communication with a variety of serial devices, including industry
   5 standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
   6 other DSPs. It has up to six transmitters and four receivers.
   7
   8 Required properties:
   9
  10   - compatible          : Compatible list, must contain "fsl,imx35-esai" or
  11                           "fsl,vf610-esai"
  12
  13   - reg                 : Offset and length of the register set for the device.
  14
  15   - interrupts          : Contains the spdif interrupt.
  16
  17   - dmas                : Generic dma devicetree binding as described in
  18                           Documentation/devicetree/bindings/dma/dma.txt.
  19
  20   - dma-names           : Two dmas have to be defined, "tx" and "rx".
  21
  22   - clocks              : Contains an entry for each entry in clock-names.
  23
  24   - clock-names         : Includes the following entries:
  25         "core"            The core clock used to access registers
  26         "extal"           The esai baud clock for esai controller used to
  27                           derive HCK, SCK and FS.
  28         "fsys"            The system clock derived from ahb clock used to
  29                           derive HCK, SCK and FS.
  30         "spba"            The spba clock is required when ESAI is placed as a
  31                           bus slave of the Shared Peripheral Bus and when two
  32                           or more bus masters (CPU, DMA or DSP) try to access
  33                           it. This property is optional depending on the SoC
  34                           design.
  35
  36   - fsl,fifo-depth      : The number of elements in the transmit and receive
  37                           FIFOs. This number is the maximum allowed value for
  38                           TFCR[TFWM] or RFCR[RFWM].
  39
  40   - fsl,esai-synchronous: This is a boolean property. If present, indicating
  41                           that ESAI would work in the synchronous mode, which
  42                           means all the settings for Receiving would be
  43                           duplicated from Transmition related registers.
  44
  45   - big-endian          : If this property is absent, the native endian mode
  46                           will be in use as default, or the big endian mode
  47                           will be in use for all the device registers.
  48
  49 Example:
  50
  51 esai: esai@02024000 {
  52         compatible = "fsl,imx35-esai";
  53         reg = <0x02024000 0x4000>;
  54         interrupts = <0 51 0x04>;
  55         clocks = <&clks 208>, <&clks 118>, <&clks 208>;
  56         clock-names = "core", "extal", "fsys";
  57         dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
  58         dma-names = "rx", "tx";
  59         fsl,fifo-depth = <128>;
  60         fsl,esai-synchronous;
  61         big-endian;
  62         status = "disabled";
  63 };