Documentation/devicetree/bindings/spi/qcom,spi-qup.txt

   1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
   2
   3 The QUP core is an AHB slave that provides a common data path (an output FIFO
   4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
   5
   6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
   7 data path from 4 bits to 32 bits and numerous protocol variants.
   8
   9 Required properties:
  10 - compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
  11 - reg:            Should contain base register location and length
  12 - interrupts:     Interrupt number used by this controller
  13
  14 - clocks:         Should contain the core clock and the AHB clock.
  15 - clock-names:    Should be "core" for the core clock and "iface" for the
  16                   AHB clock.
  17
  18 - #address-cells: Number of cells required to define a chip select
  19                   address on the SPI bus. Should be set to 1.
  20 - #size-cells:    Should be zero.
  21
  22 Optional properties:
  23 - spi-max-frequency: Specifies maximum SPI clock frequency,
  24                      Units - Hz. Definition as per
  25                      Documentation/devicetree/bindings/spi/spi-bus.txt
  26
  27 SPI slave nodes must be children of the SPI master node and can contain
  28 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
  29
  30 Example:
  31
  32         spi_8: spi@f9964000 { /* BLSP2 QUP2 */
  33
  34                 compatible = "qcom,spi-qup-v2";
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37                 reg = <0xf9964000 0x1000>;
  38                 interrupts = <0 102 0>;
  39                 spi-max-frequency = <19200000>;
  40
  41                 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  42                 clock-names = "core", "iface";
  43
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&spi8_default>;
  46
  47                 device@0 {
  48                         compatible = "arm,pl022-dummy";
  49                         #address-cells = <1>;
  50                         #size-cells = <1>;
  51                         reg = <0>; /* Chip select 0 */
  52                         spi-max-frequency = <19200000>;
  53                         spi-cpol;
  54                 };
  55
  56                 device@1 {
  57                         compatible = "arm,pl022-dummy";
  58                         #address-cells = <1>;
  59                         #size-cells = <1>;
  60                         reg = <1>; /* Chip select 1 */
  61                         spi-max-frequency = <9600000>;
  62                         spi-cpha;
  63                 };
  64
  65                 device@2 {
  66                         compatible = "arm,pl022-dummy";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         reg = <2>; /* Chip select 2 */
  70                         spi-max-frequency = <19200000>;
  71                         spi-cpol;
  72                         spi-cpha;
  73                 };
  74
  75                 device@3 {
  76                         compatible = "arm,pl022-dummy";
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79                         reg = <3>; /* Chip select 3 */
  80                         spi-max-frequency = <19200000>;
  81                         spi-cpol;
  82                         spi-cpha;
  83                         spi-cs-high;
  84                 };
  85         };