Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt

   1 Allwinner SoCs High Speed Timer Controller
   2
   3 Required properties:
   4
   5 - compatible :  should be "allwinner,sun5i-a13-hstimer" or
   6                 "allwinner,sun7i-a20-hstimer"
   7 - reg : Specifies base physical address and size of the registers.
   8 - interrupts :  The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
   9                 one)
  10 - clocks: phandle to the source clock (usually the AHB clock)
  11
  12 Optionnal properties:
  13 - resets: phandle to a reset controller asserting the timer
  14
  15 Example:
  16
  17 timer@01c60000 {
  18         compatible = "allwinner,sun7i-a20-hstimer";
  19         reg = <0x01c60000 0x1000>;
  20         interrupts = <0 51 1>,
  21                      <0 52 1>,
  22                      <0 53 1>,
  23                      <0 54 1>;
  24         clocks = <&ahb1_gates 19>;
  25         resets = <&ahb1rst 19>;
  26 };