Documentation/sound/alsa/soc/DAI.txt

   1 ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
   2 SoC controllers and portable audio CODECS today, namely AC97, I2S and PCM.
   3
   4
   5 AC97
   6 ====
   7
   8   AC97 is a five wire interface commonly found on many PC sound cards. It is
   9 now also popular in many portable devices. This DAI has a reset line and time
  10 multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
  11 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
  12 frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
  13 frame is 21uS long and is divided into 13 time slots.
  14
  15 The AC97 specification can be found at http://intel.com/
  16
  17
  18 I2S
  19 ===
  20
  21  I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
  22 Rx lines are used for audio transmision, whilst the bit clock (BCLK) and
  23 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
  24 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
  25 usually varies depending on the sample rate and the master system clock
  26 (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
  27 ADC and DAC LRCLK's, this allows for similtanious capture and playback at
  28 different sample rates.
  29
  30 I2S has several different operating modes:-
  31
  32  o I2S - MSB is transmitted on the falling edge of the first BCLK after LRC
  33          transition.
  34
  35  o Left Justified - MSB is transmitted on transition of LRC.
  36
  37  o Right Justified - MSB is transmitted sample size BCLK's before LRC
  38                      transition.
  39
  40 PCM
  41 ===
  42
  43 PCM is another 4 wire interface, very similar to I2S, that can support a more
  44 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
  45 to synchronise the link whilst the Tx and Rx lines are used to transmit and
  46 receive the audio data. Bit clock usually varies depending on sample rate
  47 whilst sync runs at the sample rate. PCM also supports Time Division
  48 Multiplexing (TDM) in that several devices can use the bus similtaniuosly (This
  49 is sometimes referred to as network mode).
  50
  51 Common PCM operating modes:-
  52
  53  o Mode A - MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
  54
  55  o Mode B - MSB is transmitted on rising edge of FRAME/SYNC.
  56
  57
  58 ASoC DAI Configuration
  59 ======================
  60
  61 Every CODEC DAI and SoC DAI must have their capabilities defined in order to
  62 be configured together at runtime when the audio and clocking parameters are
  63 known. This is achieved by creating an array of struct snd_soc_hw_mode in the
  64 the CODEC and SoC interface drivers. Each element in the array describes a DAI
  65 mode and each mode is usually based upon the DAI system clock to sample rate
  66 ratio (FS).
  67
  68 i.e. 48k sample rate @ 256 FS = sytem clock of 12.288 MHz
  69      48000 * 256 = 12288000
  70
  71 The CPU and Codec DAI modes are then ANDed together at runtime to determine the
  72 rutime DAI configuration for both the Codec and CPU.
  73
  74 When creating a new codec or SoC DAI it's probably best to start of with a few
  75 sample rates first and then test your interface.
  76
  77 struct snd_soc_dai_mode is defined (in soc.h) as:-
  78
  79 /* SoC DAI mode */
  80 struct snd_soc_hw_mode {
  81         unsigned int fmt:16;            /* SND_SOC_DAIFMT_* */
  82         unsigned int tdm:16;            /* SND_SOC_DAITDM_* */
  83         unsigned int pcmfmt:6;          /* SNDRV_PCM_FORMAT_* */
  84         unsigned int pcmrate:16;        /* SND_SOC_DAIRATE_* */
  85         unsigned int pcmdir:2;          /* SND_SOC_DAIDIR_* */
  86         unsigned int flags:8;           /* hw flags */
  87         unsigned int fs:32;                     /* mclk to rate dividers */
  88         unsigned int bfs:16;            /* mclk to bclk dividers */
  89         unsigned long priv;             /* private mode data */
  90 };
  91
  92 fmt:
  93 ----
  94 This field defines the DAI mode hardware format (e.g. I2S settings) and
  95 supports the following settings:-
  96
  97  1) hardware DAI formats
  98
  99 #define SND_SOC_DAIFMT_I2S        (1 << 0)      /* I2S mode */
 100 #define SND_SOC_DAIFMT_RIGHT_J    (1 << 1)      /* Right justified mode */
 101 #define SND_SOC_DAIFMT_LEFT_J     (1 << 2)      /* Left Justified mode */
 102 #define SND_SOC_DAIFMT_DSP_A      (1 << 3)      /* L data msb after FRM */
 103 #define SND_SOC_DAIFMT_DSP_B      (1 << 4)      /* L data msb during FRM */
 104 #define SND_SOC_DAIFMT_AC97       (1 << 5)      /* AC97 */
 105
 106  2) hw DAI signal inversions
 107
 108 #define SND_SOC_DAIFMT_NB_NF            (1 << 8)        /* normal bit clock + frame */
 109 #define SND_SOC_DAIFMT_NB_IF            (1 << 9)        /* normal bclk + inv frm */
 110 #define SND_SOC_DAIFMT_IB_NF            (1 << 10)       /* invert bclk + nor frm */
 111 #define SND_SOC_DAIFMT_IB_IF            (1 << 11)       /* invert bclk + frm */
 112
 113  3) hw clock masters
 114     This is wrt the codec, the inverse is true for the interface
 115     i.e. if the codec is clk and frm master then the interface is
 116     clk and frame slave.
 117
 118 #define SND_SOC_DAIFMT_CBM_CFM          (1 << 12)       /* codec clk & frm master */
 119 #define SND_SOC_DAIFMT_CBS_CFM          (1 << 13)       /* codec clk slave & frm master */
 120 #define SND_SOC_DAIFMT_CBM_CFS          (1 << 14)       /* codec clk master & frame slave */
 121 #define SND_SOC_DAIFMT_CBS_CFS          (1 << 15)       /* codec clk & frm slave */
 122
 123 At least one option from each section must be selected. Multiple selections are
 124 also supported e.g.
 125
 126  .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_RIGHT_J | \
 127         SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_IB_NF | \
 128         SND_SOC_DAIFMT_IB_IF
 129
 130
 131 tdm:
 132 ------
 133 This field defines the Time Division Multiplexing left and right word
 134 positions for the DAI mode if applicable. Set to SND_SOC_DAITDM_LRDW(0,0) for
 135 no TDM.
 136
 137
 138 pcmfmt:
 139 ---------
 140 The hardware PCM format. This describes the PCM formats supported by the DAI
 141 mode e.g.
 142
 143  .hwpcmfmt = SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
 144         SNDRV_PCM_FORMAT_S24_3LE
 145
 146 pcmrate:
 147 ----------
 148 The PCM sample rates supported by the DAI mode. e.g.
 149
 150  .hwpcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
 151         SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
 152         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000
 153
 154
 155 pcmdir:
 156 ---------
 157 The stream directions supported by this mode. e.g. playback and capture
 158
 159
 160 flags:
 161 --------
 162 The DAI hardware flags supported by the mode.
 163
 164 SND_SOC_DAI_BFS_DIV
 165 This flag states that bit clock is generated by dividing MCLK in this mode, if
 166 this flag is absent the bitclock generated by mulitiplying sample rate.
 167
 168 NOTE: Bitclock division and mulitiplication modes can be safely matched by the
 169 core logic.
 170
 171
 172 fs:
 173 -----
 174 The FS supported by this DAI mode FS is the ratio between the system clock and
 175 the sample rate. See above
 176
 177 bfs:
 178 ------
 179 BFS is the ratio of BCLK to MCLK or the ratio of BCLK to sample rate (this
 180 depends on the codec or CPU DAI).
 181
 182 The BFS supported by the DAI mode. This can either be the ratio between the
 183 bitclock (BCLK) and the sample rate OR the ratio between the system clock and
 184 the sample rate. Depends on the SND_SOC_DAI_BFS_DIV flag above.
 185
 186 priv:
 187 -----
 188 private codec mode data.
 189
 190
 191
 192 Examples
 193 ========
 194
 195 Note that Codec DAI and CPU DAI examples are interchangeable in these examples
 196 as long as the bus master is reversed. i.e.
 197
 198   SND_SOC_DAIFMT_CBM_CFM would become SND_SOC_DAIFMT_CBS_CFS
 199   and vice versa.
 200
 201 This applies to all SND_SOC_DAIFMT_CB*_CF*.
 202
 203 Example 1
 204 ---------
 205
 206 Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
 207 BCLK of either MCLK/2 or MCLK/4.
 208
 209         /* codec master */
 210         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 211         SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
 212         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
 213         256, SND_SOC_FSBD(2) | SND_SOC_FSBD(4)},
 214
 215
 216 Example 2
 217 ---------
 218 Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
 219 BCLK of either Rate * 32 or Rate * 64.
 220
 221         /* codec master */
 222         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 223         SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
 224         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
 225         256, SND_SOC_FSB(32) | SND_SOC_FSB(64)},
 226
 227
 228 Example 3
 229 ---------
 230 Codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
 231 BCLK of either Rate * 32 or Rate * 64. Codec can also run in slave mode as long
 232 as BCLK is rate * 32 or rate * 64.
 233
 234         /* codec master */
 235         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 236         SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
 237         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
 238         256, SND_SOC_FSB(32) | SND_SOC_FSB(64)},
 239
 240         /* codec slave */
 241         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
 242         SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
 243         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
 244         SND_SOC_FS_ALL, SND_SOC_FSB(32) | SND_SOC_FSB(64)},
 245
 246
 247 Example 4
 248 ---------
 249 Codec that only runs at 8k, 16k, 32k, 48k, 96k @ 128FS, 192FS & 256FS in master
 250 mode and can generate a BCLK of MCLK / (1,2,4,8,16). Codec can also run in slave
 251 mode as and does not care about FS or BCLK (as long as there is enough bandwidth).
 252
 253         #define CODEC_FSB \
 254         (SND_SOC_FSBD(1) | SND_SOC_FSBD(2) | SND_SOC_FSBD(4) | \
 255         SND_SOC_FSBD(8) | SND_SOC_FSBD(16))
 256
 257         #define CODEC_RATES \
 258         (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
 259          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
 260
 261         /* codec master @ 128, 192 & 256 FS */
 262         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 263         SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
 264         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
 265         128, CODEC_FSB},
 266
 267         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 268         SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
 269         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
 270         192, CODEC_FSB},
 271
 272         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 273         SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
 274         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
 275         256, CODEC_FSB},
 276
 277         /* codec slave */
 278         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
 279         SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
 280         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
 281         SND_SOC_FS_ALL, SND_SOC_FSB_ALL},
 282
 283
 284 Example 5
 285 ---------
 286 Codec that only runs at 8k, 44.1k, 48k @ different FS in master mode (for use
 287 with a fixed MCLK) and can generate a BCLK of MCLK / (1,2,4,8,16).
 288 Codec can also run in slave mode as and does not care about FS or BCLK (as long
 289 as there is enough bandwidth). Codec can support 16, 24 and 32 bit PCM sample
 290 sizes.
 291
 292         #define CODEC_FSB \
 293         (SND_SOC_FSBD(1) | SND_SOC_FSBD(2) | SND_SOC_FSBD(4) | \
 294         SND_SOC_FSBD(8) | SND_SOC_FSBD(16))
 295
 296         #define CODEC_PCM_FORMATS \
 297         (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
 298         SNDRV_PCM_FORMAT_S24_3LE | SNDRV_PCM_FORMAT_S24_LE | SNDRV_PCM_FORMAT_S32_LE)
 299
 300         /* codec master */
 301         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 302         SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000,
 303         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
 304         1536, CODEC_FSB},
 305
 306         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 307         SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_44100,
 308         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
 309         272, CODEC_FSB},
 310
 311         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
 312         SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_48000,
 313         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
 314         256, CODEC_FSB},
 315
 316         /* codec slave */
 317         {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
 318         SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
 319         SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
 320         SND_SOC_FS_ALL, SND_SOC_FSB_ALL},
 321
 322
 323 Example 6
 324 ---------
 325 AC97 Codec that does not support VRA (i.e only runs at 48k).
 326
 327         #define AC97_DIR \
 328         (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
 329
 330
 331         #define AC97_PCM_FORMATS \
 332         (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S18_3LE | \
 333         SNDRV_PCM_FORMAT_S20_3LE)
 334
 335         /* AC97 with no VRA */
 336         {0, 0,  AC97_PCM_FORMATS,       SNDRV_PCM_RATE_48000},
 337
 338
 339 Example 7
 340 ---------
 341
 342 CPU DAI that supports 8k - 48k @ 256FS and BCLK = MCLK / 4 in master mode.
 343 Slave mode (CPU DAI is FRAME master) supports 8k - 96k at any FS as long as
 344 BCLK = 64 * rate. (Intel XScale I2S controller).
 345
 346         #define PXA_I2S_DAIFMT \
 347         (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF)
 348
 349         #define PXA_I2S_DIR \
 350         (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
 351
 352         #define PXA_I2S_RATES \
 353         (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
 354         SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
 355         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
 356
 357         /* pxa2xx I2S frame and clock master modes */
 358         {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
 359                 SNDRV_PCM_RATE_8000, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
 360                 SND_SOC_FSBD(4), 0x48},
 361         {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
 362                 SNDRV_PCM_RATE_11025, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
 363                 SND_SOC_FSBD(4), 0x34},
 364         {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
 365                 SNDRV_PCM_RATE_16000, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
 366                 SND_SOC_FSBD(4), 0x24},
 367         {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
 368                 SNDRV_PCM_RATE_22050, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
 369                 SND_SOC_FSBD(4), 0x1a},
 370         {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
 371                 SNDRV_PCM_RATE_44100, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
 372                 SND_SOC_FSBD(4), 0xd},
 373         {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
 374                 SNDRV_PCM_RATE_48000, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
 375                 SND_SOC_FSBD(4), 0xc},
 376
 377         /* pxa2xx I2S frame master and clock slave mode */
 378         {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBM_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
 379                 PXA_I2S_RATES, PXA_I2S_DIR, 0, SND_SOC_FS_ALL, SND_SOC_FSB(64)},
 380