arch/alpha/kernel/pci.c

   1 /*
   2  *      linux/arch/alpha/kernel/pci.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  */
   8
   9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
  10
  11 /*
  12  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  13  *           PCI-PCI bridges cleanup
  14  */
  15 #include <linux/string.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/module.h>
  22 #include <linux/cache.h>
  23 #include <linux/slab.h>
  24 #include <asm/machvec.h>
  25
  26 #include "proto.h"
  27 #include "pci_impl.h"
  28
  29
  30 /*
  31  * Some string constants used by the various core logics.
  32  */
  33
  34 const char *const pci_io_names[] = {
  35   "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
  36   "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
  37 };
  38
  39 const char *const pci_mem_names[] = {
  40   "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
  41   "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
  42 };
  43
  44 const char pci_hae0_name[] = "HAE0";
  45
  46 /* Indicate whether we respect the PCI setup left by console. */
  47 /*
  48  * Make this long-lived  so that we know when shutting down
  49  * whether we probed only or not.
  50  */
  51 int pci_probe_only;
  52
  53 /*
  54  * The PCI controller list.
  55  */
  56
  57 struct pci_controller *hose_head, **hose_tail = &hose_head;
  58 struct pci_controller *pci_isa_hose;
  59
  60 /*
  61  * Quirks.
  62  */
  63
  64 static void __init
  65 quirk_isa_bridge(struct pci_dev *dev)
  66 {
  67         dev->class = PCI_CLASS_BRIDGE_ISA << 8;
  68 }
  69 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
  70
  71 static void __init
  72 quirk_cypress(struct pci_dev *dev)
  73 {
  74         /* The Cypress bridge responds on the PCI bus in the address range
  75            0xffff0000-0xffffffff (conventional x86 BIOS ROM).  There is no
  76            way to turn this off.  The bridge also supports several extended
  77            BIOS ranges (disabled after power-up), and some consoles do turn
  78            them on.  So if we use a large direct-map window, or a large SG
  79            window, we must avoid the entire 0xfff00000-0xffffffff region.  */
  80         if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
  81                 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
  82                         __direct_map_size = 0xfff00000UL - __direct_map_base;
  83                 else {
  84                         struct pci_controller *hose = dev->sysdata;
  85                         struct pci_iommu_arena *pci = hose->sg_pci;
  86                         if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
  87                                 pci->size = 0xfff00000UL - pci->dma_base;
  88                 }
  89         }
  90 }
  91 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
  92
  93 /* Called for each device after PCI setup is done. */
  94 static void __init
  95 pcibios_fixup_final(struct pci_dev *dev)
  96 {
  97         unsigned int class = dev->class >> 8;
  98
  99         if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
 100                 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
 101                 isa_bridge = dev;
 102         }
 103 }
 104 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
 105
 106 /* Just declaring that the power-of-ten prefixes are actually the
 107    power-of-two ones doesn't make it true :) */
 108 #define KB                      1024
 109 #define MB                      (1024*KB)
 110 #define GB                      (1024*MB)
 111
 112 void
 113 pcibios_align_resource(void *data, struct resource *res,
 114                        resource_size_t size, resource_size_t align)
 115 {
 116         struct pci_dev *dev = data;
 117         struct pci_controller *hose = dev->sysdata;
 118         unsigned long alignto;
 119         resource_size_t start = res->start;
 120
 121         if (res->flags & IORESOURCE_IO) {
 122                 /* Make sure we start at our min on all hoses */
 123                 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
 124                         start = PCIBIOS_MIN_IO + hose->io_space->start;
 125
 126                 /*
 127                  * Put everything into 0x00-0xff region modulo 0x400
 128                  */
 129                 if (start & 0x300)
 130                         start = (start + 0x3ff) & ~0x3ff;
 131         }
 132         else if (res->flags & IORESOURCE_MEM) {
 133                 /* Make sure we start at our min on all hoses */
 134                 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
 135                         start = PCIBIOS_MIN_MEM + hose->mem_space->start;
 136
 137                 /*
 138                  * The following holds at least for the Low Cost
 139                  * Alpha implementation of the PCI interface:
 140                  *
 141                  * In sparse memory address space, the first
 142                  * octant (16MB) of every 128MB segment is
 143                  * aliased to the very first 16 MB of the
 144                  * address space (i.e., it aliases the ISA
 145                  * memory address space).  Thus, we try to
 146                  * avoid allocating PCI devices in that range.
 147                  * Can be allocated in 2nd-7th octant only.
 148                  * Devices that need more than 112MB of
 149                  * address space must be accessed through
 150                  * dense memory space only!
 151                  */
 152
 153                 /* Align to multiple of size of minimum base.  */
 154                 alignto = max(0x1000UL, align);
 155                 start = ALIGN(start, alignto);
 156                 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
 157                         if (((start / (16*MB)) & 0x7) == 0) {
 158                                 start &= ~(128*MB - 1);
 159                                 start += 16*MB;
 160                                 start  = ALIGN(start, alignto);
 161                         }
 162                         if (start/(128*MB) != (start + size - 1)/(128*MB)) {
 163                                 start &= ~(128*MB - 1);
 164                                 start += (128 + 16)*MB;
 165                                 start  = ALIGN(start, alignto);
 166                         }
 167                 }
 168         }
 169
 170         res->start = start;
 171 }
 172 #undef KB
 173 #undef MB
 174 #undef GB
 175
 176 static int __init
 177 pcibios_init(void)
 178 {
 179         if (alpha_mv.init_pci)
 180                 alpha_mv.init_pci();
 181         return 0;
 182 }
 183
 184 subsys_initcall(pcibios_init);
 185
 186 char * __devinit
 187 pcibios_setup(char *str)
 188 {
 189         return str;
 190 }
 191
 192 #ifdef ALPHA_RESTORE_SRM_SETUP
 193 static struct pdev_srm_saved_conf *srm_saved_configs;
 194
 195 void __devinit
 196 pdev_save_srm_config(struct pci_dev *dev)
 197 {
 198         struct pdev_srm_saved_conf *tmp;
 199         static int printed = 0;
 200
 201         if (!alpha_using_srm || pci_probe_only)
 202                 return;
 203
 204         if (!printed) {
 205                 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
 206                 printed = 1;
 207         }
 208
 209         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
 210         if (!tmp) {
 211                 printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
 212                 return;
 213         }
 214         tmp->next = srm_saved_configs;
 215         tmp->dev = dev;
 216
 217         pci_save_state(dev);
 218
 219         srm_saved_configs = tmp;
 220 }
 221
 222 void
 223 pci_restore_srm_config(void)
 224 {
 225         struct pdev_srm_saved_conf *tmp;
 226
 227         /* No need to restore if probed only. */
 228         if (pci_probe_only)
 229                 return;
 230
 231         /* Restore SRM config. */
 232         for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
 233                 pci_restore_state(tmp->dev);
 234         }
 235 }
 236 #endif
 237
 238 void __devinit
 239 pcibios_fixup_resource(struct resource *res, struct resource *root)
 240 {
 241         res->start += root->start;
 242         res->end += root->start;
 243 }
 244
 245 void __devinit
 246 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
 247 {
 248         /* Update device resources.  */
 249         struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
 250         int i;
 251
 252         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 253                 if (!dev->resource[i].start)
 254                         continue;
 255                 if (dev->resource[i].flags & IORESOURCE_IO)
 256                         pcibios_fixup_resource(&dev->resource[i],
 257                                                hose->io_space);
 258                 else if (dev->resource[i].flags & IORESOURCE_MEM)
 259                         pcibios_fixup_resource(&dev->resource[i],
 260                                                hose->mem_space);
 261         }
 262 }
 263
 264 void __devinit
 265 pcibios_fixup_bus(struct pci_bus *bus)
 266 {
 267         /* Propagate hose info into the subordinate devices.  */
 268
 269         struct pci_controller *hose = bus->sysdata;
 270         struct pci_dev *dev = bus->self;
 271
 272         if (!dev) {
 273                 /* Root bus. */
 274                 u32 pci_mem_end;
 275                 u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
 276                 unsigned long end;
 277
 278                 bus->resource[0] = hose->io_space;
 279                 bus->resource[1] = hose->mem_space;
 280
 281                 /* Adjust hose mem_space limit to prevent PCI allocations
 282                    in the iommu windows. */
 283                 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
 284                 end = hose->mem_space->start + pci_mem_end;
 285                 if (hose->mem_space->end > end)
 286                         hose->mem_space->end = end;
 287         } else if (pci_probe_only &&
 288                    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 289                 pci_read_bridge_bases(bus);
 290                 pcibios_fixup_device_resources(dev, bus);
 291         }
 292
 293         list_for_each_entry(dev, &bus->devices, bus_list) {
 294                 pdev_save_srm_config(dev);
 295                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 296                         pcibios_fixup_device_resources(dev, bus);
 297         }
 298 }
 299
 300 void __init
 301 pcibios_update_irq(struct pci_dev *dev, int irq)
 302 {
 303         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 304 }
 305
 306 /* Most Alphas have straight-forward swizzling needs.  */
 307
 308 u8 __init
 309 common_swizzle(struct pci_dev *dev, u8 *pinp)
 310 {
 311         u8 pin = *pinp;
 312
 313         while (dev->bus->parent) {
 314                 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
 315                 /* Move up the chain of bridges. */
 316                 dev = dev->bus->self;
 317         }
 318         *pinp = pin;
 319
 320         /* The slot is the slot of the last bridge. */
 321         return PCI_SLOT(dev->devfn);
 322 }
 323
 324 void __devinit
 325 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 326                          struct resource *res)
 327 {
 328         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 329         unsigned long offset = 0;
 330
 331         if (res->flags & IORESOURCE_IO)
 332                 offset = hose->io_space->start;
 333         else if (res->flags & IORESOURCE_MEM)
 334                 offset = hose->mem_space->start;
 335
 336         region->start = res->start - offset;
 337         region->end = res->end - offset;
 338 }
 339
 340 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 341                              struct pci_bus_region *region)
 342 {
 343         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 344         unsigned long offset = 0;
 345
 346         if (res->flags & IORESOURCE_IO)
 347                 offset = hose->io_space->start;
 348         else if (res->flags & IORESOURCE_MEM)
 349                 offset = hose->mem_space->start;
 350
 351         res->start = region->start + offset;
 352         res->end = region->end + offset;
 353 }
 354
 355 #ifdef CONFIG_HOTPLUG
 356 EXPORT_SYMBOL(pcibios_resource_to_bus);
 357 EXPORT_SYMBOL(pcibios_bus_to_resource);
 358 #endif
 359
 360 int
 361 pcibios_enable_device(struct pci_dev *dev, int mask)
 362 {
 363         return pci_enable_resources(dev, mask);
 364 }
 365
 366 /*
 367  *  If we set up a device for bus mastering, we need to check the latency
 368  *  timer as certain firmware forgets to set it properly, as seen
 369  *  on SX164 and LX164 with SRM.
 370  */
 371 void
 372 pcibios_set_master(struct pci_dev *dev)
 373 {
 374         u8 lat;
 375         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 376         if (lat >= 16) return;
 377         printk("PCI: Setting latency timer of device %s to 64\n",
 378                                                         pci_name(dev));
 379         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 380 }
 381
 382 void __init
 383 pcibios_claim_one_bus(struct pci_bus *b)
 384 {
 385         struct pci_dev *dev;
 386         struct pci_bus *child_bus;
 387
 388         list_for_each_entry(dev, &b->devices, bus_list) {
 389                 int i;
 390
 391                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 392                         struct resource *r = &dev->resource[i];
 393
 394                         if (r->parent || !r->start || !r->flags)
 395                                 continue;
 396                         if (pci_probe_only || (r->flags & IORESOURCE_PCI_FIXED))
 397                                 pci_claim_resource(dev, i);
 398                 }
 399         }
 400
 401         list_for_each_entry(child_bus, &b->children, node)
 402                 pcibios_claim_one_bus(child_bus);
 403 }
 404
 405 static void __init
 406 pcibios_claim_console_setup(void)
 407 {
 408         struct pci_bus *b;
 409
 410         list_for_each_entry(b, &pci_root_buses, node)
 411                 pcibios_claim_one_bus(b);
 412 }
 413
 414 void __init
 415 common_init_pci(void)
 416 {
 417         struct pci_controller *hose;
 418         struct pci_bus *bus;
 419         int next_busno;
 420         int need_domain_info = 0;
 421
 422         /* Scan all of the recorded PCI controllers.  */
 423         for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
 424                 bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
 425                 hose->bus = bus;
 426                 hose->need_domain_info = need_domain_info;
 427                 next_busno = bus->subordinate + 1;
 428                 /* Don't allow 8-bit bus number overflow inside the hose -
 429                    reserve some space for bridges. */
 430                 if (next_busno > 224) {
 431                         next_busno = 0;
 432                         need_domain_info = 1;
 433                 }
 434         }
 435
 436         pcibios_claim_console_setup();
 437
 438         pci_assign_unassigned_resources();
 439         pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
 440 }
 441
 442
 443 struct pci_controller * __init
 444 alloc_pci_controller(void)
 445 {
 446         struct pci_controller *hose;
 447
 448         hose = alloc_bootmem(sizeof(*hose));
 449
 450         *hose_tail = hose;
 451         hose_tail = &hose->next;
 452
 453         return hose;
 454 }
 455
 456 struct resource * __init
 457 alloc_resource(void)
 458 {
 459         struct resource *res;
 460
 461         res = alloc_bootmem(sizeof(*res));
 462
 463         return res;
 464 }
 465
 466
 467 /* Provide information on locations of various I/O regions in physical
 468    memory.  Do this on a per-card basis so that we choose the right hose.  */
 469
 470 asmlinkage long
 471 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
 472 {
 473         struct pci_controller *hose;
 474         struct pci_dev *dev;
 475
 476         /* from hose or from bus.devfn */
 477         if (which & IOBASE_FROM_HOSE) {
 478                 for(hose = hose_head; hose; hose = hose->next)
 479                         if (hose->index == bus) break;
 480                 if (!hose) return -ENODEV;
 481         } else {
 482                 /* Special hook for ISA access.  */
 483                 if (bus == 0 && dfn == 0) {
 484                         hose = pci_isa_hose;
 485                 } else {
 486                         dev = pci_get_bus_and_slot(bus, dfn);
 487                         if (!dev)
 488                                 return -ENODEV;
 489                         hose = dev->sysdata;
 490                         pci_dev_put(dev);
 491                 }
 492         }
 493
 494         switch (which & ~IOBASE_FROM_HOSE) {
 495         case IOBASE_HOSE:
 496                 return hose->index;
 497         case IOBASE_SPARSE_MEM:
 498                 return hose->sparse_mem_base;
 499         case IOBASE_DENSE_MEM:
 500                 return hose->dense_mem_base;
 501         case IOBASE_SPARSE_IO:
 502                 return hose->sparse_io_base;
 503         case IOBASE_DENSE_IO:
 504                 return hose->dense_io_base;
 505         case IOBASE_ROOT_BUS:
 506                 return hose->bus->number;
 507         }
 508
 509         return -EOPNOTSUPP;
 510 }
 511
 512 /* Create an __iomem token from a PCI BAR.  Copied from lib/iomap.c with
 513    no changes, since we don't want the other things in that object file.  */
 514
 515 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
 516 {
 517         resource_size_t start = pci_resource_start(dev, bar);
 518         resource_size_t len = pci_resource_len(dev, bar);
 519         unsigned long flags = pci_resource_flags(dev, bar);
 520
 521         if (!len || !start)
 522                 return NULL;
 523         if (maxlen && len > maxlen)
 524                 len = maxlen;
 525         if (flags & IORESOURCE_IO)
 526                 return ioport_map(start, len);
 527         if (flags & IORESOURCE_MEM) {
 528                 /* Not checking IORESOURCE_CACHEABLE because alpha does
 529                    not distinguish between ioremap and ioremap_nocache.  */
 530                 return ioremap(start, len);
 531         }
 532         return NULL;
 533 }
 534
 535 /* Destroy that token.  Not copied from lib/iomap.c.  */
 536
 537 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
 538 {
 539         if (__is_mmio(addr))
 540                 iounmap(addr);
 541 }
 542
 543 EXPORT_SYMBOL(pci_iomap);
 544 EXPORT_SYMBOL(pci_iounmap);
 545
 546 /* FIXME: Some boxes have multiple ISA bridges! */
 547 struct pci_dev *isa_bridge;
 548 EXPORT_SYMBOL(isa_bridge);