arch/alpha/kernel/sys_sio.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_sio.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code for all boards that route the PCI interrupts through the SIO
   9  * PCI/ISA bridge.  This includes Noname (AXPpci33), Multia (UDB),
  10  * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/mm.h>
  16 #include <linux/sched.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/screen_info.h>
  20
  21 #include <asm/compiler.h>
  22 #include <asm/ptrace.h>
  23 #include <asm/system.h>
  24 #include <asm/dma.h>
  25 #include <asm/irq.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/io.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/core_apecs.h>
  30 #include <asm/core_lca.h>
  31 #include <asm/tlbflush.h>
  32
  33 #include "proto.h"
  34 #include "irq_impl.h"
  35 #include "pci_impl.h"
  36 #include "machvec_impl.h"
  37
  38 #if defined(ALPHA_RESTORE_SRM_SETUP)
  39 /* Save LCA configuration data as the console had it set up.  */
  40 struct
  41 {
  42         unsigned int orig_route_tab; /* for SAVE/RESTORE */
  43 } saved_config __attribute((common));
  44 #endif
  45
  46
  47 static void __init
  48 sio_init_irq(void)
  49 {
  50         if (alpha_using_srm)
  51                 alpha_mv.device_interrupt = srm_device_interrupt;
  52
  53         init_i8259a_irqs();
  54         common_init_isa_dma();
  55 }
  56
  57 static inline void __init
  58 alphabook1_init_arch(void)
  59 {
  60         /* The AlphaBook1 has LCD video fixed at 800x600,
  61            37 rows and 100 cols. */
  62         screen_info.orig_y = 37;
  63         screen_info.orig_video_cols = 100;
  64         screen_info.orig_video_lines = 37;
  65
  66         lca_init_arch();
  67 }
  68
  69
  70 /*
  71  * sio_route_tab selects irq routing in PCI/ISA bridge so that:
  72  *              PIRQ0 -> irq 15
  73  *              PIRQ1 -> irq  9
  74  *              PIRQ2 -> irq 10
  75  *              PIRQ3 -> irq 11
  76  *
  77  * This probably ought to be configurable via MILO.  For
  78  * example, sound boards seem to like using IRQ 9.
  79  *
  80  * This is NOT how we should do it. PIRQ0-X should have
  81  * their own IRQ's, the way intel uses the IO-APIC irq's.
  82  */
  83
  84 static void __init
  85 sio_pci_route(void)
  86 {
  87 #if defined(ALPHA_RESTORE_SRM_SETUP)
  88         /* First, read and save the original setting. */
  89         pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
  90                                   &saved_config.orig_route_tab);
  91         printk("%s: PIRQ original 0x%x new 0x%x\n", __FUNCTION__,
  92                saved_config.orig_route_tab, alpha_mv.sys.sio.route_tab);
  93 #endif
  94
  95         /* Now override with desired setting. */
  96         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
  97                                    alpha_mv.sys.sio.route_tab);
  98 }
  99
 100 static unsigned int __init
 101 sio_collect_irq_levels(void)
 102 {
 103         unsigned int level_bits = 0;
 104         struct pci_dev *dev = NULL;
 105
 106         /* Iterate through the devices, collecting IRQ levels.  */
 107         for_each_pci_dev(dev) {
 108                 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
 109                     (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
 110                         continue;
 111
 112                 if (dev->irq)
 113                         level_bits |= (1 << dev->irq);
 114         }
 115         return level_bits;
 116 }
 117
 118 static void __init
 119 sio_fixup_irq_levels(unsigned int level_bits)
 120 {
 121         unsigned int old_level_bits;
 122
 123         /*
 124          * Now, make all PCI interrupts level sensitive.  Notice:
 125          * these registers must be accessed byte-wise.  inw()/outw()
 126          * don't work.
 127          *
 128          * Make sure to turn off any level bits set for IRQs 9,10,11,15,
 129          *  so that the only bits getting set are for devices actually found.
 130          * Note that we do preserve the remainder of the bits, which we hope
 131          *  will be set correctly by ARC/SRM.
 132          *
 133          * Note: we at least preserve any level-set bits on AlphaBook1
 134          */
 135         old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 136
 137         level_bits |= (old_level_bits & 0x71ff);
 138
 139         outb((level_bits >> 0) & 0xff, 0x4d0);
 140         outb((level_bits >> 8) & 0xff, 0x4d1);
 141 }
 142
 143 static inline int __init
 144 noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 145 {
 146         /*
 147          * The Noname board has 5 PCI slots with each of the 4
 148          * interrupt pins routed to different pins on the PCI/ISA
 149          * bridge (PIRQ0-PIRQ3).  The table below is based on
 150          * information available at:
 151          *
 152          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 153          *
 154          * I have no information on the Avanti interrupt routing, but
 155          * the routing seems to be identical to the Noname except
 156          * that the Avanti has an additional slot whose routing I'm
 157          * unsure of.
 158          *
 159          * pirq_tab[0] is a fake entry to deal with old PCI boards
 160          * that have the interrupt pin number hardwired to 0 (meaning
 161          * that they use the default INTA line, if they are interrupt
 162          * driven at all).
 163          */
 164         static char irq_tab[][5] __initdata = {
 165                 /*INT A   B   C   D */
 166                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */
 167                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 168                 { 2,  2, -1, -1, -1}, /* idsel  8 (Hack: slot closest ISA) */
 169                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 170                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 171                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 172                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 173                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 174                 { 0,  0,  0,  0,  0}, /* idsel 14 AS255 TULIP */
 175         };
 176         const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
 177         int irq = COMMON_TABLE_LOOKUP, tmp;
 178         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 179         return irq >= 0 ? tmp : -1;
 180 }
 181
 182 static inline int __init
 183 p2k_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 184 {
 185         static char irq_tab[][5] __initdata = {
 186                 /*INT A   B   C   D */
 187                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 188                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 189                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 190                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 191                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 192                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 193                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 194         };
 195         const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
 196         int irq = COMMON_TABLE_LOOKUP, tmp;
 197         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 198         return irq >= 0 ? tmp : -1;
 199 }
 200
 201 static inline void __init
 202 noname_init_pci(void)
 203 {
 204         common_init_pci();
 205         sio_pci_route();
 206         sio_fixup_irq_levels(sio_collect_irq_levels());
 207         ns87312_enable_ide(0x26e);
 208 }
 209
 210 static inline void __init
 211 alphabook1_init_pci(void)
 212 {
 213         struct pci_dev *dev;
 214         unsigned char orig, config;
 215
 216         common_init_pci();
 217         sio_pci_route();
 218
 219         /*
 220          * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
 221          * is sensitive to PCI bus bursts, so we must DISABLE
 222          * burst mode for the NCR 8xx SCSI... :-(
 223          *
 224          * Note that the NCR810 SCSI driver must preserve the
 225          * setting of the bit in order for this to work.  At the
 226          * moment (2.0.29), ncr53c8xx.c does NOT do this, but
 227          * 53c7,8xx.c DOES.
 228          */
 229
 230         dev = NULL;
 231         while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
 232                 if (dev->device == PCI_DEVICE_ID_NCR_53C810
 233                     || dev->device == PCI_DEVICE_ID_NCR_53C815
 234                     || dev->device == PCI_DEVICE_ID_NCR_53C820
 235                     || dev->device == PCI_DEVICE_ID_NCR_53C825) {
 236                         unsigned long io_port;
 237                         unsigned char ctest4;
 238
 239                         io_port = dev->resource[0].start;
 240                         ctest4 = inb(io_port+0x21);
 241                         if (!(ctest4 & 0x80)) {
 242                                 printk("AlphaBook1 NCR init: setting"
 243                                        " burst disable\n");
 244                                 outb(ctest4 | 0x80, io_port+0x21);
 245                         }
 246                 }
 247         }
 248
 249         /* Do not set *ANY* level triggers for AlphaBook1. */
 250         sio_fixup_irq_levels(0);
 251
 252         /* Make sure that register PR1 indicates 1Mb mem */
 253         outb(0x0f, 0x3ce); orig = inb(0x3cf);   /* read PR5  */
 254         outb(0x0f, 0x3ce); outb(0x05, 0x3cf);   /* unlock PR0-4 */
 255         outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
 256         if ((config & 0xc0) != 0xc0) {
 257                 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
 258                 config |= 0xc0;
 259                 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
 260         }
 261         outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
 262 }
 263
 264 void
 265 sio_kill_arch(int mode)
 266 {
 267 #if defined(ALPHA_RESTORE_SRM_SETUP)
 268         /* Since we cannot read the PCI DMA Window CSRs, we
 269          * cannot restore them here.
 270          *
 271          * However, we CAN read the PIRQ route register, so restore it
 272          * now...
 273          */
 274         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
 275                                    saved_config.orig_route_tab);
 276 #endif
 277 }
 278
 279
 280 /*
 281  * The System Vectors
 282  */
 283
 284 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
 285 struct alpha_machine_vector alphabook1_mv __initmv = {
 286         .vector_name            = "AlphaBook1",
 287         DO_EV4_MMU,
 288         DO_DEFAULT_RTC,
 289         DO_LCA_IO,
 290         .machine_check          = lca_machine_check,
 291         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 292         .min_io_address         = DEFAULT_IO_BASE,
 293         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 294
 295         .nr_irqs                = 16,
 296         .device_interrupt       = isa_device_interrupt,
 297
 298         .init_arch              = alphabook1_init_arch,
 299         .init_irq               = sio_init_irq,
 300         .init_rtc               = common_init_rtc,
 301         .init_pci               = alphabook1_init_pci,
 302         .kill_arch              = sio_kill_arch,
 303         .pci_map_irq            = noname_map_irq,
 304         .pci_swizzle            = common_swizzle,
 305
 306         .sys = { .sio = {
 307                 /* NCR810 SCSI is 14, PCMCIA controller is 15.  */
 308                 .route_tab      = 0x0e0f0a0a,
 309         }}
 310 };
 311 ALIAS_MV(alphabook1)
 312 #endif
 313
 314 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
 315 struct alpha_machine_vector avanti_mv __initmv = {
 316         .vector_name            = "Avanti",
 317         DO_EV4_MMU,
 318         DO_DEFAULT_RTC,
 319         DO_APECS_IO,
 320         .machine_check          = apecs_machine_check,
 321         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 322         .min_io_address         = DEFAULT_IO_BASE,
 323         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 324
 325         .nr_irqs                = 16,
 326         .device_interrupt       = isa_device_interrupt,
 327
 328         .init_arch              = apecs_init_arch,
 329         .init_irq               = sio_init_irq,
 330         .init_rtc               = common_init_rtc,
 331         .init_pci               = noname_init_pci,
 332         .kill_arch              = sio_kill_arch,
 333         .pci_map_irq            = noname_map_irq,
 334         .pci_swizzle            = common_swizzle,
 335
 336         .sys = { .sio = {
 337                 .route_tab      = 0x0b0a0e0f,
 338         }}
 339 };
 340 ALIAS_MV(avanti)
 341 #endif
 342
 343 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
 344 struct alpha_machine_vector noname_mv __initmv = {
 345         .vector_name            = "Noname",
 346         DO_EV4_MMU,
 347         DO_DEFAULT_RTC,
 348         DO_LCA_IO,
 349         .machine_check          = lca_machine_check,
 350         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 351         .min_io_address         = DEFAULT_IO_BASE,
 352         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 353
 354         .nr_irqs                = 16,
 355         .device_interrupt       = srm_device_interrupt,
 356
 357         .init_arch              = lca_init_arch,
 358         .init_irq               = sio_init_irq,
 359         .init_rtc               = common_init_rtc,
 360         .init_pci               = noname_init_pci,
 361         .kill_arch              = sio_kill_arch,
 362         .pci_map_irq            = noname_map_irq,
 363         .pci_swizzle            = common_swizzle,
 364
 365         .sys = { .sio = {
 366                 /* For UDB, the only available PCI slot must not map to IRQ 9,
 367                    since that's the builtin MSS sound chip. That PCI slot
 368                    will map to PIRQ1 (for INTA at least), so we give it IRQ 15
 369                    instead.
 370
 371                    Unfortunately we have to do this for NONAME as well, since
 372                    they are co-indicated when the platform type "Noname" is
 373                    selected... :-(  */
 374
 375                 .route_tab      = 0x0b0a0f0d,
 376         }}
 377 };
 378 ALIAS_MV(noname)
 379 #endif
 380
 381 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
 382 struct alpha_machine_vector p2k_mv __initmv = {
 383         .vector_name            = "Platform2000",
 384         DO_EV4_MMU,
 385         DO_DEFAULT_RTC,
 386         DO_LCA_IO,
 387         .machine_check          = lca_machine_check,
 388         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 389         .min_io_address         = DEFAULT_IO_BASE,
 390         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 391
 392         .nr_irqs                = 16,
 393         .device_interrupt       = srm_device_interrupt,
 394
 395         .init_arch              = lca_init_arch,
 396         .init_irq               = sio_init_irq,
 397         .init_rtc               = common_init_rtc,
 398         .init_pci               = noname_init_pci,
 399         .kill_arch              = sio_kill_arch,
 400         .pci_map_irq            = p2k_map_irq,
 401         .pci_swizzle            = common_swizzle,
 402
 403         .sys = { .sio = {
 404                 .route_tab      = 0x0b0a090f,
 405         }}
 406 };
 407 ALIAS_MV(p2k)
 408 #endif
 409
 410 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
 411 struct alpha_machine_vector xl_mv __initmv = {
 412         .vector_name            = "XL",
 413         DO_EV4_MMU,
 414         DO_DEFAULT_RTC,
 415         DO_APECS_IO,
 416         .machine_check          = apecs_machine_check,
 417         .max_isa_dma_address    = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
 418         .min_io_address         = DEFAULT_IO_BASE,
 419         .min_mem_address        = XL_DEFAULT_MEM_BASE,
 420
 421         .nr_irqs                = 16,
 422         .device_interrupt       = isa_device_interrupt,
 423
 424         .init_arch              = apecs_init_arch,
 425         .init_irq               = sio_init_irq,
 426         .init_rtc               = common_init_rtc,
 427         .init_pci               = noname_init_pci,
 428         .kill_arch              = sio_kill_arch,
 429         .pci_map_irq            = noname_map_irq,
 430         .pci_swizzle            = common_swizzle,
 431
 432         .sys = { .sio = {
 433                 .route_tab      = 0x0b0a090f,
 434         }}
 435 };
 436 ALIAS_MV(xl)
 437 #endif