2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12 select BUILDTIME_EXTABLE_SORT
14 select CLONE_BACKWARDS
16 select GENERIC_ATOMIC64
17 select GENERIC_CLOCKEVENTS
18 select GENERIC_FIND_FIRST_BIT
19 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_PENDING_IRQ if SMP
23 select GENERIC_SMP_IDLE_THREAD
25 select HAVE_ARCH_TRACEHOOK
26 select HAVE_FUTEX_CMPXCHG
27 select HAVE_IOREMAP_PROT
29 select HAVE_KRETPROBES
31 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
33 select HAVE_PERF_EVENTS
34 select HANDLE_DOMAIN_IRQ
36 select MODULES_USE_ELF_RELA
39 select OF_EARLY_FLATTREE
40 select OF_RESERVED_MEM
41 select PERF_USE_VMALLOC
42 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_GENERIC_DMA_COHERENT
48 config TRACE_IRQFLAGS_SUPPORT
51 config LOCKDEP_SUPPORT
54 config SCHED_OMIT_FRAME_POINTER
60 config RWSEM_GENERIC_SPINLOCK
63 config ARCH_DISCONTIGMEM_ENABLE
66 config ARCH_FLATMEM_ENABLE
75 config GENERIC_CALIBRATE_DELAY
78 config GENERIC_HWEIGHT
81 config STACKTRACE_SUPPORT
85 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
90 source "kernel/Kconfig.freezer"
92 menu "ARC Architecture Configuration"
94 menu "ARC Platform/SoC/Board"
96 source "arch/arc/plat-sim/Kconfig"
97 source "arch/arc/plat-tb10x/Kconfig"
98 source "arch/arc/plat-axs10x/Kconfig"
99 #New platform adds here
100 source "arch/arc/plat-eznps/Kconfig"
105 prompt "ARC Instruction Set"
106 default ISA_ARCOMPACT
110 select CPU_NO_EFFICIENT_FFS
112 The original ARC ISA of ARC600/700 cores
117 ISA for the Next Generation ARC-HS cores
121 menu "ARC CPU Configuration"
125 default ARC_CPU_770 if ISA_ARCOMPACT
126 default ARC_CPU_HS if ISA_ARCV2
134 Support for ARC750 core
140 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
141 This core has a bunch of cool new features:
142 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
143 Shared Address Spaces (for sharing TLB entires in MMU)
144 -Caches: New Prog Model, Region Flush
145 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
153 Support for ARC HS38x Cores based on ARCv2 ISA
154 The notable features are:
155 - SMP configurations of upto 4 core with coherency
156 - Optional L2 Cache and IO-Coherency
157 - Revised Interrupt Architecture (multiple priorites, reg banks,
158 auto stack switch, auto regfile save/restore)
159 - MMUv4 (PIPT dcache, Huge Pages)
161 * 64bit load/store: LDD, STD
162 * Hardware assisted divide/remainder: DIV, REM
163 * Function prologue/epilogue: ENTER_S, LEAVE_S
164 * IRQ enable/disable: CLRI, SETI
165 * pop count: FFS, FLS
166 * SETcc, BMSKN, XBFU...
170 config CPU_BIG_ENDIAN
171 bool "Enable Big Endian Mode"
174 Build kernel for Big Endian Mode of ARC CPU
177 bool "Symmetric Multi-Processing"
179 select ARC_HAS_COH_CACHES if ISA_ARCV2
180 select ARC_MCIP if ISA_ARCV2
182 This enables support for systems with more than one CPU.
186 config ARC_HAS_COH_CACHES
189 config ARC_HAS_REENTRANT_IRQ_LV2
193 bool "ARConnect Multicore IP (MCIP) Support "
196 This IP block enables SMP in ARC-HS38 cores.
197 It provides for cross-core interrupts, multi-core debug
198 hardware semaphores, shared memory,....
201 int "Maximum number of CPUs (2-4096)"
205 config ARC_SMP_HALT_ON_RESET
206 bool "Enable Halt-on-reset boot mode"
207 default y if ARC_UBOOT_SUPPORT
209 In SMP configuration cores can be configured as Halt-on-reset
210 or they could all start at same time. For Halt-on-reset, non
211 masters are parked until Master kicks them so they can start of
212 at designated entry point. For other case, all jump to common
213 entry point and spin wait for Master's signal.
218 bool "Enable Cache Support"
220 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
221 depends on !SMP || ARC_HAS_COH_CACHES
225 config ARC_CACHE_LINE_SHIFT
226 int "Cache Line Length (as power of 2)"
230 Starting with ARC700 4.9, Cache line length is configurable,
231 This option specifies "N", with Line-len = 2 power N
232 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
233 Linux only supports same line lengths for I and D caches.
235 config ARC_HAS_ICACHE
236 bool "Use Instruction Cache"
239 config ARC_HAS_DCACHE
240 bool "Use Data Cache"
243 config ARC_CACHE_PAGES
244 bool "Per Page Cache Control"
246 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
248 This can be used to over-ride the global I/D Cache Enable on a
249 per-page basis (but only for pages accessed via MMU such as
250 Kernel Virtual address or User Virtual Address)
251 TLB entries have a per-page Cache Enable Bit.
252 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
253 Global DISABLE + Per Page ENABLE won't work
255 config ARC_CACHE_VIPT_ALIASING
256 bool "Support VIPT Aliasing D$"
257 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
265 Single Cycle RAMS to store Fast Path Code
269 int "ICCM Size in KB"
271 depends on ARC_HAS_ICCM
276 Single Cycle RAMS to store Fast Path Data
280 int "DCCM Size in KB"
282 depends on ARC_HAS_DCCM
285 hex "DCCM map address"
287 depends on ARC_HAS_DCCM
291 default ARC_MMU_V3 if ARC_CPU_770
292 default ARC_MMU_V2 if ARC_CPU_750D
293 default ARC_MMU_V4 if ARC_CPU_HS
305 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
306 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
310 depends on ARC_CPU_770
312 Introduced with ARC700 4.10: New Features
313 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
314 Shared Address Spaces (SASID)
326 prompt "MMU Page Size"
327 default ARC_PAGE_SIZE_8K
329 config ARC_PAGE_SIZE_8K
332 Choose between 8k vs 16k
334 config ARC_PAGE_SIZE_16K
336 depends on ARC_MMU_V3 || ARC_MMU_V4
338 config ARC_PAGE_SIZE_4K
340 depends on ARC_MMU_V3 || ARC_MMU_V4
345 prompt "MMU Super Page Size"
346 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
347 default ARC_HUGEPAGE_2M
349 config ARC_HUGEPAGE_2M
352 config ARC_HUGEPAGE_16M
358 int "Maximum NUMA Nodes (as a power of 2)"
359 default "1" if !DISCONTIGMEM
360 default "2" if DISCONTIGMEM
361 depends on NEED_MULTIPLE_NODES
363 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
368 config ARC_COMPACT_IRQ_LEVELS
369 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
371 # Timer HAS to be high priority, for any other high priority config
373 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
374 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
376 if ARC_COMPACT_IRQ_LEVELS
387 endif #ARC_COMPACT_IRQ_LEVELS
389 config ARC_FPU_SAVE_RESTORE
390 bool "Enable FPU state persistence across context switch"
393 Double Precision Floating Point unit had dedictaed regs which
394 need to be saved/restored across context-switch.
395 Note that ARC FPU is overly simplistic, unlike say x86, which has
396 hardware pieces to allow software to conditionally save/restore,
397 based on actual usage of FPU by a task. Thus our implemn does
398 this for all tasks in system.
406 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
408 depends on !ARC_CANT_LLSC
410 config ARC_STAR_9000923308
411 bool "Workaround for llock/scond livelock"
413 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
416 bool "Insn: SWAPE (endian-swap)"
422 bool "Insn: 64bit LDD/STD"
424 Enable gcc to generate 64-bit load/store instructions
425 ISA mandates even/odd registers to allow encoding of two
426 dest operands with 2 possible source operands.
429 config ARC_HAS_DIV_REM
430 bool "Insn: div, divu, rem, remu"
434 bool "Local 64-bit r/o cycle counter"
439 bool "SMP synchronized 64-bit cycle counter"
443 config ARC_NUMBER_OF_INTERRUPTS
444 int "Number of interrupts"
448 This defines the number of interrupts on the ARCv2HS core.
449 It affects the size of vector table.
450 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
451 in hardware, it keep things simple for Linux to assume they are always
456 endmenu # "ARC CPU Configuration"
458 config LINUX_LINK_BASE
459 hex "Linux Link Address"
462 ARC700 divides the 32 bit phy address space into two equal halves
463 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
464 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
465 Typically Linux kernel is linked at the start of untransalted addr,
466 hence the default value of 0x8zs.
467 However some customers have peripherals mapped at this addr, so
468 Linux needs to be scooted a bit.
469 If you don't know what the above means, leave this setting alone.
470 This needs to match memory start address specified in Device Tree
473 bool "High Memory Support"
476 With ARC 2G:2G address split, only upper 2G is directly addressable by
477 kernel. Enable this to potentially allow access to rest of 2G and PAE
481 bool "Support for the 40-bit Physical Address Extension"
485 Enable access to physical memory beyond 4G, only supported on
486 ARC cores with 40 bit Physical Addressing support
488 config ARCH_PHYS_ADDR_T_64BIT
489 def_bool ARC_HAS_PAE40
491 config ARCH_DMA_ADDR_T_64BIT
494 config ARC_PLAT_NEEDS_PHYS_TO_DMA
497 config ARC_KVADDR_SIZE
498 int "Kernel Virtaul Address Space size (MB)"
502 The kernel address space is carved out of 256MB of translated address
503 space for catering to vmalloc, modules, pkmap, fixmap. This however may
504 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
505 this to be stretched to 512 MB (by extending into the reserved
508 config ARC_CURR_IN_REG
509 bool "Dedicate Register r25 for current_task pointer"
512 This reserved Register R25 to point to Current Task in
513 kernel mode. This saves memory access for each such access
516 config ARC_EMUL_UNALIGNED
517 bool "Emulate unaligned memory access (userspace only)"
519 select SYSCTL_ARCH_UNALIGN_NO_WARN
520 select SYSCTL_ARCH_UNALIGN_ALLOW
521 depends on ISA_ARCOMPACT
523 This enables misaligned 16 & 32 bit memory access from user space.
524 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
525 potential bugs in code
528 int "Timer Frequency"
531 config ARC_METAWARE_HLINK
532 bool "Support for Metaware debugger assisted Host access"
535 This options allows a Linux userland apps to directly access
536 host file system (open/creat/read/write etc) with help from
537 Metaware Debugger. This can come in handy for Linux-host communication
538 when there is no real usable peripheral such as EMAC.
546 config ARC_DW2_UNWIND
547 bool "Enable DWARF specific kernel stack unwind"
551 Compiles the kernel with DWARF unwind information and can be used
552 to get stack backtraces.
554 If you say Y here the resulting kernel image will be slightly larger
555 but not slower, and it will give very useful debugging information.
556 If you don't debug the kernel, you can say N, but we may not be able
557 to solve problems without frame unwind information
559 config ARC_DBG_TLB_PARANOIA
560 bool "Paranoia Checks in Low Level TLB Handlers"
563 config ARC_DBG_TLB_MISS_COUNT
564 bool "Profile TLB Misses"
568 Counts number of I and D TLB Misses and exports them via Debugfs
569 The counters can be cleared via Debugfs as well
573 config ARC_UBOOT_SUPPORT
574 bool "Support uboot arg Handling"
577 ARC Linux by default checks for uboot provided args as pointers to
578 external cmdline or DTB. This however breaks in absence of uboot,
579 when booting from Metaware debugger directly, as the registers are
580 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
581 registers look like uboot args to kernel which then chokes.
582 So only enable the uboot arg checking/processing if users are sure
583 of uboot being in play.
585 config ARC_BUILTIN_DTB_NAME
586 string "Built in DTB"
588 Set the name of the DTB to embed in the vmlinux binary
589 Leaving it blank selects the minimal "skeleton" dtb
591 source "kernel/Kconfig.preempt"
593 menu "Executable file formats"
594 source "fs/Kconfig.binfmt"
597 endmenu # "ARC Architecture Configuration"
601 config FORCE_MAX_ZONEORDER
602 int "Maximum zone order"
603 default "12" if ARC_HUGEPAGE_16M
607 source "drivers/Kconfig"
612 bool "PCI support" if MIGHT_HAVE_PCI
614 PCI is the name of a bus system, i.e., the way the CPU talks to
615 the other stuff inside your box. Find out if your board/platform
618 Note: PCIe support for Synopsys Device will be available only
619 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
625 source "drivers/pci/Kconfig"
630 source "arch/arc/Kconfig.debug"
631 source "security/Kconfig"
632 source "crypto/Kconfig"
634 source "kernel/power/Kconfig"