2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12 select BUILDTIME_EXTABLE_SORT
14 select CLONE_BACKWARDS
16 select GENERIC_ATOMIC64
17 select GENERIC_CLOCKEVENTS
18 select GENERIC_FIND_FIRST_BIT
19 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_PENDING_IRQ if SMP
23 select GENERIC_SMP_IDLE_THREAD
25 select HAVE_ARCH_TRACEHOOK
26 select HAVE_FUTEX_CMPXCHG
27 select HAVE_IOREMAP_PROT
29 select HAVE_KRETPROBES
31 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
33 select HAVE_PERF_EVENTS
34 select HANDLE_DOMAIN_IRQ
36 select MODULES_USE_ELF_RELA
39 select OF_EARLY_FLATTREE
40 select OF_RESERVED_MEM
41 select PERF_USE_VMALLOC
42 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_GENERIC_DMA_COHERENT
48 config TRACE_IRQFLAGS_SUPPORT
51 config LOCKDEP_SUPPORT
54 config SCHED_OMIT_FRAME_POINTER
60 config RWSEM_GENERIC_SPINLOCK
63 config ARCH_DISCONTIGMEM_ENABLE
66 config ARCH_FLATMEM_ENABLE
75 config GENERIC_CALIBRATE_DELAY
78 config GENERIC_HWEIGHT
81 config STACKTRACE_SUPPORT
85 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
90 source "kernel/Kconfig.freezer"
92 menu "ARC Architecture Configuration"
94 menu "ARC Platform/SoC/Board"
96 source "arch/arc/plat-sim/Kconfig"
97 source "arch/arc/plat-tb10x/Kconfig"
98 source "arch/arc/plat-axs10x/Kconfig"
99 #New platform adds here
100 source "arch/arc/plat-eznps/Kconfig"
105 prompt "ARC Instruction Set"
106 default ISA_ARCOMPACT
111 The original ARC ISA of ARC600/700 cores
116 ISA for the Next Generation ARC-HS cores
120 menu "ARC CPU Configuration"
124 default ARC_CPU_770 if ISA_ARCOMPACT
125 default ARC_CPU_HS if ISA_ARCV2
133 Support for ARC750 core
139 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
140 This core has a bunch of cool new features:
141 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
142 Shared Address Spaces (for sharing TLB entires in MMU)
143 -Caches: New Prog Model, Region Flush
144 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
152 Support for ARC HS38x Cores based on ARCv2 ISA
153 The notable features are:
154 - SMP configurations of upto 4 core with coherency
155 - Optional L2 Cache and IO-Coherency
156 - Revised Interrupt Architecture (multiple priorites, reg banks,
157 auto stack switch, auto regfile save/restore)
158 - MMUv4 (PIPT dcache, Huge Pages)
160 * 64bit load/store: LDD, STD
161 * Hardware assisted divide/remainder: DIV, REM
162 * Function prologue/epilogue: ENTER_S, LEAVE_S
163 * IRQ enable/disable: CLRI, SETI
164 * pop count: FFS, FLS
165 * SETcc, BMSKN, XBFU...
169 config CPU_BIG_ENDIAN
170 bool "Enable Big Endian Mode"
173 Build kernel for Big Endian Mode of ARC CPU
176 bool "Symmetric Multi-Processing"
178 select ARC_HAS_COH_CACHES if ISA_ARCV2
179 select ARC_MCIP if ISA_ARCV2
181 This enables support for systems with more than one CPU.
185 config ARC_HAS_COH_CACHES
188 config ARC_HAS_REENTRANT_IRQ_LV2
192 bool "ARConnect Multicore IP (MCIP) Support "
195 This IP block enables SMP in ARC-HS38 cores.
196 It provides for cross-core interrupts, multi-core debug
197 hardware semaphores, shared memory,....
200 int "Maximum number of CPUs (2-4096)"
204 config ARC_SMP_HALT_ON_RESET
205 bool "Enable Halt-on-reset boot mode"
206 default y if ARC_UBOOT_SUPPORT
208 In SMP configuration cores can be configured as Halt-on-reset
209 or they could all start at same time. For Halt-on-reset, non
210 masters are parked until Master kicks them so they can start of
211 at designated entry point. For other case, all jump to common
212 entry point and spin wait for Master's signal.
217 bool "Enable Cache Support"
219 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
220 depends on !SMP || ARC_HAS_COH_CACHES
224 config ARC_CACHE_LINE_SHIFT
225 int "Cache Line Length (as power of 2)"
229 Starting with ARC700 4.9, Cache line length is configurable,
230 This option specifies "N", with Line-len = 2 power N
231 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
232 Linux only supports same line lengths for I and D caches.
234 config ARC_HAS_ICACHE
235 bool "Use Instruction Cache"
238 config ARC_HAS_DCACHE
239 bool "Use Data Cache"
242 config ARC_CACHE_PAGES
243 bool "Per Page Cache Control"
245 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
247 This can be used to over-ride the global I/D Cache Enable on a
248 per-page basis (but only for pages accessed via MMU such as
249 Kernel Virtual address or User Virtual Address)
250 TLB entries have a per-page Cache Enable Bit.
251 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
252 Global DISABLE + Per Page ENABLE won't work
254 config ARC_CACHE_VIPT_ALIASING
255 bool "Support VIPT Aliasing D$"
256 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
264 Single Cycle RAMS to store Fast Path Code
268 int "ICCM Size in KB"
270 depends on ARC_HAS_ICCM
275 Single Cycle RAMS to store Fast Path Data
279 int "DCCM Size in KB"
281 depends on ARC_HAS_DCCM
284 hex "DCCM map address"
286 depends on ARC_HAS_DCCM
290 default ARC_MMU_V3 if ARC_CPU_770
291 default ARC_MMU_V2 if ARC_CPU_750D
292 default ARC_MMU_V4 if ARC_CPU_HS
304 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
305 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
309 depends on ARC_CPU_770
311 Introduced with ARC700 4.10: New Features
312 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
313 Shared Address Spaces (SASID)
325 prompt "MMU Page Size"
326 default ARC_PAGE_SIZE_8K
328 config ARC_PAGE_SIZE_8K
331 Choose between 8k vs 16k
333 config ARC_PAGE_SIZE_16K
335 depends on ARC_MMU_V3 || ARC_MMU_V4
337 config ARC_PAGE_SIZE_4K
339 depends on ARC_MMU_V3 || ARC_MMU_V4
344 prompt "MMU Super Page Size"
345 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
346 default ARC_HUGEPAGE_2M
348 config ARC_HUGEPAGE_2M
351 config ARC_HUGEPAGE_16M
357 int "Maximum NUMA Nodes (as a power of 2)"
358 default "1" if !DISCONTIGMEM
359 default "2" if DISCONTIGMEM
360 depends on NEED_MULTIPLE_NODES
362 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
367 config ARC_COMPACT_IRQ_LEVELS
368 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
370 # Timer HAS to be high priority, for any other high priority config
372 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
373 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
375 if ARC_COMPACT_IRQ_LEVELS
386 endif #ARC_COMPACT_IRQ_LEVELS
388 config ARC_FPU_SAVE_RESTORE
389 bool "Enable FPU state persistence across context switch"
392 Double Precision Floating Point unit had dedictaed regs which
393 need to be saved/restored across context-switch.
394 Note that ARC FPU is overly simplistic, unlike say x86, which has
395 hardware pieces to allow software to conditionally save/restore,
396 based on actual usage of FPU by a task. Thus our implemn does
397 this for all tasks in system.
405 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
407 depends on !ARC_CANT_LLSC
409 config ARC_STAR_9000923308
410 bool "Workaround for llock/scond livelock"
412 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
415 bool "Insn: SWAPE (endian-swap)"
421 bool "Insn: 64bit LDD/STD"
423 Enable gcc to generate 64-bit load/store instructions
424 ISA mandates even/odd registers to allow encoding of two
425 dest operands with 2 possible source operands.
428 config ARC_HAS_DIV_REM
429 bool "Insn: div, divu, rem, remu"
433 bool "Local 64-bit r/o cycle counter"
438 bool "SMP synchronized 64-bit cycle counter"
442 config ARC_NUMBER_OF_INTERRUPTS
443 int "Number of interrupts"
447 This defines the number of interrupts on the ARCv2HS core.
448 It affects the size of vector table.
449 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
450 in hardware, it keep things simple for Linux to assume they are always
455 endmenu # "ARC CPU Configuration"
457 config LINUX_LINK_BASE
458 hex "Linux Link Address"
461 ARC700 divides the 32 bit phy address space into two equal halves
462 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
463 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
464 Typically Linux kernel is linked at the start of untransalted addr,
465 hence the default value of 0x8zs.
466 However some customers have peripherals mapped at this addr, so
467 Linux needs to be scooted a bit.
468 If you don't know what the above means, leave this setting alone.
469 This needs to match memory start address specified in Device Tree
472 bool "High Memory Support"
475 With ARC 2G:2G address split, only upper 2G is directly addressable by
476 kernel. Enable this to potentially allow access to rest of 2G and PAE
480 bool "Support for the 40-bit Physical Address Extension"
484 Enable access to physical memory beyond 4G, only supported on
485 ARC cores with 40 bit Physical Addressing support
487 config ARCH_PHYS_ADDR_T_64BIT
488 def_bool ARC_HAS_PAE40
490 config ARCH_DMA_ADDR_T_64BIT
493 config ARC_PLAT_NEEDS_PHYS_TO_DMA
496 config ARC_KVADDR_SIZE
497 int "Kernel Virtaul Address Space size (MB)"
501 The kernel address space is carved out of 256MB of translated address
502 space for catering to vmalloc, modules, pkmap, fixmap. This however may
503 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
504 this to be stretched to 512 MB (by extending into the reserved
507 config ARC_CURR_IN_REG
508 bool "Dedicate Register r25 for current_task pointer"
511 This reserved Register R25 to point to Current Task in
512 kernel mode. This saves memory access for each such access
515 config ARC_EMUL_UNALIGNED
516 bool "Emulate unaligned memory access (userspace only)"
518 select SYSCTL_ARCH_UNALIGN_NO_WARN
519 select SYSCTL_ARCH_UNALIGN_ALLOW
520 depends on ISA_ARCOMPACT
522 This enables misaligned 16 & 32 bit memory access from user space.
523 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
524 potential bugs in code
527 int "Timer Frequency"
530 config ARC_METAWARE_HLINK
531 bool "Support for Metaware debugger assisted Host access"
534 This options allows a Linux userland apps to directly access
535 host file system (open/creat/read/write etc) with help from
536 Metaware Debugger. This can come in handy for Linux-host communication
537 when there is no real usable peripheral such as EMAC.
545 config ARC_DW2_UNWIND
546 bool "Enable DWARF specific kernel stack unwind"
550 Compiles the kernel with DWARF unwind information and can be used
551 to get stack backtraces.
553 If you say Y here the resulting kernel image will be slightly larger
554 but not slower, and it will give very useful debugging information.
555 If you don't debug the kernel, you can say N, but we may not be able
556 to solve problems without frame unwind information
558 config ARC_DBG_TLB_PARANOIA
559 bool "Paranoia Checks in Low Level TLB Handlers"
562 config ARC_DBG_TLB_MISS_COUNT
563 bool "Profile TLB Misses"
567 Counts number of I and D TLB Misses and exports them via Debugfs
568 The counters can be cleared via Debugfs as well
572 config ARC_UBOOT_SUPPORT
573 bool "Support uboot arg Handling"
576 ARC Linux by default checks for uboot provided args as pointers to
577 external cmdline or DTB. This however breaks in absence of uboot,
578 when booting from Metaware debugger directly, as the registers are
579 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
580 registers look like uboot args to kernel which then chokes.
581 So only enable the uboot arg checking/processing if users are sure
582 of uboot being in play.
584 config ARC_BUILTIN_DTB_NAME
585 string "Built in DTB"
587 Set the name of the DTB to embed in the vmlinux binary
588 Leaving it blank selects the minimal "skeleton" dtb
590 source "kernel/Kconfig.preempt"
592 menu "Executable file formats"
593 source "fs/Kconfig.binfmt"
596 endmenu # "ARC Architecture Configuration"
600 config FORCE_MAX_ZONEORDER
601 int "Maximum zone order"
602 default "12" if ARC_HUGEPAGE_16M
606 source "drivers/Kconfig"
611 bool "PCI support" if MIGHT_HAVE_PCI
613 PCI is the name of a bus system, i.e., the way the CPU talks to
614 the other stuff inside your box. Find out if your board/platform
617 Note: PCIe support for Synopsys Device will be available only
618 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
624 source "drivers/pci/Kconfig"
629 source "arch/arc/Kconfig.debug"
630 source "security/Kconfig"
631 source "crypto/Kconfig"
633 source "kernel/power/Kconfig"