arch/arc/Kconfig

   1 #
   2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3 #
   4 # This program is free software; you can redistribute it and/or modify
   5 # it under the terms of the GNU General Public License version 2 as
   6 # published by the Free Software Foundation.
   7 #
   8
   9 config ARC
  10         def_bool y
  11         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
  12         select BUILDTIME_EXTABLE_SORT
  13         select COMMON_CLK
  14         select CLONE_BACKWARDS
  15         select GENERIC_ATOMIC64
  16         select GENERIC_CLOCKEVENTS
  17         select GENERIC_FIND_FIRST_BIT
  18         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
  19         select GENERIC_IRQ_SHOW
  20         select GENERIC_PCI_IOMAP
  21         select GENERIC_PENDING_IRQ if SMP
  22         select GENERIC_SMP_IDLE_THREAD
  23         select HAVE_ARCH_KGDB
  24         select HAVE_ARCH_TRACEHOOK
  25         select HAVE_FUTEX_CMPXCHG
  26         select HAVE_IOREMAP_PROT
  27         select HAVE_KPROBES
  28         select HAVE_KRETPROBES
  29         select HAVE_MEMBLOCK
  30         select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
  31         select HAVE_OPROFILE
  32         select HAVE_PERF_EVENTS
  33         select IRQ_DOMAIN
  34         select MODULES_USE_ELF_RELA
  35         select NO_BOOTMEM
  36         select OF
  37         select OF_EARLY_FLATTREE
  38         select PERF_USE_VMALLOC
  39         select HAVE_DEBUG_STACKOVERFLOW
  40         select HAVE_GENERIC_DMA_COHERENT
  41
  42 config MIGHT_HAVE_PCI
  43         bool
  44
  45 config TRACE_IRQFLAGS_SUPPORT
  46         def_bool y
  47
  48 config LOCKDEP_SUPPORT
  49         def_bool y
  50
  51 config SCHED_OMIT_FRAME_POINTER
  52         def_bool y
  53
  54 config GENERIC_CSUM
  55         def_bool y
  56
  57 config RWSEM_GENERIC_SPINLOCK
  58         def_bool y
  59
  60 config ARCH_FLATMEM_ENABLE
  61         def_bool y
  62
  63 config MMU
  64         def_bool y
  65
  66 config NO_IOPORT_MAP
  67         def_bool y
  68
  69 config GENERIC_CALIBRATE_DELAY
  70         def_bool y
  71
  72 config GENERIC_HWEIGHT
  73         def_bool y
  74
  75 config STACKTRACE_SUPPORT
  76         def_bool y
  77         select STACKTRACE
  78
  79 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
  80         def_bool y
  81         depends on ARC_MMU_V4
  82
  83 source "init/Kconfig"
  84 source "kernel/Kconfig.freezer"
  85
  86 menu "ARC Architecture Configuration"
  87
  88 menu "ARC Platform/SoC/Board"
  89
  90 source "arch/arc/plat-sim/Kconfig"
  91 source "arch/arc/plat-tb10x/Kconfig"
  92 source "arch/arc/plat-axs10x/Kconfig"
  93 #New platform adds here
  94
  95 endmenu
  96
  97 choice
  98         prompt "ARC Instruction Set"
  99         default ISA_ARCOMPACT
 100
 101 config ISA_ARCOMPACT
 102         bool "ARCompact ISA"
 103         help
 104           The original ARC ISA of ARC600/700 cores
 105
 106 config ISA_ARCV2
 107         bool "ARC ISA v2"
 108         help
 109           ISA for the Next Generation ARC-HS cores
 110
 111 endchoice
 112
 113 menu "ARC CPU Configuration"
 114
 115 choice
 116         prompt "ARC Core"
 117         default ARC_CPU_770 if ISA_ARCOMPACT
 118         default ARC_CPU_HS if ISA_ARCV2
 119
 120 if ISA_ARCOMPACT
 121
 122 config ARC_CPU_750D
 123         bool "ARC750D"
 124         select ARC_CANT_LLSC
 125         help
 126           Support for ARC750 core
 127
 128 config ARC_CPU_770
 129         bool "ARC770"
 130         select ARC_HAS_SWAPE
 131         help
 132           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
 133           This core has a bunch of cool new features:
 134           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
 135                    Shared Address Spaces (for sharing TLB entires in MMU)
 136           -Caches: New Prog Model, Region Flush
 137           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 138
 139 endif   #ISA_ARCOMPACT
 140
 141 config ARC_CPU_HS
 142         bool "ARC-HS"
 143         depends on ISA_ARCV2
 144         help
 145           Support for ARC HS38x Cores based on ARCv2 ISA
 146           The notable features are:
 147             - SMP configurations of upto 4 core with coherency
 148             - Optional L2 Cache and IO-Coherency
 149             - Revised Interrupt Architecture (multiple priorites, reg banks,
 150                 auto stack switch, auto regfile save/restore)
 151             - MMUv4 (PIPT dcache, Huge Pages)
 152             - Instructions for
 153                 * 64bit load/store: LDD, STD
 154                 * Hardware assisted divide/remainder: DIV, REM
 155                 * Function prologue/epilogue: ENTER_S, LEAVE_S
 156                 * IRQ enable/disable: CLRI, SETI
 157                 * pop count: FFS, FLS
 158                 * SETcc, BMSKN, XBFU...
 159
 160 endchoice
 161
 162 config CPU_BIG_ENDIAN
 163         bool "Enable Big Endian Mode"
 164         default n
 165         help
 166           Build kernel for Big Endian Mode of ARC CPU
 167
 168 config SMP
 169         bool "Symmetric Multi-Processing"
 170         default n
 171         select ARC_HAS_COH_CACHES if ISA_ARCV2
 172         select ARC_MCIP if ISA_ARCV2
 173         help
 174           This enables support for systems with more than one CPU.
 175
 176 if SMP
 177
 178 config ARC_HAS_COH_CACHES
 179         def_bool n
 180
 181 config ARC_HAS_REENTRANT_IRQ_LV2
 182         def_bool n
 183
 184 config ARC_MCIP
 185         bool "ARConnect Multicore IP (MCIP) Support "
 186         depends on ISA_ARCV2
 187         help
 188           This IP block enables SMP in ARC-HS38 cores.
 189           It provides for cross-core interrupts, multi-core debug
 190           hardware semaphores, shared memory,....
 191
 192 config NR_CPUS
 193         int "Maximum number of CPUs (2-4096)"
 194         range 2 4096
 195         default "4"
 196
 197 config ARC_SMP_HALT_ON_RESET
 198         bool "Enable Halt-on-reset boot mode"
 199         default y if ARC_UBOOT_SUPPORT
 200         help
 201           In SMP configuration cores can be configured as Halt-on-reset
 202           or they could all start at same time. For Halt-on-reset, non
 203           masters are parked until Master kicks them so they can start of
 204           at designated entry point. For other case, all jump to common
 205           entry point and spin wait for Master's signal.
 206
 207 endif   #SMP
 208
 209 menuconfig ARC_CACHE
 210         bool "Enable Cache Support"
 211         default y
 212         # if SMP, cache enabled ONLY if ARC implementation has cache coherency
 213         depends on !SMP || ARC_HAS_COH_CACHES
 214
 215 if ARC_CACHE
 216
 217 config ARC_CACHE_LINE_SHIFT
 218         int "Cache Line Length (as power of 2)"
 219         range 5 7
 220         default "6"
 221         help
 222           Starting with ARC700 4.9, Cache line length is configurable,
 223           This option specifies "N", with Line-len = 2 power N
 224           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
 225           Linux only supports same line lengths for I and D caches.
 226
 227 config ARC_HAS_ICACHE
 228         bool "Use Instruction Cache"
 229         default y
 230
 231 config ARC_HAS_DCACHE
 232         bool "Use Data Cache"
 233         default y
 234
 235 config ARC_CACHE_PAGES
 236         bool "Per Page Cache Control"
 237         default y
 238         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
 239         help
 240           This can be used to over-ride the global I/D Cache Enable on a
 241           per-page basis (but only for pages accessed via MMU such as
 242           Kernel Virtual address or User Virtual Address)
 243           TLB entries have a per-page Cache Enable Bit.
 244           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
 245           Global DISABLE + Per Page ENABLE won't work
 246
 247 config ARC_CACHE_VIPT_ALIASING
 248         bool "Support VIPT Aliasing D$"
 249         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 250         default n
 251
 252 endif   #ARC_CACHE
 253
 254 config ARC_HAS_ICCM
 255         bool "Use ICCM"
 256         help
 257           Single Cycle RAMS to store Fast Path Code
 258         default n
 259
 260 config ARC_ICCM_SZ
 261         int "ICCM Size in KB"
 262         default "64"
 263         depends on ARC_HAS_ICCM
 264
 265 config ARC_HAS_DCCM
 266         bool "Use DCCM"
 267         help
 268           Single Cycle RAMS to store Fast Path Data
 269         default n
 270
 271 config ARC_DCCM_SZ
 272         int "DCCM Size in KB"
 273         default "64"
 274         depends on ARC_HAS_DCCM
 275
 276 config ARC_DCCM_BASE
 277         hex "DCCM map address"
 278         default "0xA0000000"
 279         depends on ARC_HAS_DCCM
 280
 281 choice
 282         prompt "MMU Version"
 283         default ARC_MMU_V3 if ARC_CPU_770
 284         default ARC_MMU_V2 if ARC_CPU_750D
 285         default ARC_MMU_V4 if ARC_CPU_HS
 286
 287 if ISA_ARCOMPACT
 288
 289 config ARC_MMU_V1
 290         bool "MMU v1"
 291         help
 292           Orig ARC700 MMU
 293
 294 config ARC_MMU_V2
 295         bool "MMU v2"
 296         help
 297           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
 298           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
 299
 300 config ARC_MMU_V3
 301         bool "MMU v3"
 302         depends on ARC_CPU_770
 303         help
 304           Introduced with ARC700 4.10: New Features
 305           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 306           Shared Address Spaces (SASID)
 307
 308 endif
 309
 310 config ARC_MMU_V4
 311         bool "MMU v4"
 312         depends on ISA_ARCV2
 313
 314 endchoice
 315
 316
 317 choice
 318         prompt "MMU Page Size"
 319         default ARC_PAGE_SIZE_8K
 320
 321 config ARC_PAGE_SIZE_8K
 322         bool "8KB"
 323         help
 324           Choose between 8k vs 16k
 325
 326 config ARC_PAGE_SIZE_16K
 327         bool "16KB"
 328         depends on ARC_MMU_V3 || ARC_MMU_V4
 329
 330 config ARC_PAGE_SIZE_4K
 331         bool "4KB"
 332         depends on ARC_MMU_V3 || ARC_MMU_V4
 333
 334 endchoice
 335
 336 choice
 337         prompt "MMU Super Page Size"
 338         depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
 339         default ARC_HUGEPAGE_2M
 340
 341 config ARC_HUGEPAGE_2M
 342         bool "2MB"
 343
 344 config ARC_HUGEPAGE_16M
 345         bool "16MB"
 346
 347 endchoice
 348
 349 if ISA_ARCOMPACT
 350
 351 config ARC_COMPACT_IRQ_LEVELS
 352         bool "ARCompact IRQ Priorities: High(2)/Low(1)"
 353         default n
 354         # Timer HAS to be high priority, for any other high priority config
 355         select ARC_IRQ3_LV2
 356         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
 357         depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
 358
 359 if ARC_COMPACT_IRQ_LEVELS
 360
 361 config ARC_IRQ3_LV2
 362         bool
 363
 364 config ARC_IRQ5_LV2
 365         bool
 366
 367 config ARC_IRQ6_LV2
 368         bool
 369
 370 endif   #ARC_COMPACT_IRQ_LEVELS
 371
 372 config ARC_FPU_SAVE_RESTORE
 373         bool "Enable FPU state persistence across context switch"
 374         default n
 375         help
 376           Double Precision Floating Point unit had dedictaed regs which
 377           need to be saved/restored across context-switch.
 378           Note that ARC FPU is overly simplistic, unlike say x86, which has
 379           hardware pieces to allow software to conditionally save/restore,
 380           based on actual usage of FPU by a task. Thus our implemn does
 381           this for all tasks in system.
 382
 383 endif   #ISA_ARCOMPACT
 384
 385 config ARC_CANT_LLSC
 386         def_bool n
 387
 388 config ARC_HAS_LLSC
 389         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
 390         default y
 391         depends on !ARC_CANT_LLSC
 392
 393 config ARC_STAR_9000923308
 394         bool "Workaround for llock/scond livelock"
 395         default n
 396         depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
 397
 398 config ARC_HAS_SWAPE
 399         bool "Insn: SWAPE (endian-swap)"
 400         default y
 401
 402 if ISA_ARCV2
 403
 404 config ARC_HAS_LL64
 405         bool "Insn: 64bit LDD/STD"
 406         help
 407           Enable gcc to generate 64-bit load/store instructions
 408           ISA mandates even/odd registers to allow encoding of two
 409           dest operands with 2 possible source operands.
 410         default y
 411
 412 config ARC_HAS_DIV_REM
 413         bool "Insn: div, divu, rem, remu"
 414         default y
 415
 416 config ARC_HAS_RTC
 417         bool "Local 64-bit r/o cycle counter"
 418         default n
 419         depends on !SMP
 420
 421 config ARC_HAS_GFRC
 422         bool "SMP synchronized 64-bit cycle counter"
 423         default y
 424         depends on SMP
 425
 426 config ARC_NUMBER_OF_INTERRUPTS
 427         int "Number of interrupts"
 428         range 8 240
 429         default 32
 430         help
 431           This defines the number of interrupts on the ARCv2HS core.
 432           It affects the size of vector table.
 433           The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
 434           in hardware, it keep things simple for Linux to assume they are always
 435           present.
 436
 437 endif   # ISA_ARCV2
 438
 439 endmenu   # "ARC CPU Configuration"
 440
 441 config LINUX_LINK_BASE
 442         hex "Linux Link Address"
 443         default "0x80000000"
 444         help
 445           ARC700 divides the 32 bit phy address space into two equal halves
 446           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
 447           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
 448           Typically Linux kernel is linked at the start of untransalted addr,
 449           hence the default value of 0x8zs.
 450           However some customers have peripherals mapped at this addr, so
 451           Linux needs to be scooted a bit.
 452           If you don't know what the above means, leave this setting alone.
 453           This needs to match memory start address specified in Device Tree
 454
 455 config HIGHMEM
 456         bool "High Memory Support"
 457         help
 458           With ARC 2G:2G address split, only upper 2G is directly addressable by
 459           kernel. Enable this to potentially allow access to rest of 2G and PAE
 460           in future
 461
 462 config ARC_HAS_PAE40
 463         bool "Support for the 40-bit Physical Address Extension"
 464         default n
 465         depends on ISA_ARCV2
 466         help
 467           Enable access to physical memory beyond 4G, only supported on
 468           ARC cores with 40 bit Physical Addressing support
 469
 470 config ARCH_PHYS_ADDR_T_64BIT
 471         def_bool ARC_HAS_PAE40
 472
 473 config ARCH_DMA_ADDR_T_64BIT
 474         bool
 475
 476 config ARC_PLAT_NEEDS_PHYS_TO_DMA
 477         bool
 478
 479 config ARC_CURR_IN_REG
 480         bool "Dedicate Register r25 for current_task pointer"
 481         default y
 482         help
 483           This reserved Register R25 to point to Current Task in
 484           kernel mode. This saves memory access for each such access
 485
 486
 487 config ARC_EMUL_UNALIGNED
 488         bool "Emulate unaligned memory access (userspace only)"
 489         default N
 490         select SYSCTL_ARCH_UNALIGN_NO_WARN
 491         select SYSCTL_ARCH_UNALIGN_ALLOW
 492         depends on ISA_ARCOMPACT
 493         help
 494           This enables misaligned 16 & 32 bit memory access from user space.
 495           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
 496           potential bugs in code
 497
 498 config HZ
 499         int "Timer Frequency"
 500         default 100
 501
 502 config ARC_METAWARE_HLINK
 503         bool "Support for Metaware debugger assisted Host access"
 504         default n
 505         help
 506           This options allows a Linux userland apps to directly access
 507           host file system (open/creat/read/write etc) with help from
 508           Metaware Debugger. This can come in handy for Linux-host communication
 509           when there is no real usable peripheral such as EMAC.
 510
 511 menuconfig ARC_DBG
 512         bool "ARC debugging"
 513         default y
 514
 515 if ARC_DBG
 516
 517 config ARC_DW2_UNWIND
 518         bool "Enable DWARF specific kernel stack unwind"
 519         default y
 520         select KALLSYMS
 521         help
 522           Compiles the kernel with DWARF unwind information and can be used
 523           to get stack backtraces.
 524
 525           If you say Y here the resulting kernel image will be slightly larger
 526           but not slower, and it will give very useful debugging information.
 527           If you don't debug the kernel, you can say N, but we may not be able
 528           to solve problems without frame unwind information
 529
 530 config ARC_DBG_TLB_PARANOIA
 531         bool "Paranoia Checks in Low Level TLB Handlers"
 532         default n
 533
 534 config ARC_DBG_TLB_MISS_COUNT
 535         bool "Profile TLB Misses"
 536         default n
 537         select DEBUG_FS
 538         help
 539           Counts number of I and D TLB Misses and exports them via Debugfs
 540           The counters can be cleared via Debugfs as well
 541
 542 endif
 543
 544 config ARC_UBOOT_SUPPORT
 545         bool "Support uboot arg Handling"
 546         default n
 547         help
 548           ARC Linux by default checks for uboot provided args as pointers to
 549           external cmdline or DTB. This however breaks in absence of uboot,
 550           when booting from Metaware debugger directly, as the registers are
 551           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
 552           registers look like uboot args to kernel which then chokes.
 553           So only enable the uboot arg checking/processing if users are sure
 554           of uboot being in play.
 555
 556 config ARC_BUILTIN_DTB_NAME
 557         string "Built in DTB"
 558         help
 559           Set the name of the DTB to embed in the vmlinux binary
 560           Leaving it blank selects the minimal "skeleton" dtb
 561
 562 source "kernel/Kconfig.preempt"
 563
 564 menu "Executable file formats"
 565 source "fs/Kconfig.binfmt"
 566 endmenu
 567
 568 endmenu  # "ARC Architecture Configuration"
 569
 570 source "mm/Kconfig"
 571
 572 config FORCE_MAX_ZONEORDER
 573         int "Maximum zone order"
 574         default "12" if ARC_HUGEPAGE_16M
 575         default "11"
 576
 577 source "net/Kconfig"
 578 source "drivers/Kconfig"
 579
 580 menu "Bus Support"
 581
 582 config PCI
 583         bool "PCI support" if MIGHT_HAVE_PCI
 584         help
 585           PCI is the name of a bus system, i.e., the way the CPU talks to
 586           the other stuff inside your box.  Find out if your board/platform
 587           has PCI.
 588
 589           Note: PCIe support for Synopsys Device will be available only
 590           when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
 591           say Y, otherwise N.
 592
 593 config PCI_SYSCALL
 594         def_bool PCI
 595
 596 source "drivers/pci/Kconfig"
 597
 598 endmenu
 599
 600 source "fs/Kconfig"
 601 source "arch/arc/Kconfig.debug"
 602 source "security/Kconfig"
 603 source "crypto/Kconfig"
 604 source "lib/Kconfig"
 605 source "kernel/power/Kconfig"