arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         axs10x_mb {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0x00000000 0xe0000000 0x10000000>;
  17                 interrupt-parent = <&mb_intc>;
  18
  19                 clocks {
  20                         i2cclk: i2cclk {
  21                                 compatible = "fixed-clock";
  22                                 clock-frequency = <50000000>;
  23                                 #clock-cells = <0>;
  24                         };
  25
  26                         apbclk: apbclk {
  27                                 compatible = "fixed-clock";
  28                                 clock-frequency = <50000000>;
  29                                 #clock-cells = <0>;
  30                         };
  31
  32                         mmcclk: mmcclk {
  33                                 compatible = "fixed-clock";
  34                                 clock-frequency = <50000000>;
  35                                 #clock-cells = <0>;
  36                         };
  37
  38                         pguclk: pguclk {
  39                                 #clock-cells = <0>;
  40                                 compatible = "fixed-clock";
  41                                 clock-frequency = <74440000>;
  42                         };
  43                 };
  44
  45                 ethernet@0x18000 {
  46                         #interrupt-cells = <1>;
  47                         compatible = "snps,dwmac";
  48                         reg = < 0x18000 0x2000 >;
  49                         interrupts = < 4 >;
  50                         interrupt-names = "macirq";
  51                         phy-mode = "rgmii";
  52                         snps,pbl = < 32 >;
  53                         clocks = <&apbclk>;
  54                         clock-names = "stmmaceth";
  55                         max-speed = <100>;
  56                 };
  57
  58                 ehci@0x40000 {
  59                         compatible = "generic-ehci";
  60                         reg = < 0x40000 0x100 >;
  61                         interrupts = < 8 >;
  62                 };
  63
  64                 ohci@0x60000 {
  65                         compatible = "generic-ohci";
  66                         reg = < 0x60000 0x100 >;
  67                         interrupts = < 8 >;
  68                 };
  69
  70                 /*
  71                  * According to DW Mobile Storage databook it is required
  72                  * to use  "Hold Register" if card is enumerated in SDR12 or
  73                  * SDR25 modes.
  74                  *
  75                  * Utilization of "Hold Register" is already implemented via
  76                  * dw_mci_pltfm_prepare_command() which in its turn gets
  77                  * used through dw_mci_drv_data->prepare_command call-back.
  78                  * This call-back is used in Altera Socfpga platform and so
  79                  * we may reuse it saying that we're compatible with their
  80                  * "altr,socfpga-dw-mshc".
  81                  *
  82                  * Most probably "Hold Register" utilization is platform-
  83                  * independent requirement which means that single unified
  84                  * "snps,dw-mshc" should be enough for all users of DW MMC once
  85                  * dw_mci_pltfm_prepare_command() is used in generic platform
  86                  * code.
  87                  */
  88                 mmc@0x15000 {
  89                         compatible = "altr,socfpga-dw-mshc";
  90                         reg = < 0x15000 0x400 >;
  91                         num-slots = < 1 >;
  92                         fifo-depth = < 16 >;
  93                         card-detect-delay = < 200 >;
  94                         clocks = <&apbclk>, <&mmcclk>;
  95                         clock-names = "biu", "ciu";
  96                         interrupts = < 7 >;
  97                         bus-width = < 4 >;
  98                 };
  99
 100                 uart@0x20000 {
 101                         compatible = "snps,dw-apb-uart";
 102                         reg = <0x20000 0x100>;
 103                         clock-frequency = <33333333>;
 104                         interrupts = <17>;
 105                         baud = <115200>;
 106                         reg-shift = <2>;
 107                         reg-io-width = <4>;
 108                 };
 109
 110                 uart@0x21000 {
 111                         compatible = "snps,dw-apb-uart";
 112                         reg = <0x21000 0x100>;
 113                         clock-frequency = <33333333>;
 114                         interrupts = <18>;
 115                         baud = <115200>;
 116                         reg-shift = <2>;
 117                         reg-io-width = <4>;
 118                 };
 119
 120                 /* UART muxed with USB data port (ttyS3) */
 121                 uart@0x22000 {
 122                         compatible = "snps,dw-apb-uart";
 123                         reg = <0x22000 0x100>;
 124                         clock-frequency = <33333333>;
 125                         interrupts = <19>;
 126                         baud = <115200>;
 127                         reg-shift = <2>;
 128                         reg-io-width = <4>;
 129                 };
 130
 131                 i2c@0x1d000 {
 132                         compatible = "snps,designware-i2c";
 133                         reg = <0x1d000 0x100>;
 134                         clock-frequency = <400000>;
 135                         clocks = <&i2cclk>;
 136                         interrupts = <14>;
 137                 };
 138
 139                 i2c@0x1e000 {
 140                         compatible = "snps,designware-i2c";
 141                         reg = <0x1e000 0x100>;
 142                         clock-frequency = <400000>;
 143                         clocks = <&i2cclk>;
 144                         interrupts = <15>;
 145                 };
 146
 147                 i2c@0x1f000 {
 148                         compatible = "snps,designware-i2c";
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         reg = <0x1f000 0x100>;
 152                         clock-frequency = <400000>;
 153                         clocks = <&i2cclk>;
 154                         interrupts = <16>;
 155
 156                         adv7511:adv7511@39{
 157                                 compatible="adi,adv7511";
 158                                 reg = <0x39>;
 159                                 interrupts = <23>;
 160                                 adi,input-depth = <8>;
 161                                 adi,input-colorspace = "rgb";
 162                                 adi,input-clock = "1x";
 163                                 adi,clock-delay = <0x03>;
 164
 165                                 ports {
 166                                         #address-cells = <1>;
 167                                         #size-cells = <0>;
 168
 169                                         /* RGB/YUV input */
 170                                         port@0 {
 171                                                 reg = <0>;
 172                                                 adv7511_input:endpoint {
 173                                                 remote-endpoint = <&pgu_output>;
 174                                                 };
 175                                         };
 176
 177                                         /* HDMI output */
 178                                         port@1 {
 179                                                 reg = <1>;
 180                                                 adv7511_output: endpoint {
 181                                                         remote-endpoint = <&hdmi_connector_in>;
 182                                                 };
 183                                         };
 184                                 };
 185                         };
 186
 187                         eeprom@0x54{
 188                                 compatible = "24c01";
 189                                 reg = <0x54>;
 190                                 pagesize = <0x8>;
 191                         };
 192
 193                         eeprom@0x57{
 194                                 compatible = "24c04";
 195                                 reg = <0x57>;
 196                                 pagesize = <0x8>;
 197                         };
 198                 };
 199
 200                 hdmi0: connector {
 201                         compatible = "hdmi-connector";
 202                         type = "a";
 203                         port {
 204                                 hdmi_connector_in: endpoint {
 205                                         remote-endpoint = <&adv7511_output>;
 206                                 };
 207                         };
 208                 };
 209
 210                 gpio0:gpio@13000 {
 211                         compatible = "snps,dw-apb-gpio";
 212                         reg = <0x13000 0x1000>;
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215
 216                         gpio0_banka: gpio-controller@0 {
 217                                 compatible = "snps,dw-apb-gpio-port";
 218                                 gpio-controller;
 219                                 #gpio-cells = <2>;
 220                                 snps,nr-gpios = <32>;
 221                                 reg = <0>;
 222                         };
 223
 224                         gpio0_bankb: gpio-controller@1 {
 225                                 compatible = "snps,dw-apb-gpio-port";
 226                                 gpio-controller;
 227                                 #gpio-cells = <2>;
 228                                 snps,nr-gpios = <8>;
 229                                 reg = <1>;
 230                         };
 231
 232                         gpio0_bankc: gpio-controller@2 {
 233                                 compatible = "snps,dw-apb-gpio-port";
 234                                 gpio-controller;
 235                                 #gpio-cells = <2>;
 236                                 snps,nr-gpios = <8>;
 237                                 reg = <2>;
 238                         };
 239                 };
 240
 241                 gpio1:gpio@14000 {
 242                         compatible = "snps,dw-apb-gpio";
 243                         reg = <0x14000 0x1000>;
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246
 247                         gpio1_banka: gpio-controller@0 {
 248                                 compatible = "snps,dw-apb-gpio-port";
 249                                 gpio-controller;
 250                                 #gpio-cells = <2>;
 251                                 snps,nr-gpios = <30>;
 252                                 reg = <0>;
 253                         };
 254
 255                         gpio1_bankb: gpio-controller@1 {
 256                                 compatible = "snps,dw-apb-gpio-port";
 257                                 gpio-controller;
 258                                 #gpio-cells = <2>;
 259                                 snps,nr-gpios = <10>;
 260                                 reg = <1>;
 261                         };
 262
 263                         gpio1_bankc: gpio-controller@2 {
 264                                 compatible = "snps,dw-apb-gpio-port";
 265                                 gpio-controller;
 266                                 #gpio-cells = <2>;
 267                                 snps,nr-gpios = <8>;
 268                                 reg = <2>;
 269                         };
 270                 };
 271
 272                 pgu@17000 {
 273                         compatible = "snps,arcpgu";
 274                         reg = <0x17000 0x400>;
 275                         encoder-slave = <&adv7511>;
 276                         clocks = <&pguclk>;
 277                         clock-names = "pxlclk";
 278                         memory-region = <&frame_buffer>;
 279                         port {
 280                                 pgu_output: endpoint {
 281                                         remote-endpoint = <&adv7511_input>;
 282                                 };
 283                         };
 284                 };
 285         };
 286 };