2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 /include/ "skeleton_hs_idu.dtsi"
13 model = "snps,nsim_hs-smp";
14 compatible = "snps,nsim_hs";
15 interrupt-parent = <&core_intc>;
18 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
26 compatible = "simple-bus";
30 /* child and parent address space 1:1 mapped */
35 compatible = "fixed-clock";
36 clock-frequency = <80000000>;
39 core_intc: core-interrupt-controller {
40 compatible = "snps,archs-intc";
42 #interrupt-cells = <1>;
45 idu_intc: idu-interrupt-controller {
46 compatible = "snps,archs-idu-intc";
48 interrupt-parent = <&core_intc>;
51 * <hwirq distribution>
52 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
54 #interrupt-cells = <2>;
57 * upstream irqs to core intc - downstream these are
60 interrupts = <24 25 26 27 28 29 30 31>;
63 arcuart0: serial@c0fc1000 {
64 compatible = "snps,arc-uart";
65 reg = <0xc0fc1000 0x100>;
66 interrupt-parent = <&idu_intc>;
68 clock-frequency = <80000000>;
69 current-speed = <115200>;
74 compatible = "snps,archs-pct";
75 #interrupt-cells = <1>;